0ea7905395
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26432 a1c6a512-1295-4272-9138-f99709370657
752 lines
20 KiB
ArmAsm
752 lines
20 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Karl Kurbjun
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*
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* Arm bootloader and startup code based on startup.s from the iPodLinux
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* loader
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* Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
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* Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#define CACHE_NONE 0
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#define CACHE_ALL 0x0C
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#define BUFFERED 0x04
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/****************************************************************************/
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#ifdef TOSHIBA_GIGABEAT_F
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/* Clock and Power Management setup values */
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#define VAL_CLKDIV 0x7
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#define VAL_UPLLCON 0x0003C042
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#define VAL_MPLLCON 0x000C9042
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/* Memory Controller setup */
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/* Memory setup (taken from 0x5070) */
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/* BWSCON
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* Reserved 0
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* Bank 0:
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* Bus width 01 (16 bit)
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* Bank 1:
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* Buswidth 00 (8 bit)
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* Disable wait 0
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* Not using UB/LB 0
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* Bank 2:
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* Buswidth 10 (32 bit)
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* Disable wait 0
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* Not using UB/LB 0
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* Bank 3:
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* Buswidth 10 (32 bit)
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* Disable wait 0
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* Use UB/LB 1
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* Bank 4:
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* Buswidth 10 (32 bit)
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* Disable wait 0
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* Use UB/LB 1
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* Bank 5:
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* Buswidth 00 (8 bit)
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* Disable wait 0
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* Not using UB/LB 0
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* Bank 6:
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* Buswidth 10 (32 bit)
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* Disable wait 0
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* Not using UB/LB 0
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* Bank 7:
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* Buswidth 00 (8 bit)
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* Disable wait 0
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* Not using UB/LB 0
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*/
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#define VAL_BWSCON 0x01055102
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/* BANKCON0
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* Pagemode: normal (1 data) 00
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* Pagemode access cycle: 2 clocks 00
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* Address hold: 2 clocks 10
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* Chip selection hold time: 1 clock 10
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* Access cycle: 8 clocks 101
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* Chip select setup time: 1 clock 01
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* Address setup time: 0 clock 00
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*/
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#define VAL_BANKCON0 0x00000D60
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/* BANKCON1
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* Pagemode: normal (1 data) 00
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* Pagemode access cycle: 2 clocks 00
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* Address hold: 0 clocks 00
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* Chip selection hold time: 0 clock 00
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* Access cycle: 1 clocks 000
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* Chip select setup time: 0 clocks 00
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* Address setup time: 0 clocks 00
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*/
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#define VAL_BANKCON1 0x00000000
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/* BANKCON2
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* Pagemode: normal (1 data) 00
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* Pagemode access cycle: 2 clocks 00
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* Address hold: 2 clocks 10
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* Chip selection hold time: 2 clocks 10
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* Access cycle: 14 clocks 111
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* Chip select setup time: 4 clocks 11
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* Address setup time: 0 clocks 00
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*/
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#define VAL_BANKCON2 0x00001FA0
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#define VAL_BANKCON3 0x00001D80
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#define VAL_BANKCON4 0x00001D80
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#define VAL_BANKCON5 0x00000000
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/* BANKCON6/7
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* SCAN: 9 bit 01
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* Trcd: 3 clocks 01
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* Tcah: 0 clock 00
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* Tcoh: 0 clock 00
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* Tacc: 1 clock 000
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* Tcos: 0 clock 00
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* Tacs: 0 clock 00
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* MT: Sync DRAM 11
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*/
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#define VAL_BANKCON6 0x00018005
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#define VAL_BANKCON7 0x00018005
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#define VAL_REFRESH 0x00980501
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/* BANKSIZE
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* BK76MAP: 32M/32M 000
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* Reserved: 0 0 (was 1)
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* SCLK_EN: always 1 (was 0)
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* SCKE_EN: disable 0
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* Reserved: 0 0
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* BURST_EN: enabled 1
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*/
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#define VAL_BANKSIZE 0x00000090
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#define VAL_MRSRB6 0x00000030
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#define VAL_MRSRB7 0x00000030
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#define VAL_GPACON 0x00FFFFFF
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/****************************************************************************/
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#elif defined (MINI2440)
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/* For Mini2440 board or compatible */
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/* Clock and Power Management setup values */
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/* NB: clock settings must match values in s3c2440/system-target.h */
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#define VAL_CLKDIV 0x5 /* HCLK = FCLK/4, PCLK = HCLK/2 */
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#define VAL_UPLLCON 0x00038022 /* UCLK = 48 MHz */
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#define VAL_MPLLCON 0x000C3041 /* FCLK = 406 MHz */
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/* Memory Controller setup */
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#define VAL_BWSCON 0x22111112
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#define VAL_BANKCON0 0x00002F50
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#define VAL_BANKCON1 0x00000700
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#define VAL_BANKCON2 0x00000700
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#define VAL_BANKCON3 0x00000700
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#define VAL_BANKCON4 0x00000700
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#define VAL_BANKCON5 0x0007FFFC
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#define VAL_BANKCON6 0x00018009
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#define VAL_BANKCON7 0x00018009
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#define VAL_REFRESH 0x008E04EB
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#define VAL_BANKSIZE 0x000000B2
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#define VAL_MRSRB6 0x00000030
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#define VAL_MRSRB7 0x00000030
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#define VAL_GPACON 0x00FFFFFF
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#define VAL_GPFCON 0x000055AA
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#define VAL_GPGCON 0xAA2A0128
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#define VAL_GPGDAT 0x0000
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#else
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#error Unknown target
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#endif
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/****************************************************************************/
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/* Exception Handlers */
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.section .vectors,"ax",%progbits
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.code 32
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.global vectors
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vectors:
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b start
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b undef_instr_handler
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b software_int_handler
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b prefetch_abort_handler
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b data_abort_handler
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b reserved_handler
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b irq_handler
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b fiq_handler
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/* This branch is used to make sure that we know where the shutdown routine
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* is located in flash (0x040A0020)
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*/
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b rom_shutdown
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/* Add some strings to detect the bootloader in flash and give it a version
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* number. (0x040A0028, 0x040A002C)
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*/
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.string "ROCKBOX\0"
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.string "R 03.00\0"
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/*
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* Function: word_copy
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* Variables:
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* r0 = from
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* r1 = to
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* r2 = length
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*/
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.section .init.text, "ax", %progbits
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.align 0x04
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.global word_copy
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.type word_copy, %function
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word_copy:
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subs r2, r2, #0x04
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ldrge r3, [r0], #4
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strge r3, [r1], #4
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bgt word_copy
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bx lr
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.ltorg
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.size word_copy, .-word_copy
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/*
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* Entry: start
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* Variables:
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* none
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*/
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.section .init.text,"ax",%progbits
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.code 32
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.align 0x04
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.global start
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start:
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/* Get the execute address; R0 is used to store the address and it should
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* not be written to till the rest of the execution checks are done below.
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* This is done first thing since we have to check if the code was started
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* with the old rockbox bootloader that offset the image by 100 bytes.
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*/
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ldr r0, =0xffffff00
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and r0, pc, r0
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/************************** DO NOT WRITE TO R0 ***************************/
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#ifdef TOSHIBA_GIGABEAT_F
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/* Check if the code is running from flash. If not skip all these checks */
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cmp r0, #0xA0000
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bne poweron
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/* Point LCDSADDR1 to the boot logo for lcd_init_device in lcd-meg-fx.c */
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mov r2, #0x4D000000
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ldr r1, =0x020200A8
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str r1, [r2, #0x14]
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/* Did an RTC event wake the player up? */
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mov r2, #0x4A000000
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ldr r1, [r2]
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ands r1, r1, #0x40000000
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/* Store a flag in GSTATUS3 to indicate that the bootloader is flashed */
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ldr r2, =0x560000b8
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mov r1, #0x02
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/* Woke up with the alarm? - store a flag in GSTATUS3 */
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orrne r1, r1, #0x01
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str r1, [r2]
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bne poweron
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/* Set GPG up to read power and menu status */
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ldr r2, =0x56000050
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ldr r1, [r2, #0x18]
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orr r1, r1, #0x03
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str r1, [r2, #0x18]
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/* Check if menu is held down */
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ldr r1, [r2, #0x14]
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ands r3, r1, #0x02
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bne bootOF
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/* Check if power is held down */
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ands r3, r1, #0x01
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bne poweron
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/* Set GPF up to read charger connection if power is not held down */
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ldr r1, [r2, #0x08]
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orr r1, r1, #0x10
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str r1, [r2, #0x08]
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/* Check if charger is connected */
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ldr r1, [r2, #0x04]
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ands r1, r1, #0x10
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beq poweron
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bootOF:
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/* power is not down || menu is held || the charger is not connected */
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mov pc, #0x70
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#endif
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poweron:
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/* enter supervisor mode, disable IRQ */
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msr cpsr, #0xd3
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/* Disable the watchdog */
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ldr r2, =0x00000000
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mov r1, #0x53000000
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str r2, [r1]
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/* Mask all Interupts to be safe */
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ldr r2, =0xFFFFFFFF
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mov r1, #0x4A000000
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str r2, [r1, #0x08]
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/* Submask too */
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ldr r2, =0x00003FFF
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str r2, [r1, #0x1C]
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#ifdef TOSHIBA_GIGABEAT_F
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/* Check if loaded by the old bootloader or by the OF. This copy routine
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* cannot run/copy properly until the memory has been initialized, so the
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* copy routine later is still necessary. The old bootloader/OF will
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* initialize the memory.
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*/
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/* Calculate the length of the code needed to run/copy */
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ldr r1, = _vectorstart
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ldr r2, = _initdata_end
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sub r2, r2, r1
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add r3, r2, #0x30000000
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/* Is there enough space to copy without overwriting? */
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cmp r0, r3
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/* There's enough space, skip copying */
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bgt skipreset
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/* Is this code running from 0xA0000? If so skip copy. */
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cmplt r0, #0xA0000
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beq skipreset
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/****************************** OK TO USE R0 *****************************/
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/* There's not enough space to copy without overwriting, copy to safe
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* spot and reset
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*/
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mov r1, #0x31000000 /* copy location */
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bl word_copy
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mov pc, #0x31000000
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#endif
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skipreset:
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/* Initial Clock Setup */
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/* set Bus to Asynchronous mode (full speed) */
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mov r0, #0
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =0xC0000000
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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mov r2, #VAL_CLKDIV
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mov r1, #0x4C000000
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str r2, [r1, #0x14]
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mov r2, #0x0
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str r2, [r1, #0x18]
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ldr r2, =0xFFFFFFFF
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str r2, [r1]
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ldr r2, =VAL_UPLLCON
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str r2, [r1, #0x08]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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ldr r2, =VAL_MPLLCON
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str r2, [r1, #0x04]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* Setup MISCCR */
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ldr r2, =0x00613020
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mov r1, #0x56000000
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str r2, [r1, #0x80]
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/* Memory setup */
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ldr r2, =VAL_BWSCON
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mov r1, #0x48000000
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str r2, [r1]
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/* BANKCON0 */
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ldr r2, =VAL_BANKCON0
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str r2, [r1, #0x04]
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/* BANKCON1 */
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ldr r2, =VAL_BANKCON1
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str r2, [r1, #0x08]
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/* BANKCON2 */
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ldr r2, =VAL_BANKCON2
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str r2, [r1, #0xC]
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/* BANKCON3 */
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ldr r2, =VAL_BANKCON3
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str r2, [r1, #0x10]
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/* BANKCON4 */
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str r2, [r1, #0x14]
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/* BANKCON5 */
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ldr r2, =VAL_BANKCON5
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str r2, [r1, #0x18]
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/* BANKCON6/7 */
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ldr r2, =VAL_BANKCON6
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str r2, [r1, #0x1C]
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/* BANKCON7 */
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str r2, [r1, #0x20]
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/* REFRESH */
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ldr r2, =VAL_REFRESH
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str r2, [r1, #0x24]
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/* BANKSIZE */
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ldr r2, =VAL_BANKSIZE
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str r2, [r1, #0x28]
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/* MRSRB6 */
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ldr r2, =VAL_MRSRB6
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str r2, [r1, #0x2C]
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/* MRSRB7 */
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str r2, [r1, #0x30]
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/* RMC: I guess this is some notes about Gigabeat */
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/*
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0x56000000 0x1FFFCFF
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4 0x1FFFEFF
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0X4800002C 0X0
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0X560000
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*/
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/* GPACON */
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mov r1, #0x56000000
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ldr r2, =VAL_GPACON
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str r2, [r1]
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#if 0
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/* GPGCON */
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ldr r2, =VAL_GPGCON
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str r2, [r1, #0x60]
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ldr r2, =VAL_GPGDAT
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str r2, [r1, #0x64]
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#endif
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/* Copy from current location (from NOR Flash if bootloader, load buffer if
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firmware) to RAM */
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/* Gigabeat: The builds have two potential load addresses, one being from flash,
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* and the other from some "unknown" location right now the assumption
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* is that the code is not at 0x3000000.
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*/
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/* get the high part of our execute address (where am I) */
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ldr r0, =0xfffff000
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and r0, pc, r0 /* copy from address */
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/* SDRAM starts at 0x30000000 (physical address) */
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ldr r1, =0x30000000 /* copy To address */
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ldr r2, = _vectorstart
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ldr r3, = _initdata_end
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sub r2, r3, r2 /* length of loader */
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bl word_copy
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ldr r1, =donecopy
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ldr r2, =0x30000000
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add r1, r1, r2
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bx r1 /* The code is located where we want it so jump */
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donecopy:
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/* Setup the MMU, start by disabling */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x5 /* disable mmu and dcache */
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bic r0, r0, #0x1000 /* disable icache */
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mcr p15, 0, r0, c1, c0, 0
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bl ttb_init
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ldr r0, =0x0
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ldr r1, =0x0
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ldr r2, =0x1000
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mov r3, #CACHE_NONE
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bl map_section
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ldr r0, =0x30000000
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ldr r1, =0x0
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mov r2, #MEMORYSIZE
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mov r3, #CACHE_ALL
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bl map_section
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ldr r0, =LCD_FRAME_ADDR /* LCD Frame buffer */
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mov r1, r0
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mov r2, #1
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mov r3, #BUFFERED
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bl map_section
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bl enable_mmu
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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bsszero:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi bsszero
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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mov r3, sp
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ldr r2, =stackbegin
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ldr r4, =0xdeadbeef
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stackmunge:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi stackmunge
|
|
|
|
/* Set up stack for IRQ mode */
|
|
msr cpsr_c, #0xd2
|
|
ldr sp, =irq_stack
|
|
/* Set up stack for FIQ mode */
|
|
msr cpsr_c, #0xd1
|
|
ldr sp, =fiq_stack
|
|
|
|
/* Let abort and undefined modes use IRQ stack */
|
|
msr cpsr_c, #0xd7
|
|
ldr sp, =irq_stack
|
|
msr cpsr_c, #0xdb
|
|
ldr sp, =irq_stack
|
|
/* Switch to supervisor mode */
|
|
msr cpsr_c, #0xd3
|
|
ldr sp, =stackend
|
|
|
|
/* Start the main function */
|
|
ldr lr, =vectors
|
|
ldr pc, =main
|
|
|
|
/* Should never get here, but let's restart in case (also needed for
|
|
* linking)
|
|
*/
|
|
b vectors
|
|
|
|
/* All illegal exceptions call into UIE with exception address as first
|
|
parameter. This is calculated differently depending on which exception
|
|
we're in. Second parameter is exception number, used for a string lookup
|
|
in UIE.
|
|
*/
|
|
undef_instr_handler:
|
|
sub r0, lr, #4
|
|
mov r1, #0
|
|
b UIE
|
|
|
|
/* We run supervisor mode most of the time, and should never see a software
|
|
exception being thrown. Perhaps make it illegal and call UIE?
|
|
*/
|
|
software_int_handler:
|
|
reserved_handler:
|
|
movs pc, lr
|
|
|
|
prefetch_abort_handler:
|
|
sub r0, lr, #4
|
|
mov r1, #1
|
|
b UIE
|
|
|
|
data_abort_handler:
|
|
sub r0, lr, #8
|
|
mov r1, #2
|
|
b UIE
|
|
|
|
#if defined(BOOTLOADER)
|
|
fiq_handler:
|
|
b UIE
|
|
#endif
|
|
|
|
UIE:
|
|
b UIE
|
|
|
|
/* TODO: Review this function - is it target dependent? */
|
|
/*
|
|
* Function: rom_shutdown
|
|
* Variables:
|
|
* none
|
|
*/
|
|
|
|
.section .init.text, "ax", %progbits
|
|
.align 0x04
|
|
.global rom_shutdown
|
|
.type rom_shutdown, %function
|
|
rom_shutdown:
|
|
/* Turn off the MMU */
|
|
mrc p15, 0, r1, c1, c0, 0
|
|
bic r1, r1, #0x0001
|
|
mcr p15, 0, r1, c1, c0, 0
|
|
|
|
/* Taken from 0x10010 */
|
|
ldr r2, =0x56000014 //GPBDAT
|
|
ldr r1, =0x56000010 //GPBCON
|
|
ldr r3, =0x00015450
|
|
ldr r8, =0x56000024 //GPCDAT
|
|
ldr r10, =0x56000020 //GPCCON
|
|
ldr r5, =0xAAA054A8
|
|
ldr r6, =0x56000024 //GPDDAT
|
|
ldr r7, =0x56000030 //GPDCON
|
|
ldr r12, =0x56000044 //GPEDAT
|
|
ldr lr, =0x56000040 //GPECON
|
|
ldr r0, =0x56000054 //GPFDAT
|
|
mov r4, #0
|
|
str r4, [r2]
|
|
str r3, [r1]
|
|
ldr r1, =0xAAA0AAA5
|
|
ldr r2, =0xAA8002AA
|
|
mov r3, #0x80
|
|
str r3, [r8]
|
|
add r3, r3, #0x980
|
|
str r5, [r10]
|
|
mov r5, #4
|
|
str r4, [r6]
|
|
str r1, [r7]
|
|
str r4, [r12]
|
|
str r2, [lr]
|
|
str r4, [r0],#(0x56000064-0x56000054) //(GPGDAT - GPFDAT)
|
|
add r12, r12, #(0x56000060-0x56000044)//(GPGCON - GPEDAT)
|
|
ldr r1, =0x56000050 //GPFCON
|
|
ldr r2, =0x01401002
|
|
mov lr, #0xFFFFFFFF
|
|
str r3, [r1],#(0x56000074-0x56000050)// (GPHDAT - GPFCON)
|
|
str r4, [r0],#(0x56000060-0x56000054)// (GPGCON - GPFDAT)
|
|
// str r2, [r12]
|
|
ldr r2, =0x140A5
|
|
mov r3, #0x81
|
|
str r3, [r1]
|
|
ldr r12, =0x4A000008 //INTMSK
|
|
|
|
// mov r3, #0x200000 // disable EINT13
|
|
ldr r3, =0xFFFFFECF
|
|
|
|
str r2, [r0] // GPFDAT=0x140A5
|
|
ldr r2, =0x56000088 //EXTINT0
|
|
ldr r0, =0x4A000010 //INTPND
|
|
|
|
add r1, r1, #(0x56000068 - 0x56000050) // (GPGUP - GPFCON) (0x18)
|
|
str lr, [r12] /* INTMSK = 0xFFFFFFFF */
|
|
str r3, [r2],#(0x560000A4 - 0x56000088) // (EINTMASK - EXTINT0) disable EINT13 (0x1C)
|
|
// mov r3, #0xFFFFFECF
|
|
mov r3, #0xFFFFFEFF
|
|
str r5, [r1],#(0x56000074-0x56000058) //(GPHDAT - GPFUP) (0x1C) DCLKCON
|
|
str r3, [r2]
|
|
|
|
ldr r11, =0x56000060
|
|
ldr r6, =0x01401002
|
|
str r6, [r11]
|
|
|
|
// add r3, r3, #0x00000100
|
|
ldr r3, =0xFFFFFFDF;
|
|
str r3, [r12] // disable INT_TICK
|
|
|
|
mov r3, #0x4A000000
|
|
add r2, r2, #(0x560000B0-0x56000088) //(GSTATUS1 - EXTINT0) //; 0x600 (0x28)
|
|
str lr, [r1]
|
|
str lr, [r3]
|
|
mov r3, #0x600
|
|
str lr, [r0]
|
|
str r3, [r2] // GSTATUS1 = 0x600 /* what for ??? */
|
|
|
|
ldr r12, =0x56000080 //MISCCr
|
|
mov r2, #0x58000000 //ADCCON
|
|
str r5, [r2]
|
|
add r2, r2, #(0x4D000000-0x58000000) //(LCDCON1 - ADCCON) // LCDCON1 (0xF5000000)
|
|
ldr r3, [r12]
|
|
ldr r0, =0x48000024 // REFRESH
|
|
bic r3, r3, #0x700000
|
|
bic r3, r3, #0x3000
|
|
orr r3, r3, #0x600000
|
|
orr r3, r3, #0x3000
|
|
str r3, [r12] // MISCCR = (MISCCR & ~0x100000) | 0x603000;
|
|
/* clear [20] BATTFLT_FUNC - BATT_FLT function On/Off.
|
|
* 0, Battery fault function will be turned on.
|
|
* set [21] BATTFLT_INTR - BATT_FLT Interrupt On/Off.
|
|
* 1, Battery fault interrupt will be masked by hardware.
|
|
* set [13] SEL_SUSPND1 - USB Port 1 Suspend mode
|
|
* 1= suspend mode
|
|
* set [12] SEL_SUSPND0 - USB Port 0 Suspend mode
|
|
* 1= suspend mode
|
|
*/
|
|
mov r3, #0x4C000000 // LOCKTIME
|
|
str r4, [r2]
|
|
|
|
str lr, [r3]
|
|
ldr r1, [r0]
|
|
ldr lr, =0x4C00000C // CLKCON
|
|
// str r1, [r11,#-0x28]
|
|
ldr r2, [lr]
|
|
// str r2, [r11,#-0x28]
|
|
ldr r3, [r0]
|
|
orr r3, r3, #0x00C00000
|
|
/* REFRESH
|
|
* [22] TREFMD - SDRAM Refresh Mode
|
|
*/
|
|
str r3, [r0]
|
|
ldr r2, [r12]
|
|
|
|
ldr r3, =0x00004018
|
|
/* [3] SLEEP - Control SLEEP mode of S3C2440X.
|
|
* [4] NAND - Control HCLK into NAND Flash Controller block.
|
|
* [14] RTC - Control PCLK into RTC control block.
|
|
*/
|
|
orr r2, r2, #0x000E0000
|
|
/* [17] nEN_SCLK0 - SCLK0 output enable (1: SCLK 0 = 0)
|
|
* [18] nEN_SCLK1 - SCLK1 output enable (1: SCLK 1 = 0)
|
|
* [19] OFFREFRESH - Self refresh retain enable after wake-up from sleep
|
|
*/
|
|
|
|
str r2, [r12]
|
|
str r3, [lr]
|
|
|
|
1:
|
|
b 1b
|
|
.ltorg
|
|
.size rom_shutdown, .-rom_shutdown
|
|
|
|
.section .text
|
|
/* 256 words of IRQ stack */
|
|
.space 256*4
|
|
irq_stack:
|
|
|
|
/* 256 words of FIQ stack */
|
|
.space 256*4
|
|
fiq_stack:
|
|
|