f64e8dc33c
I think this covers everything now, although some fields are missing enum values. Those can be added in if and when they are needed. Change-Id: Ib1a94ba9c9a5949b6a038f8c1a49786823fae58f
323 lines
15 KiB
C
323 lines
15 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* x1000 version: 1.0
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* x1000 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_SSI_H__
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#define __HEADERGEN_SSI_H__
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#include "macro.h"
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#define REG_SSI_DR jz_reg(SSI_DR)
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#define JA_SSI_DR (0xb0043000 + 0x0)
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#define JT_SSI_DR JIO_32_RW
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#define JN_SSI_DR SSI_DR
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#define JI_SSI_DR
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#define REG_SSI_CR0 jz_reg(SSI_CR0)
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#define JA_SSI_CR0 (0xb0043000 + 0x4)
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#define JT_SSI_CR0 JIO_32_RW
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#define JN_SSI_CR0 SSI_CR0
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#define JI_SSI_CR0
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#define BP_SSI_CR0_TENDIAN 18
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#define BM_SSI_CR0_TENDIAN 0xc0000
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#define BF_SSI_CR0_TENDIAN(v) (((v) & 0x3) << 18)
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#define BFM_SSI_CR0_TENDIAN(v) BM_SSI_CR0_TENDIAN
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#define BF_SSI_CR0_TENDIAN_V(e) BF_SSI_CR0_TENDIAN(BV_SSI_CR0_TENDIAN__##e)
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#define BFM_SSI_CR0_TENDIAN_V(v) BM_SSI_CR0_TENDIAN
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#define BP_SSI_CR0_RENDIAN 16
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#define BM_SSI_CR0_RENDIAN 0x30000
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#define BF_SSI_CR0_RENDIAN(v) (((v) & 0x3) << 16)
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#define BFM_SSI_CR0_RENDIAN(v) BM_SSI_CR0_RENDIAN
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#define BF_SSI_CR0_RENDIAN_V(e) BF_SSI_CR0_RENDIAN(BV_SSI_CR0_RENDIAN__##e)
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#define BFM_SSI_CR0_RENDIAN_V(v) BM_SSI_CR0_RENDIAN
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#define BP_SSI_CR0_SSIE 15
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#define BM_SSI_CR0_SSIE 0x8000
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#define BF_SSI_CR0_SSIE(v) (((v) & 0x1) << 15)
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#define BFM_SSI_CR0_SSIE(v) BM_SSI_CR0_SSIE
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#define BF_SSI_CR0_SSIE_V(e) BF_SSI_CR0_SSIE(BV_SSI_CR0_SSIE__##e)
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#define BFM_SSI_CR0_SSIE_V(v) BM_SSI_CR0_SSIE
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#define BP_SSI_CR0_TIE 14
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#define BM_SSI_CR0_TIE 0x4000
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#define BF_SSI_CR0_TIE(v) (((v) & 0x1) << 14)
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#define BFM_SSI_CR0_TIE(v) BM_SSI_CR0_TIE
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#define BF_SSI_CR0_TIE_V(e) BF_SSI_CR0_TIE(BV_SSI_CR0_TIE__##e)
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#define BFM_SSI_CR0_TIE_V(v) BM_SSI_CR0_TIE
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#define BP_SSI_CR0_RIE 13
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#define BM_SSI_CR0_RIE 0x2000
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#define BF_SSI_CR0_RIE(v) (((v) & 0x1) << 13)
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#define BFM_SSI_CR0_RIE(v) BM_SSI_CR0_RIE
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#define BF_SSI_CR0_RIE_V(e) BF_SSI_CR0_RIE(BV_SSI_CR0_RIE__##e)
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#define BFM_SSI_CR0_RIE_V(v) BM_SSI_CR0_RIE
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#define BP_SSI_CR0_TEIE 12
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#define BM_SSI_CR0_TEIE 0x1000
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#define BF_SSI_CR0_TEIE(v) (((v) & 0x1) << 12)
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#define BFM_SSI_CR0_TEIE(v) BM_SSI_CR0_TEIE
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#define BF_SSI_CR0_TEIE_V(e) BF_SSI_CR0_TEIE(BV_SSI_CR0_TEIE__##e)
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#define BFM_SSI_CR0_TEIE_V(v) BM_SSI_CR0_TEIE
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#define BP_SSI_CR0_REIE 11
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#define BM_SSI_CR0_REIE 0x800
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#define BF_SSI_CR0_REIE(v) (((v) & 0x1) << 11)
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#define BFM_SSI_CR0_REIE(v) BM_SSI_CR0_REIE
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#define BF_SSI_CR0_REIE_V(e) BF_SSI_CR0_REIE(BV_SSI_CR0_REIE__##e)
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#define BFM_SSI_CR0_REIE_V(v) BM_SSI_CR0_REIE
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#define BP_SSI_CR0_LOOP 10
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#define BM_SSI_CR0_LOOP 0x400
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#define BF_SSI_CR0_LOOP(v) (((v) & 0x1) << 10)
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#define BFM_SSI_CR0_LOOP(v) BM_SSI_CR0_LOOP
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#define BF_SSI_CR0_LOOP_V(e) BF_SSI_CR0_LOOP(BV_SSI_CR0_LOOP__##e)
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#define BFM_SSI_CR0_LOOP_V(v) BM_SSI_CR0_LOOP
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#define BP_SSI_CR0_RFINE 9
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#define BM_SSI_CR0_RFINE 0x200
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#define BF_SSI_CR0_RFINE(v) (((v) & 0x1) << 9)
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#define BFM_SSI_CR0_RFINE(v) BM_SSI_CR0_RFINE
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#define BF_SSI_CR0_RFINE_V(e) BF_SSI_CR0_RFINE(BV_SSI_CR0_RFINE__##e)
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#define BFM_SSI_CR0_RFINE_V(v) BM_SSI_CR0_RFINE
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#define BP_SSI_CR0_RFINC 8
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#define BM_SSI_CR0_RFINC 0x100
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#define BF_SSI_CR0_RFINC(v) (((v) & 0x1) << 8)
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#define BFM_SSI_CR0_RFINC(v) BM_SSI_CR0_RFINC
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#define BF_SSI_CR0_RFINC_V(e) BF_SSI_CR0_RFINC(BV_SSI_CR0_RFINC__##e)
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#define BFM_SSI_CR0_RFINC_V(v) BM_SSI_CR0_RFINC
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#define BP_SSI_CR0_EACLRUN 7
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#define BM_SSI_CR0_EACLRUN 0x80
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#define BF_SSI_CR0_EACLRUN(v) (((v) & 0x1) << 7)
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#define BFM_SSI_CR0_EACLRUN(v) BM_SSI_CR0_EACLRUN
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#define BF_SSI_CR0_EACLRUN_V(e) BF_SSI_CR0_EACLRUN(BV_SSI_CR0_EACLRUN__##e)
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#define BFM_SSI_CR0_EACLRUN_V(v) BM_SSI_CR0_EACLRUN
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#define BP_SSI_CR0_FSEL 6
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#define BM_SSI_CR0_FSEL 0x40
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#define BF_SSI_CR0_FSEL(v) (((v) & 0x1) << 6)
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#define BFM_SSI_CR0_FSEL(v) BM_SSI_CR0_FSEL
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#define BF_SSI_CR0_FSEL_V(e) BF_SSI_CR0_FSEL(BV_SSI_CR0_FSEL__##e)
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#define BFM_SSI_CR0_FSEL_V(v) BM_SSI_CR0_FSEL
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#define BP_SSI_CR0_VRCNT 4
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#define BM_SSI_CR0_VRCNT 0x10
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#define BF_SSI_CR0_VRCNT(v) (((v) & 0x1) << 4)
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#define BFM_SSI_CR0_VRCNT(v) BM_SSI_CR0_VRCNT
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#define BF_SSI_CR0_VRCNT_V(e) BF_SSI_CR0_VRCNT(BV_SSI_CR0_VRCNT__##e)
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#define BFM_SSI_CR0_VRCNT_V(v) BM_SSI_CR0_VRCNT
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#define BP_SSI_CR0_TFMODE 3
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#define BM_SSI_CR0_TFMODE 0x8
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#define BF_SSI_CR0_TFMODE(v) (((v) & 0x1) << 3)
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#define BFM_SSI_CR0_TFMODE(v) BM_SSI_CR0_TFMODE
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#define BF_SSI_CR0_TFMODE_V(e) BF_SSI_CR0_TFMODE(BV_SSI_CR0_TFMODE__##e)
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#define BFM_SSI_CR0_TFMODE_V(v) BM_SSI_CR0_TFMODE
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#define BP_SSI_CR0_TFLUSH 2
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#define BM_SSI_CR0_TFLUSH 0x4
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#define BF_SSI_CR0_TFLUSH(v) (((v) & 0x1) << 2)
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#define BFM_SSI_CR0_TFLUSH(v) BM_SSI_CR0_TFLUSH
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#define BF_SSI_CR0_TFLUSH_V(e) BF_SSI_CR0_TFLUSH(BV_SSI_CR0_TFLUSH__##e)
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#define BFM_SSI_CR0_TFLUSH_V(v) BM_SSI_CR0_TFLUSH
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#define BP_SSI_CR0_RFLUSH 1
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#define BM_SSI_CR0_RFLUSH 0x2
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#define BF_SSI_CR0_RFLUSH(v) (((v) & 0x1) << 1)
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#define BFM_SSI_CR0_RFLUSH(v) BM_SSI_CR0_RFLUSH
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#define BF_SSI_CR0_RFLUSH_V(e) BF_SSI_CR0_RFLUSH(BV_SSI_CR0_RFLUSH__##e)
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#define BFM_SSI_CR0_RFLUSH_V(v) BM_SSI_CR0_RFLUSH
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#define BP_SSI_CR0_DISREV 0
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#define BM_SSI_CR0_DISREV 0x1
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#define BF_SSI_CR0_DISREV(v) (((v) & 0x1) << 0)
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#define BFM_SSI_CR0_DISREV(v) BM_SSI_CR0_DISREV
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#define BF_SSI_CR0_DISREV_V(e) BF_SSI_CR0_DISREV(BV_SSI_CR0_DISREV__##e)
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#define BFM_SSI_CR0_DISREV_V(v) BM_SSI_CR0_DISREV
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#define REG_SSI_CR1 jz_reg(SSI_CR1)
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#define JA_SSI_CR1 (0xb0043000 + 0x8)
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#define JT_SSI_CR1 JIO_32_RW
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#define JN_SSI_CR1 SSI_CR1
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#define JI_SSI_CR1
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#define BP_SSI_CR1_FRMHL 30
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#define BM_SSI_CR1_FRMHL 0xc0000000
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#define BF_SSI_CR1_FRMHL(v) (((v) & 0x3) << 30)
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#define BFM_SSI_CR1_FRMHL(v) BM_SSI_CR1_FRMHL
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#define BF_SSI_CR1_FRMHL_V(e) BF_SSI_CR1_FRMHL(BV_SSI_CR1_FRMHL__##e)
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#define BFM_SSI_CR1_FRMHL_V(v) BM_SSI_CR1_FRMHL
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#define BP_SSI_CR1_TFVCK 28
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#define BM_SSI_CR1_TFVCK 0x30000000
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#define BF_SSI_CR1_TFVCK(v) (((v) & 0x3) << 28)
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#define BFM_SSI_CR1_TFVCK(v) BM_SSI_CR1_TFVCK
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#define BF_SSI_CR1_TFVCK_V(e) BF_SSI_CR1_TFVCK(BV_SSI_CR1_TFVCK__##e)
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#define BFM_SSI_CR1_TFVCK_V(v) BM_SSI_CR1_TFVCK
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#define BP_SSI_CR1_TCKFI 26
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#define BM_SSI_CR1_TCKFI 0xc000000
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#define BF_SSI_CR1_TCKFI(v) (((v) & 0x3) << 26)
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#define BFM_SSI_CR1_TCKFI(v) BM_SSI_CR1_TCKFI
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#define BF_SSI_CR1_TCKFI_V(e) BF_SSI_CR1_TCKFI(BV_SSI_CR1_TCKFI__##e)
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#define BFM_SSI_CR1_TCKFI_V(v) BM_SSI_CR1_TCKFI
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#define BP_SSI_CR1_FMAT 20
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#define BM_SSI_CR1_FMAT 0x300000
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#define BF_SSI_CR1_FMAT(v) (((v) & 0x3) << 20)
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#define BFM_SSI_CR1_FMAT(v) BM_SSI_CR1_FMAT
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#define BF_SSI_CR1_FMAT_V(e) BF_SSI_CR1_FMAT(BV_SSI_CR1_FMAT__##e)
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#define BFM_SSI_CR1_FMAT_V(v) BM_SSI_CR1_FMAT
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#define BP_SSI_CR1_TTRG 16
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#define BM_SSI_CR1_TTRG 0xf0000
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#define BF_SSI_CR1_TTRG(v) (((v) & 0xf) << 16)
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#define BFM_SSI_CR1_TTRG(v) BM_SSI_CR1_TTRG
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#define BF_SSI_CR1_TTRG_V(e) BF_SSI_CR1_TTRG(BV_SSI_CR1_TTRG__##e)
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#define BFM_SSI_CR1_TTRG_V(v) BM_SSI_CR1_TTRG
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#define BP_SSI_CR1_MCOM 12
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#define BM_SSI_CR1_MCOM 0xf000
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#define BF_SSI_CR1_MCOM(v) (((v) & 0xf) << 12)
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#define BFM_SSI_CR1_MCOM(v) BM_SSI_CR1_MCOM
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#define BF_SSI_CR1_MCOM_V(e) BF_SSI_CR1_MCOM(BV_SSI_CR1_MCOM__##e)
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#define BFM_SSI_CR1_MCOM_V(v) BM_SSI_CR1_MCOM
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#define BP_SSI_CR1_RTRG 8
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#define BM_SSI_CR1_RTRG 0xf00
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#define BF_SSI_CR1_RTRG(v) (((v) & 0xf) << 8)
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#define BFM_SSI_CR1_RTRG(v) BM_SSI_CR1_RTRG
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#define BF_SSI_CR1_RTRG_V(e) BF_SSI_CR1_RTRG(BV_SSI_CR1_RTRG__##e)
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#define BFM_SSI_CR1_RTRG_V(v) BM_SSI_CR1_RTRG
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#define BP_SSI_CR1_FLEN 3
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#define BM_SSI_CR1_FLEN 0xf8
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#define BF_SSI_CR1_FLEN(v) (((v) & 0x1f) << 3)
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#define BFM_SSI_CR1_FLEN(v) BM_SSI_CR1_FLEN
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#define BF_SSI_CR1_FLEN_V(e) BF_SSI_CR1_FLEN(BV_SSI_CR1_FLEN__##e)
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#define BFM_SSI_CR1_FLEN_V(v) BM_SSI_CR1_FLEN
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#define BP_SSI_CR1_ITFRM 24
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#define BM_SSI_CR1_ITFRM 0x1000000
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#define BF_SSI_CR1_ITFRM(v) (((v) & 0x1) << 24)
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#define BFM_SSI_CR1_ITFRM(v) BM_SSI_CR1_ITFRM
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#define BF_SSI_CR1_ITFRM_V(e) BF_SSI_CR1_ITFRM(BV_SSI_CR1_ITFRM__##e)
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#define BFM_SSI_CR1_ITFRM_V(v) BM_SSI_CR1_ITFRM
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#define BP_SSI_CR1_UNFIN 23
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#define BM_SSI_CR1_UNFIN 0x800000
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#define BF_SSI_CR1_UNFIN(v) (((v) & 0x1) << 23)
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#define BFM_SSI_CR1_UNFIN(v) BM_SSI_CR1_UNFIN
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#define BF_SSI_CR1_UNFIN_V(e) BF_SSI_CR1_UNFIN(BV_SSI_CR1_UNFIN__##e)
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#define BFM_SSI_CR1_UNFIN_V(v) BM_SSI_CR1_UNFIN
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#define BP_SSI_CR1_PHA 1
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#define BM_SSI_CR1_PHA 0x2
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#define BF_SSI_CR1_PHA(v) (((v) & 0x1) << 1)
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#define BFM_SSI_CR1_PHA(v) BM_SSI_CR1_PHA
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#define BF_SSI_CR1_PHA_V(e) BF_SSI_CR1_PHA(BV_SSI_CR1_PHA__##e)
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#define BFM_SSI_CR1_PHA_V(v) BM_SSI_CR1_PHA
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#define BP_SSI_CR1_POL 0
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#define BM_SSI_CR1_POL 0x1
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#define BF_SSI_CR1_POL(v) (((v) & 0x1) << 0)
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#define BFM_SSI_CR1_POL(v) BM_SSI_CR1_POL
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#define BF_SSI_CR1_POL_V(e) BF_SSI_CR1_POL(BV_SSI_CR1_POL__##e)
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#define BFM_SSI_CR1_POL_V(v) BM_SSI_CR1_POL
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#define REG_SSI_SR jz_reg(SSI_SR)
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#define JA_SSI_SR (0xb0043000 + 0xc)
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#define JT_SSI_SR JIO_32_RW
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#define JN_SSI_SR SSI_SR
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#define JI_SSI_SR
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#define BP_SSI_SR_TFIFO_NUM 16
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#define BM_SSI_SR_TFIFO_NUM 0x1ff0000
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#define BF_SSI_SR_TFIFO_NUM(v) (((v) & 0x1ff) << 16)
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#define BFM_SSI_SR_TFIFO_NUM(v) BM_SSI_SR_TFIFO_NUM
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#define BF_SSI_SR_TFIFO_NUM_V(e) BF_SSI_SR_TFIFO_NUM(BV_SSI_SR_TFIFO_NUM__##e)
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#define BFM_SSI_SR_TFIFO_NUM_V(v) BM_SSI_SR_TFIFO_NUM
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#define BP_SSI_SR_RFIFO_NUM 8
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#define BM_SSI_SR_RFIFO_NUM 0xff00
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#define BF_SSI_SR_RFIFO_NUM(v) (((v) & 0xff) << 8)
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#define BFM_SSI_SR_RFIFO_NUM(v) BM_SSI_SR_RFIFO_NUM
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#define BF_SSI_SR_RFIFO_NUM_V(e) BF_SSI_SR_RFIFO_NUM(BV_SSI_SR_RFIFO_NUM__##e)
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#define BFM_SSI_SR_RFIFO_NUM_V(v) BM_SSI_SR_RFIFO_NUM
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#define BP_SSI_SR_END 7
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#define BM_SSI_SR_END 0x80
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#define BF_SSI_SR_END(v) (((v) & 0x1) << 7)
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#define BFM_SSI_SR_END(v) BM_SSI_SR_END
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#define BF_SSI_SR_END_V(e) BF_SSI_SR_END(BV_SSI_SR_END__##e)
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#define BFM_SSI_SR_END_V(v) BM_SSI_SR_END
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#define BP_SSI_SR_BUSY 6
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#define BM_SSI_SR_BUSY 0x40
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#define BF_SSI_SR_BUSY(v) (((v) & 0x1) << 6)
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#define BFM_SSI_SR_BUSY(v) BM_SSI_SR_BUSY
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#define BF_SSI_SR_BUSY_V(e) BF_SSI_SR_BUSY(BV_SSI_SR_BUSY__##e)
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#define BFM_SSI_SR_BUSY_V(v) BM_SSI_SR_BUSY
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#define BP_SSI_SR_TFF 5
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#define BM_SSI_SR_TFF 0x20
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#define BF_SSI_SR_TFF(v) (((v) & 0x1) << 5)
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#define BFM_SSI_SR_TFF(v) BM_SSI_SR_TFF
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#define BF_SSI_SR_TFF_V(e) BF_SSI_SR_TFF(BV_SSI_SR_TFF__##e)
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#define BFM_SSI_SR_TFF_V(v) BM_SSI_SR_TFF
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#define BP_SSI_SR_RFE 4
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#define BM_SSI_SR_RFE 0x10
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#define BF_SSI_SR_RFE(v) (((v) & 0x1) << 4)
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#define BFM_SSI_SR_RFE(v) BM_SSI_SR_RFE
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#define BF_SSI_SR_RFE_V(e) BF_SSI_SR_RFE(BV_SSI_SR_RFE__##e)
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#define BFM_SSI_SR_RFE_V(v) BM_SSI_SR_RFE
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#define BP_SSI_SR_TFHE 3
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#define BM_SSI_SR_TFHE 0x8
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#define BF_SSI_SR_TFHE(v) (((v) & 0x1) << 3)
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#define BFM_SSI_SR_TFHE(v) BM_SSI_SR_TFHE
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#define BF_SSI_SR_TFHE_V(e) BF_SSI_SR_TFHE(BV_SSI_SR_TFHE__##e)
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#define BFM_SSI_SR_TFHE_V(v) BM_SSI_SR_TFHE
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#define BP_SSI_SR_RFHF 2
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#define BM_SSI_SR_RFHF 0x4
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#define BF_SSI_SR_RFHF(v) (((v) & 0x1) << 2)
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#define BFM_SSI_SR_RFHF(v) BM_SSI_SR_RFHF
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#define BF_SSI_SR_RFHF_V(e) BF_SSI_SR_RFHF(BV_SSI_SR_RFHF__##e)
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#define BFM_SSI_SR_RFHF_V(v) BM_SSI_SR_RFHF
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#define BP_SSI_SR_UNDR 1
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#define BM_SSI_SR_UNDR 0x2
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#define BF_SSI_SR_UNDR(v) (((v) & 0x1) << 1)
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#define BFM_SSI_SR_UNDR(v) BM_SSI_SR_UNDR
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#define BF_SSI_SR_UNDR_V(e) BF_SSI_SR_UNDR(BV_SSI_SR_UNDR__##e)
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#define BFM_SSI_SR_UNDR_V(v) BM_SSI_SR_UNDR
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#define BP_SSI_SR_OVER 0
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#define BM_SSI_SR_OVER 0x1
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#define BF_SSI_SR_OVER(v) (((v) & 0x1) << 0)
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#define BFM_SSI_SR_OVER(v) BM_SSI_SR_OVER
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#define BF_SSI_SR_OVER_V(e) BF_SSI_SR_OVER(BV_SSI_SR_OVER__##e)
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#define BFM_SSI_SR_OVER_V(v) BM_SSI_SR_OVER
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#define REG_SSI_ITR jz_reg(SSI_ITR)
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#define JA_SSI_ITR (0xb0043000 + 0x10)
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#define JT_SSI_ITR JIO_32_RW
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#define JN_SSI_ITR SSI_ITR
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#define JI_SSI_ITR
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#define BP_SSI_ITR_IVLTM 0
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#define BM_SSI_ITR_IVLTM 0x7fff
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#define BF_SSI_ITR_IVLTM(v) (((v) & 0x7fff) << 0)
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#define BFM_SSI_ITR_IVLTM(v) BM_SSI_ITR_IVLTM
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#define BF_SSI_ITR_IVLTM_V(e) BF_SSI_ITR_IVLTM(BV_SSI_ITR_IVLTM__##e)
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#define BFM_SSI_ITR_IVLTM_V(v) BM_SSI_ITR_IVLTM
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#define BP_SSI_ITR_CNTCLK 15
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#define BM_SSI_ITR_CNTCLK 0x8000
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#define BF_SSI_ITR_CNTCLK(v) (((v) & 0x1) << 15)
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#define BFM_SSI_ITR_CNTCLK(v) BM_SSI_ITR_CNTCLK
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#define BF_SSI_ITR_CNTCLK_V(e) BF_SSI_ITR_CNTCLK(BV_SSI_ITR_CNTCLK__##e)
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#define BFM_SSI_ITR_CNTCLK_V(v) BM_SSI_ITR_CNTCLK
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#define REG_SSI_ICR jz_reg(SSI_ICR)
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#define JA_SSI_ICR (0xb0043000 + 0x14)
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#define JT_SSI_ICR JIO_32_RW
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#define JN_SSI_ICR SSI_ICR
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#define JI_SSI_ICR
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#define REG_SSI_GR jz_reg(SSI_GR)
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#define JA_SSI_GR (0xb0043000 + 0x18)
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#define JT_SSI_GR JIO_32_RW
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#define JN_SSI_GR SSI_GR
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#define JI_SSI_GR
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#define REG_SSI_RCNT jz_reg(SSI_RCNT)
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#define JA_SSI_RCNT (0xb0043000 + 0x1c)
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#define JT_SSI_RCNT JIO_32_RW
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#define JN_SSI_RCNT SSI_RCNT
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#define JI_SSI_RCNT
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#endif /* __HEADERGEN_SSI_H__*/
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