46a608bf07
ROM. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11669 a1c6a512-1295-4272-9138-f99709370657
156 lines
6.3 KiB
C
156 lines
6.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#include "kernel.h"
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#include "system.h"
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#include "power.h"
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#include "timer.h"
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#include "pcf50606.h"
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/* Settings for all possible clock frequencies (with properly working timers)
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*
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* xxx_REFRESH_TIMER below
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* system.h, CPUFREQ_xxx_MULT |
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* | |
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* V V
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* Refreshtim. IDECONFIG1/IDECONFIG2
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* CPUCLK/Hz MULT PLLCR 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait
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* ---------------------------------------------------------------------------------------
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* 11289600 1 0x10c00200 4 1 0x0180 0x0180 0x0180 1 0 0
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* 22579200 2 0x15c4e005 10 4 0x0180 0x0180 0x0180 1 0 0
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* 33868800 3 0x13c46005 15 7 0x0180 0x0180 0x0180 1 0 0
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* 45158400 4 0x15c4e001 21 10 0x0580 0x0180 0x0580 1 0 0
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* 56448000 5 0x12c4e005 26 12 0x0580 0x0980
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* 67737600 6 0x13c46001 32 15 0x0980 0x0d80
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* 79027200 7 0x13c52001 37 18 0x0980 0x1180
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* 90316800 8 0x13c5e001 43 21 0x0d80 0x1580
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* 101606400 9 0x11c48005 48 23 0x0d80 0x1980
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* 112896000 10 0x11c4e005 54 26 0x1180 0x1d80
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* 124185600 11 0x11c56005 59 29 0x1180 0x1180 0x2180 2 1 2
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*/
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#if MEM < 32
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#define MAX_REFRESH_TIMER 59
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#define NORMAL_REFRESH_TIMER 21
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#define DEFAULT_REFRESH_TIMER 4
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#else
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#define MAX_REFRESH_TIMER 29
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#define NORMAL_REFRESH_TIMER 10
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#define DEFAULT_REFRESH_TIMER 1
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#endif
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#ifdef IRIVER_H300_SERIES
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#define RECALC_DELAYS(f) \
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pcf50606_i2c_recalc_delay(f)
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#else
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#define RECALC_DELAYS(f)
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#endif
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#ifdef HAVE_SERIAL
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#define BAUD_RATE 57600
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#define BAUDRATE_DIV_DEFAULT (CPUFREQ_DEFAULT/(BAUD_RATE*32*2))
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#define BAUDRATE_DIV_NORMAL (CPUFREQ_NORMAL/(BAUD_RATE*32*2))
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#define BAUDRATE_DIV_MAX (CPUFREQ_MAX/(BAUD_RATE*32*2))
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#endif
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void set_cpu_frequency (long) __attribute__ ((section (".icode")));
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void set_cpu_frequency(long frequency)
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{
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switch(frequency)
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{
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case CPUFREQ_MAX:
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DCR = (0x8200 | DEFAULT_REFRESH_TIMER);
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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RECALC_DELAYS(CPUFREQ_MAX);
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PLLCR = 0x01856005 | (PLLCR & 0x70400000);
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CSCR0 = 0x00001180; /* Flash: 4 wait states */
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CSCR1 = 0x00001580; /* LCD: 5 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
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#endif
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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This may take up to 10ms! */
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timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
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DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_MAX;
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IDECONFIG1 = 0x10100000 | (1 << 13) | (2 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (2 << 8); /* TA enable + CS2wait */
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#ifdef HAVE_SERIAL
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UBG10 = BAUDRATE_DIV_MAX >> 8;
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UBG20 = BAUDRATE_DIV_MAX & 0xff;
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#endif
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break;
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case CPUFREQ_NORMAL:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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RECALC_DELAYS(CPUFREQ_NORMAL);
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PLLCR = 0x0385e005 | (PLLCR & 0x70400000);
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CSCR0 = 0x00000580; /* Flash: 1 wait state */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
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#endif
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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This may take up to 10ms! */
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timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
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DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_NORMAL;
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IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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#ifdef HAVE_SERIAL
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UBG10 = BAUDRATE_DIV_NORMAL >> 8;
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UBG20 = BAUDRATE_DIV_NORMAL & 0xff;
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#endif
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break;
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default:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
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RECALC_DELAYS(CPUFREQ_DEFAULT);
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/* Power down PLL, but keep CLSEL */
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PLLCR = 0x00000200 | (PLLCR & 0x70400000);
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CSCR0 = 0x00000180; /* Flash: 0 wait states */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
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#endif
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DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_DEFAULT;
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IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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#ifdef HAVE_SERIAL
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UBG10 = BAUDRATE_DIV_DEFAULT >> 8;
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UBG20 = BAUDRATE_DIV_DEFAULT & 0xff;
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#endif
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break;
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}
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}
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