179 lines
7.7 KiB
C
179 lines
7.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _UDA1380_H
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#define _UDA1380_H
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#define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | PRESCALER_CAP | \
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LIN_GAIN_CAP | MIC_GAIN_CAP)
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AUDIOHW_SETTING(VOLUME, "dB", 0, 1, -84, 0, -25)
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AUDIOHW_SETTING(BASS, "dB", 0, 2, 0, 24, 0)
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AUDIOHW_SETTING(TREBLE, "dB", 0, 2, 0, 6, 0)
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#ifdef HAVE_RECORDING
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/* microphone: -128 .. 108 -> -64 .. 54 dB gain
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* line-in: -128 .. 96 -> -64 .. 48 dB gain */
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AUDIOHW_SETTING(LEFT_GAIN, "dB", 1, 1,-128, 96, 0, val * 5)
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AUDIOHW_SETTING(RIGHT_GAIN, "dB", 1, 1,-128, 96, 0, val * 5)
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AUDIOHW_SETTING(MIC_GAIN, "dB", 1, 1,-128, 108, 16, val * 5)
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#endif /* HAVE_RECORDING */
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#define UDA1380_ADDR 0x30
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/* REG_0: Misc settings */
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#define REG_0 0x00
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#define EN_ADC (1 << 11) /* Enable ADC */
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#define EN_DEC (1 << 10) /* Enable Decimator */
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#define EN_DAC (1 << 9) /* Enable DAC */
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#define EN_INT (1 << 8) /* Enable Interpolator */
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#define ADC_CLK (1 << 5) /* ADC_CLK: WSPLL (1) SYSCLK (0) */
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#define DAC_CLK (1 << 4) /* DAC_CLK: WSPLL (1) SYSCLK (0) */
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/* SYSCLK freqency select */
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#define SYSCLK_256FS (0 << 2)
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#define SYSCLK_384FS (1 << 2)
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#define SYSCLK_512FS (2 << 2)
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#define SYSCLK_768FS (3 << 2)
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/* WSPLL Input frequency range (kHz) */
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#define WSPLL_625_125 (0 << 0) /* 6.25 - 12.5 */
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#define WSPLL_125_25 (1 << 0) /* 12.5 - 25 */
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#define WSPLL_25_50 (2 << 0) /* 25 - 50 */
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#define WSPLL_50_100 (3 << 0) /* 50 - 100 */
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/* REG_I2S: I2S settings */
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#define REG_I2S 0x01
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#define I2S_IFMT_IIS (0 << 8)
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#define I2S_IFMT_LSB16 (1 << 8)
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#define I2S_IFMT_LSB18 (2 << 8)
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#define I2S_IFMT_LSB20 (3 << 8)
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#define I2S_IFMT_MSB (5 << 8)
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#define I2S_OFMT_IIS (0 << 0)
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#define I2S_OFMT_LSB16 (1 << 0)
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#define I2S_OFMT_LSB18 (2 << 0)
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#define I2S_OFMT_LSB20 (3 << 0)
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#define I2S_OFMT_LSB24 (4 << 0)
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#define I2S_OFMT_MSB (5 << 0)
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#define I2S_MODE_MASTER (1 << 4)
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/* REG_PWR: Power control */
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#define REG_PWR 0x02
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#define PON_PLL (1 << 15) /* Power-on WSPLL */
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#define PON_HP (1 << 13) /* Power-on Headphone driver */
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#define PON_DAC (1 << 10) /* Power-on DAC */
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#define PON_BIAS (1 << 8) /* Power-on BIAS for ADC, AVC, FSDAC */
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#define EN_AVC (1 << 7) /* Enable analog mixer */
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#define PON_AVC (1 << 6) /* Power-on analog mixer */
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#define PON_LNA (1 << 4) /* Power-on LNA & SDC */
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#define PON_PGAL (1 << 3) /* Power-on PGA left */
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#define PON_ADCL (1 << 2) /* Power-on ADC left */
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#define PON_PGAR (1 << 1) /* Power-on PGA right */
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#define PON_ADCR (1 << 0) /* Power-on ADC right */
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/* REG_AMIX: Analog mixer */
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#define REG_AMIX 0x03
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#define AMIX_LEFT(x) (((x) & 0x3f) << 8)
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#define AMIX_RIGHT(x) (((x) & 0x3f) << 0)
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/* REG_HP: Headphone amp */
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#define REG_HP 0x04
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/* REG_MV: Master Volume control */
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#define REG_MASTER_VOL 0x10
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#define MASTER_VOL_RIGHT(x) (((x) & 0xff) << 8)
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#define MASTER_VOL_LEFT(x) (((x) & 0xff) << 0)
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/* REG_MIX: Mixer volume control */
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/* Channel 1 is from digital data from I2S */
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/* Channel 2 is from decimation filter */
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#define REG_MIX_VOL 0x11
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#define MIX_VOL_CH_1(x) (((x) & 0xff) << 0)
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#define MIX_VOL_CH_2(x) (((x) & 0xff) << 8)
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/* REG_EQ: Bass boost and tremble */
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#define REG_EQ 0x12
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#define EQ_MODE_FLAT (0 << 14)
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#define EQ_MODE_MIN (1 << 14)
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#define EQ_MODE_MAX (3 << 14)
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#define BASSL(x) (((x) & 0x1E) << 7)
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#define BASSR(x) (((x) & 0x1E) >> 1)
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#define TREBLEL(x) (((x) & 0x6) << 11)
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#define TREBLER(x) (((x) & 0x6) << 3)
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#define BASS_MASK 0x0F0F
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#define TREBLE_MASK 0x3030
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/* REG_MUTE: Master Mute, silence detector and oversampling */
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#define REG_MUTE 0x13
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#define MUTE_MASTER (1 << 14) /* Master Mute (soft) */
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#define MUTE_CH2 (1 << 11) /* Channel 2 mute */
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#define MUTE_CH1 (1 << 3) /* Channel 1 mute */
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#define DE_EMPHASIS_NONE (0 << 8) /* no de-emphasis */
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#define DE_EMPHASIS_32kHz (1 << 8) /* 32 kHz */
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#define DE_EMPHASIS_44kHz (2 << 8) /* 44.1 kHz */
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#define DE_EMPHASIS_48kHz (3 << 8) /* 48 kHz */
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#define DE_EMPHASIS_96kHz (4 << 8) /* 96 kHz */
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/* REG_MIX_CTL: Mixer, silence detector and oversampling settings */
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#define REG_MIX_CTL 0x14
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#define DAC_INVERT (1 << 15) /* invert DAC polarity */
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#define MIX_CTL_SEL_NS (1 << 14) /* 0 = 3rd, 1 = 5th order */
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#define MIX_CTL_MIX_POS (1 << 13) /* MIX MODE bit MIX POS */
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#define MIX_CTL_MIX (1 << 12) /* MIX MODE bit MIX */
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#define MIX_MODE(x) (((x) & 0x3) << 12) /* Mixer mode: See table 48 */
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#define SILENCE_MODE (1 << 7) /* force silence output */
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#define SILENCE_DET_ON (1 << 6) /* enable silence detection */
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#define SILENCE_DET(x) (((x) & 0x3) << 4) /* silence detection value */
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#define SILENCE_DET_3200 (0 << 4) /* 3200 samples */
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#define SILENCE_DET_4800 (1 << 4) /* 4800 samples */
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#define SILENCE_DET_9600 (2 << 4) /* 9600 samples */
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#define SILENCE_DET_19200 (3 << 4) /* 19200 samples */
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#define OVERSAMPLE_MODE(x) (((x) & 0x3) << 0) /* oversampling mode */
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/* REG_DEC_VOL: Decimator (ADC) volume control */
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#define REG_DEC_VOL 0x20
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#define DEC_VOLL(x) (((x) & 0xff) << 8)
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#define DEC_VOLR(x) (((x) & 0xff) << 0)
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/* REG_PGA: PGA settings and mute */
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#define REG_PGA 0x21
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#define MUTE_ADC (1 << 15) /* Mute ADC */
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#define PGA_GAINR(x) (((x) & 0xF) << 8)
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#define PGA_GAINL(x) (((x) & 0xF) << 0)
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#define PGA_GAIN_MASK 0x0F0F
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/* REG_ADC: */
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#define REG_ADC 0x22
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#define ADC_INVERT (1 << 12) /* invert ADC polarity */
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#define VGA_GAIN(x) (((x) & 0xF) << 8)
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#define VGA_GAIN_MASK 0x0F00
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#define SEL_LNA (1 << 3)
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#define SEL_MIC (1 << 2)
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#define SKIP_DCFIL (1 << 1)
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#define EN_DCFIL (1 << 0)
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/* REG_AGC: Attack / Gain */
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#define REG_AGC 0x23
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#endif /* _UDA_1380_H */
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