0a7d941fb9
Split the ISR into two parts and alllow quick return from first half. Introduces a uevent() API to have a callback happen in a specified number of microseconds. Right now only one event is supported. Change-Id: Ib1666165be2f6082e5275d64961f083cab104f9f
100 lines
4.5 KiB
C
100 lines
4.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by James Espinoza
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef AVIC_IMX31_H
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#define AVIC_IMX31_H
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/* #define IRQ priorities for different modules (0-15) */
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#define INT_PRIO_DEFAULT 7
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#define INT_PRIO_DVFS (INT_PRIO_DEFAULT+1)
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#define INT_PRIO_DPTC (INT_PRIO_DEFAULT+1)
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#define INT_PRIO_GPT (INT_PRIO_DEFAULT+1)
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#define INT_PRIO_SDMA (INT_PRIO_DEFAULT+2)
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enum INT_TYPE
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{
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INT_TYPE_IRQ = 0,
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INT_TYPE_FIQ
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};
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enum IMX31_INT_LIST
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{
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__IMX31_INT_FIRST = -1,
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INT_RESERVED0, INT_RESERVED1, INT_RESERVED2, INT_I2C3,
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INT_I2C2, INT_MPEG4_ENCODER, INT_RTIC, INT_FIR,
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INT_MMC_SDHC2, INT_MMC_SDHC1, INT_I2C1, INT_SSI2,
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INT_SSI1, INT_CSPI2, INT_CSPI1, INT_ATA,
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INT_MBX, INT_CSPI3, INT_UART3, INT_IIM,
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INT_SIM1, INT_SIM2, INT_RNGA, INT_EVTMON,
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INT_KPP, INT_RTC, INT_PWN, INT_EPIT2,
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INT_EPIT1, INT_GPT, INT_PWR_FAIL, INT_CCM_DVFS,
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INT_UART2, INT_NANDFC, INT_SDMA, INT_USB_HOST1,
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INT_USB_HOST2, INT_USB_OTG, INT_RESERVED3, INT_MSHC1,
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INT_MSHC2, INT_IPU_ERR, INT_IPU, INT_RESERVED4,
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INT_RESERVED5, INT_UART1, INT_UART4, INT_UART5,
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INT_ETC_IRQ, INT_SCC_SCM, INT_SCC_SMN, INT_GPIO2,
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INT_GPIO1, INT_CCM_CLK, INT_PCMCIA, INT_WDOG,
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INT_GPIO3, INT_RESERVED6, INT_EXT_PWMG, INT_EXT_TEMP,
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INT_EXT_SENS1, INT_EXT_SENS2, INT_EXT_WDOG, INT_EXT_TV,
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INT_ALL
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};
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void avic_init(void);
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void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
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unsigned long ni_priority, void (*handler)(void));
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void avic_set_int_priority(enum IMX31_INT_LIST ints,
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unsigned long ni_priority);
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void avic_disable_int(enum IMX31_INT_LIST ints);
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void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype);
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#define AVIC_NIL_DISABLE 15
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#define AVIC_NIL_ENABLE (-1)
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void avic_set_ni_level(int level);
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static inline void avic_mask_int(enum IMX31_INT_LIST ints)
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{ AVIC_INTDISNUM = ints; }
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static inline void avic_unmask_int(enum IMX31_INT_LIST ints)
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{ AVIC_INTENNUM = ints; }
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/* Call a service routine while allowing preemption by interrupts of higher
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* priority. Avoid actually enabling IRQ until the routine decides to do so;
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* epilogue code will always disable them again. */
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#define AVIC_NESTED_NI_CALL(fn, prio) \
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({ asm volatile ( \
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"sub lr, lr, #4 \n" /* prepare return address */ \
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"srsdb #0x12! \n" /* save LR_irq and SPSR_irq */ \
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"stmfd sp!, { r0-r3, r12 } \n" /* preserve context */ \
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"mov r0, #0x68000000 \n" /* AVIC_BASE_ADDR */ \
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"mov r1, %0 \n" /* load interrupt level */ \
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"ldr r2, [r0, #0x04] \n" /* save NIMASK */ \
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"str r1, [r0, #0x04] \n" /* set interrupt level */ \
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"cps #0x13 \n" /* change to SVC mode */ \
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"stmfd sp!, { r2, lr } \n" /* push NIMASK and LR_svc */ \
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"bl " #fn " \n" /* Call SVC routine */ \
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"cpsid i \n" /* disable IRQ */ \
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"ldmfd sp!, { r1, lr } \n" /* pop NIMASK and LR_svc */ \
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"cps #0x12 \n" /* return to IRQ mode */ \
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"mov r0, #0x68000000 \n" /* AVIC BASE ADDR */ \
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"str r1, [r0, #0x04] \n" /* restore NIMASK */ \
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"ldmfd sp!, { r0-r3, r12 } \n" /* reload context */ \
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"rfefd sp! \n" /* move stacked SPSR to CPSR, return */ \
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: : "i"(prio)); })
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#endif /* AVIC_IMX31_H */
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