350 lines
9.2 KiB
C
350 lines
9.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (c) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <sys/types.h> /* off_t */
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#include <string.h>
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#include "cpu.h"
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#include "system.h"
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#include "kernel.h"
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#include "backlight-target.h"
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#include "lcd.h"
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#include "lcdif-imx233.h"
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#include "clkctrl-imx233.h"
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#include "pinctrl-imx233.h"
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#include "dma-imx233.h"
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#include "regs/regs-uartdbg.h"
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#include "logf.h"
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#ifndef BOOTLOADER
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#include "button.h"
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#include "font.h"
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#include "action.h"
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#endif
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static bool lcd_on;
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/**
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* DMA
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*/
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/* Used for DMA */
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struct lcdif_dma_command_t
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{
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struct apb_dma_command_t dma;
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uint32_t pad;
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} __attribute__((packed)) CACHEALIGN_ATTR;
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__ENSURE_STRUCT_CACHE_FRIENDLY(struct lcdif_dma_command_t)
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#define NR_CMDS ((IMX233_FRAMEBUFFER_SIZE + IMX233_MAX_SINGLE_DMA_XFER_SIZE - 1) / IMX233_MAX_SINGLE_DMA_XFER_SIZE)
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struct lcdif_dma_command_t lcdif_dma[NR_CMDS];
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/**
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* Utils
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*/
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static int g_wait_nr_frame = 0;
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static struct semaphore g_wait_sema;
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static void wait_frames_cb(void)
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{
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if(--g_wait_nr_frame == 0)
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semaphore_release(&g_wait_sema);
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}
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static void wait_nr_frames(int nr)
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{
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g_wait_nr_frame = 2 + nr; // +1 because we want entire frames, +1 to be safe
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imx233_lcdif_set_vsync_edge_cb(wait_frames_cb);
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imx233_lcdif_enable_vsync_edge_irq(true);
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semaphore_wait(&g_wait_sema, TIMEOUT_BLOCK);
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imx233_lcdif_enable_vsync_edge_irq(false);
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}
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/**
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* SPI
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*/
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#define SPI_CS(v) imx233_pinctrl_set_gpio(1, 11, v)
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#define SPI_SCL(v) imx233_pinctrl_set_gpio(1, 10, v)
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#define SPI_SDO(v) imx233_pinctrl_set_gpio(1, 9, v)
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#define DEV_ID 0x74
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#define RS 0x2
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#define RW 0x1
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static void spi_enable(bool en)
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{
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imx233_pinctrl_set_gpio(1, 9, en);
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imx233_pinctrl_set_gpio(1, 10, en);
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imx233_pinctrl_set_gpio(1, 11, en);
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imx233_pinctrl_enable_gpio(1, 9, en);
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imx233_pinctrl_enable_gpio(1, 10, en);
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imx233_pinctrl_enable_gpio(1, 11, en);
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mdelay(1);
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}
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static void spi_delay(void)
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{
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udelay(1);
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}
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static void spi_begin(void)
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{
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SPI_CS(false);
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spi_delay();
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}
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static void spi_write(unsigned char b)
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{
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for(int i = 7; i >= 0; i--)
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{
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SPI_SCL(false);
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spi_delay();
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SPI_SDO((b >> i) & 1);
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spi_delay();
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SPI_SCL(true);
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spi_delay();
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}
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}
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static void spi_end(void)
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{
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SPI_CS(true);
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spi_delay();
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}
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static void spi_write_reg(uint8_t reg, uint16_t value)
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{
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spi_begin();
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spi_write(DEV_ID);
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spi_write(0);
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spi_write(reg);
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spi_end();
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spi_begin();
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spi_write(DEV_ID | RS);
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spi_write(value >> 8);
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spi_write(value & 0xff);
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spi_end();
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}
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/**
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* LCD control
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*/
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static void lcd_power(bool en)
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{
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imx233_pinctrl_set_gpio(1, 8, en);
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mdelay(10);
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}
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static void lcd_power_seq(void)
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{
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spi_write_reg(0x7, 0);
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mdelay(10);
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spi_write_reg(0x12, 0x1618);
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spi_write_reg(0x11, 0x2227);
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spi_write_reg(0x13, 0x61d1);
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spi_write_reg(0x10, 0x550c);
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wait_nr_frames(5);
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spi_write_reg(0x12, 0x0c58);
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}
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static void lcd_init_seq(void)
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{
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/* NOTE I don't understand why I have to use BGR, logic would say I should not */
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spi_write_reg(0x1, 0x2b1d);// inversion
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spi_write_reg(0x2, 0x300);
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/* NOTE by default stmp3700 has vsync/hsync active low and data launch
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* at negative edge of dotclk, reflect this in the polarity settings */
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spi_write_reg(0x3, 0xd040);// polarity (OF uses 0xc040, seems incorrect)
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spi_write_reg(0x8, 0); // vsync back porch (0=3H)
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spi_write_reg(0x9, 0); // hsync back porch (0=24clk)
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spi_write_reg(0x76, 0x2213);
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spi_write_reg(0xb, 0x33e1);
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spi_write_reg(0xc, 0x23);
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spi_write_reg(0x76, 0);
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spi_write_reg(0xd, 7);
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spi_write_reg(0xe, 0);
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spi_write_reg(0x15, 0x803);
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spi_write_reg(0x14, 0);
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spi_write_reg(0x16, 0);
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spi_write_reg(0x30, 0x706);
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spi_write_reg(0x31, 0x406);
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spi_write_reg(0x32, 0xc09);
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spi_write_reg(0x33, 0x606);
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spi_write_reg(0x34, 0x706);
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spi_write_reg(0x35, 0x406);
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spi_write_reg(0x36, 0xc06);
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spi_write_reg(0x37, 0x601);
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spi_write_reg(0x38, 0x504);
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spi_write_reg(0x39, 0x504);
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}
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static void lcd_display_on_seq(void)
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{
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spi_write_reg(0x7, 1);
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wait_nr_frames(1);
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spi_write_reg(0x7, 0x101);
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wait_nr_frames(2);
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spi_write_reg(0x76, 0x2213);
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spi_write_reg(0x1c, 0x6650);
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spi_write_reg(0xb, 0x33e1);
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spi_write_reg(0x76, 0);
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spi_write_reg(0x7, 0x103);
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}
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static void lcd_display_off_seq(void)
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{
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spi_write_reg(0xb, 0x30e1);
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spi_write_reg(0x7, 0x102);
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wait_nr_frames(2);
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spi_write_reg(0x7, 0);
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spi_write_reg(0x12, 0);
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spi_write_reg(0x10, 0x100);
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}
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/**
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* Rockbox
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*/
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bool lcd_active(void)
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{
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return lcd_on;
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}
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void lcd_enable(bool enable)
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{
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if(lcd_on == enable)
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return;
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lcd_on = enable;
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if(lcd_on)
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{
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// enable spi
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spi_enable(true);
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// reset
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imx233_lcdif_reset_lcd(true);
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imx233_lcdif_reset_lcd(false);
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mdelay(1);
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imx233_lcdif_reset_lcd(true);
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mdelay(1);
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// "power" on
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lcd_power(true);
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// setup registers
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imx233_lcdif_enable_sync_signals(true); // we need frame signals during init
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lcd_power_seq();
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lcd_init_seq();
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lcd_display_on_seq();
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imx233_dma_reset_channel(APB_LCDIF);
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imx233_dma_start_command(APB_LCDIF, &lcdif_dma[0].dma);
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BF_SET(LCDIF_CTRL, DOTCLK_MODE);
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BF_SET(LCDIF_CTRL, RUN);
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}
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else
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{
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// power down
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lcd_display_off_seq();
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lcd_power(false);
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// stop lcdif
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BF_CLR(LCDIF_CTRL, DOTCLK_MODE);
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// disable spi
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spi_enable(false);
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}
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}
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void lcd_init_device(void)
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{
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semaphore_init(&g_wait_sema, 1, 0);
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/* I'm not really sure this pin is related to power, it does not seem to do anything */
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imx233_pinctrl_acquire(1, 8, "lcd_power");
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imx233_pinctrl_acquire(1, 9, "lcd_spi_sdo");
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imx233_pinctrl_acquire(1, 10, "lcd_spi_scl");
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imx233_pinctrl_acquire(1, 11, "lcd_spi_cs");
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imx233_pinctrl_set_function(1, 9, PINCTRL_FUNCTION_GPIO);
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imx233_pinctrl_set_function(1, 10, PINCTRL_FUNCTION_GPIO);
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imx233_pinctrl_set_function(1, 11, PINCTRL_FUNCTION_GPIO);
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imx233_pinctrl_set_function(1, 8, PINCTRL_FUNCTION_GPIO);
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imx233_pinctrl_enable_gpio(1, 8, true);
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/** lcd is 320x240, data bus is 8-bit, depth is 24-bit so we need 3clk/pix
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* by running PIX clock at 24MHz we can sustain ~100 fps */
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imx233_clkctrl_enable(CLK_PIX, false);
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imx233_clkctrl_set_div(CLK_PIX, 2);
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imx233_clkctrl_set_bypass(CLK_PIX, true); /* use XTAL */
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imx233_clkctrl_enable(CLK_PIX, true);
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imx233_dma_reset_channel(APB_LCDIF);
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imx233_dma_clkgate_channel(APB_LCDIF, true);
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imx233_lcdif_init();
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imx233_lcdif_setup_dotclk_pins(8, false);
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imx233_lcdif_set_word_length(8);
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/** Datasheet states:
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* 257H >= VBP >= 3H, VBP > VLW, VFP >= 1H
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* 1533clk >= HBP >= 24clk, HBP > HLW, HFP >= 4clk
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*
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* Take VLW=1H, VBP=3H, VFP=1H, HLW=8, HBP=24, HFP=4
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* Take 3clk/pix because we send 24-bit/pix with 8-bit data bus
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* Keep consistent with register setting in lcd_init_seq
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*/
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imx233_lcdif_setup_dotclk_ex(/*v_pulse_width*/1, /*v_back_porch*/3,
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/*v_front_porch*/1, /*h_pulse_width*/8, /*h_back_porch*/24,
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/*h_front_porch*/4, LCD_WIDTH, LCD_HEIGHT, /*clk_per_pix*/3,
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/*enable_present*/false);
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imx233_lcdif_set_byte_packing_format(0xf);
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// setup dma
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unsigned size = IMX233_FRAMEBUFFER_SIZE;
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uint8_t *frame_p = FRAME;
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for(int i = 0; i < NR_CMDS; i++)
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{
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unsigned xfer = MIN(IMX233_MAX_SINGLE_DMA_XFER_SIZE, size);
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lcdif_dma[i].dma.next = &lcdif_dma[(i + 1) % NR_CMDS].dma;
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lcdif_dma[i].dma.cmd = BF_OR3(APB_CHx_CMD, CHAIN(1),
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COMMAND(BV_APB_CHx_CMD_COMMAND__READ), XFER_COUNT(xfer));
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lcdif_dma[i].dma.buffer = frame_p;
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size -= xfer;
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frame_p += xfer;
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}
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// enable
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lcd_enable(true);
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}
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void lcd_update(void)
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{
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lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
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}
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void lcd_update_rect(int x, int y, int w, int h)
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{
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#ifdef HAVE_LCD_ENABLE
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if(!lcd_on)
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return;
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#endif
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for(int yy = y; yy < y + h; yy++)
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{
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uint16_t *pix = FBADDR(x, yy);
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uint8_t *p = 3 * (yy * LCD_WIDTH + x) + (uint8_t *)FRAME;
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for(int xx = 0; xx < w; xx++, pix++)
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{
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*p++ = RGB_UNPACK_RED(*pix);
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*p++ = RGB_UNPACK_GREEN(*pix);
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*p++ = RGB_UNPACK_BLUE(*pix);
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}
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}
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}
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