9a20d60bfb
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29234 a1c6a512-1295-4272-9138-f99709370657
153 lines
4.4 KiB
C
153 lines
4.4 KiB
C
/*
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* SPI interface driver for the DM320 SoC
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*
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* Copyright (C) 2007 shirour <mrobefan@gmail.com>
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* Copyright (C) 2007 Catalin Patulea <cat@vv.carleton.ca>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "kernel.h"
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#include "system.h"
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#include "spi.h"
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#define GIO_TS_ENABLE (1<<2)
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#define GIO_RTC_ENABLE (1<<12)
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#define GIO_BL_ENABLE (1<<13)
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#define GIO_LCD_ENABLE (1<<5)
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static struct mutex spi_mtx;
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struct SPI_info {
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volatile unsigned short *setreg;
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volatile unsigned short *clrreg;
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int bit;
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unsigned short spi_mode;
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bool clk_invert;
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};
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static const struct SPI_info spi_targets[] =
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{
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#ifndef CREATIVE_ZVx
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[SPI_target_TSC2100] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1,
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GIO_TS_ENABLE, 0x260D, true},
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/* RTC seems to have timing problems if the CLK idles low */
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[SPI_target_RX5X348AB] = { &IO_GIO_BITSET0, &IO_GIO_BITCLR0,
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GIO_RTC_ENABLE, 0x263F, true},
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/* This appears to work properly idling low, idling high is very glitchy */
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[SPI_target_BACKLIGHT] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1,
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GIO_BL_ENABLE, 0x2656, false},
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#else
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[SPI_target_LTV250QV] = { &IO_GIO_BITCLR2, &IO_GIO_BITSET2,
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GIO_LCD_ENABLE, true, 0x07},
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#endif
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};
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#define IO_SERIAL0_XMIT (0x100)
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static void spi_disable_all_targets(void)
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{
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int i;
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for(i=0;i<SPI_MAX_TARGETS;i++)
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{
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*spi_targets[i].clrreg = spi_targets[i].bit;
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}
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}
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int spi_block_transfer(enum SPI_target target,
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const uint8_t *tx_bytes, unsigned int tx_size,
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uint8_t *rx_bytes, unsigned int rx_size)
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{
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mutex_lock(&spi_mtx);
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/* Enable the clock */
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bitset16(&IO_CLK_MOD2, CLK_MOD2_SIF0);
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if(spi_targets[target].clk_invert)
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{
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bitset16(&IO_CLK_INV, (1 << 12));
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}
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else
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{
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bitclr16(&IO_CLK_INV, (1 << 12));
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}
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IO_SERIAL0_MODE = spi_targets[target].spi_mode;
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/* Activate the slave select pin */
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IO_SERIAL0_TX_ENABLE = 0x0001;
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*spi_targets[target].setreg = spi_targets[target].bit;
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while (IO_SERIAL0_RX_DATA & IO_SERIAL0_XMIT) {};
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while (tx_size--)
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{
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/* Send one byte */
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IO_SERIAL0_TX_DATA = (short)*tx_bytes++;
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/* Wait until transfer finished */
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while (IO_SERIAL0_RX_DATA & IO_SERIAL0_XMIT) {};
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}
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while (rx_size--)
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{
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unsigned short data;
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/* Make the clock tick */
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IO_SERIAL0_TX_DATA = 0;
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/* Wait until transfer finished */
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while ((data = IO_SERIAL0_RX_DATA) & IO_SERIAL0_XMIT) {};
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*rx_bytes++ = (unsigned char) data;
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}
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*spi_targets[target].clrreg = spi_targets[target].bit;
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IO_SERIAL0_TX_ENABLE = 0x0000;
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/* Disable the clock */
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bitclr16(&IO_CLK_MOD2, CLK_MOD2_SIF0);
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mutex_unlock(&spi_mtx);
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return 0;
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}
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void spi_init(void)
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{
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mutex_init(&spi_mtx);
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/* Enable the clock */
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bitset16(&IO_CLK_MOD2, CLK_MOD2_SIF0);
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/* Disable transmitter */
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IO_SERIAL0_TX_ENABLE = 0x0000;
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IO_SERIAL0_MODE = 0x0230;
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/* Make sure the SPI clock is inverted */
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bitclr16(&IO_CLK_INV, ( 1 << 12 ));
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/* make sure only one is ever enabled at a time */
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spi_disable_all_targets();
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/* Disable the clock */
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bitclr16(&IO_CLK_MOD2, CLK_MOD2_SIF0);
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}
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