8181a0c905
* settings code is not fully ready -> changing device driver has no effect * clean ups * check copyriths * find a way to detect IN transfers * support for full and highspeed * ... git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14470 a1c6a512-1295-4272-9138-f99709370657
264 lines
7.9 KiB
C
264 lines
7.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "thread.h"
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#include "i2s.h"
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#if NUM_CORES > 1
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struct mutex boostctrl_mtx NOCACHEBSS_ATTR;
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#endif
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#ifndef BOOTLOADER
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extern void TIMER1(void);
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extern void TIMER2(void);
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extern void ipod_mini_button_int(void); /* iPod Mini 1st gen only */
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extern void ipod_4g_button_int(void); /* iPod 4th gen and higher only */
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#ifdef SANSA_E200
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extern void button_int(void);
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extern void clickwheel_int(void);
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extern void microsd_int(void);
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#endif
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#ifdef HAVE_USBSTACK
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#include "usbstack/core.h"
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#endif
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void irq(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK) {
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TIMER1();
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#ifdef HAVE_USBSTACK
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usb_stack_irq();
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#endif
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} else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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#if defined(IPOD_MINI) /* Mini 1st gen only, mini 2nd gen uses iPod 4G code */
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else if (CPU_HI_INT_STAT & GPIO_MASK)
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ipod_mini_button_int();
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#elif CONFIG_KEYPAD == IPOD_4G_PAD /* except Mini 1st gen, handled above */
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else if (CPU_HI_INT_STAT & I2C_MASK)
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ipod_4g_button_int();
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#elif defined(SANSA_E200)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if (GPIOA_INT_STAT & 0x80)
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microsd_int();
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}
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else if (CPU_HI_INT_STAT & GPIO1_MASK) {
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if (GPIOF_INT_STAT & 0xff)
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button_int();
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if (GPIOH_INT_STAT & 0xc0)
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clickwheel_int();
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}
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#endif
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#endif /* BOOTLOADER */
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/* TODO: The following function has been lifted straight from IPL, and
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hence has a lot of numeric addresses used straight. I'd like to use
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#defines for these, but don't know what most of them are for or even what
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they should be named. Because of this I also have no way of knowing how
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to extend the funtions to do alternate cache configurations. */
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#ifndef BOOTLOADER
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static void ipod_init_cache(void)
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{
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/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
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unsigned i;
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/* cache init mode? */
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CACHE_CTL = CACHE_INIT;
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/* PP5002 has 8KB cache */
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for (i = 0xf0004000; i < 0xf0006000; i += 16) {
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outl(0x0, i);
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}
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outl(0x0, 0xf000f040);
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outl(0x3fc0, 0xf000f044);
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/* enable cache */
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CACHE_CTL = CACHE_ENABLE;
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for (i = 0x10000000; i < 0x10002000; i += 16)
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inb(i);
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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#else
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static void pp_set_cpu_frequency(long frequency)
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#endif
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{
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unsigned long clcd_clock_src;
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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/* Using mutex or spinlock isn't safe here. */
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while (test_and_set(&boostctrl_mtx.locked, 1)) ;
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#endif
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#ifdef SANSA_E200
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i2s_scale_attn_level(CPUFREQ_DEFAULT);
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#endif
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cpu_frequency = frequency;
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clcd_clock_src = CLCD_CLOCK_SRC; /* save selected color LCD clock source */
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switch (frequency)
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{
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/* Note: The PP5022 PLL must be run at >= 96MHz
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* Bits 20..21 select the post divider (1/2/4/8).
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* PP5026 is similar to PP5022 except it doesn't
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* have this limitation (and the post divider?) */
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case CPUFREQ_MAX:
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CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */
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CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
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DEV_TIMING1 = 0x00000808;
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#if CONFIG_CPU == PP5020
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PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */
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PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */
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PLL_CONTROL = 0x8a020a03; /* repeat setup */
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udelay(500); /* wait for relock */
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#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
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PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */
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udelay(250);
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while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
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#endif
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break;
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case CPUFREQ_NORMAL:
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CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */
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CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
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DEV_TIMING1 = 0x00000303;
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#if CONFIG_CPU == PP5020
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PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */
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udelay(500); /* wait for relock */
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#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
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PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */
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udelay(250);
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while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
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#endif
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break;
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case CPUFREQ_SLEEP:
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CLOCK_SOURCE = 0x10002202; /* source #2: 32kHz, #1, #3, #4: 24MHz */
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CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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udelay(10000); /* let 32kHz source stabilize? */
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break;
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default:
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CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */
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CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
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DEV_TIMING1 = 0x00000303;
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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cpu_frequency = CPUFREQ_DEFAULT;
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break;
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}
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CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf0000000) | 0x20000000; /* select source #2 */
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CLCD_CLOCK_SRC; /* dummy read (to sync the write pipeline??) */
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CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */
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#ifdef SANSA_E200
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i2s_scale_attn_level(frequency);
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#endif
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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boostctrl_mtx.locked = 0;
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#endif
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}
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#endif /* !BOOTLOADER */
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void system_init(void)
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{
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#ifndef BOOTLOADER
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if (CURRENT_CORE == CPU)
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{
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#ifdef SANSA_E200
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/* Reset all devices */
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DEV_RS = 0x3bfffef8;
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outl(0xffffffff, 0x60006008);
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DEV_RS = 0;
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outl(0x00000000, 0x60006008);
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#endif
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/* Remap the flash ROM from 0x00000000 to 0x20000000. */
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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/* disable all irqs */
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COP_HI_INT_CLR = -1;
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CPU_HI_INT_CLR = -1;
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HI_INT_FORCED_CLR = -1;
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COP_INT_CLR = -1;
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CPU_INT_CLR = -1;
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INT_FORCED_CLR = -1;
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GPIOA_INT_EN = 0;
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GPIOB_INT_EN = 0;
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GPIOC_INT_EN = 0;
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GPIOD_INT_EN = 0;
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GPIOE_INT_EN = 0;
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GPIOF_INT_EN = 0;
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GPIOG_INT_EN = 0;
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GPIOH_INT_EN = 0;
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GPIOI_INT_EN = 0;
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GPIOJ_INT_EN = 0;
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GPIOK_INT_EN = 0;
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GPIOL_INT_EN = 0;
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#ifdef SANSA_E200
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/* outl(0x00000000, 0x6000b000); */
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outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */
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#endif
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DEV_INIT |= 1 << 30; /* enable PLL power */
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#if NUM_CORES > 1
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spinlock_init(&boostctrl_mtx);
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#endif
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#else
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pp_set_cpu_frequency(CPUFREQ_MAX);
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#endif
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}
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ipod_init_cache();
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#endif /* BOOTLOADER */
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}
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void system_reboot(void)
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{
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/* Reboot */
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DEV_RS |= DEV_SYSTEM;
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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