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rockbox/firmware/target/arm/imx233/regs/stmp3700/emi.h
Amaury Pouly eac1ca22bd imx233: generate register headers using headergen_v2 and update code for it 
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.

The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
  BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
  BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
  its equivalent for BF_WR(reg_SET, ...)

I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".

Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml

Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-28 16:49:22 +02:00

291 lines
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stmp3700 version: 2.4.0
* stmp3700 authors: Amaury Pouly
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_STMP3700_EMI_H__
#define __HEADERGEN_STMP3700_EMI_H__
#define HW_EMI_CTRL HW(EMI_CTRL)
#define HWA_EMI_CTRL (0x80020000 + 0x0)
#define HWT_EMI_CTRL HWIO_32_RW
#define HWN_EMI_CTRL EMI_CTRL
#define HWI_EMI_CTRL
#define HW_EMI_CTRL_SET HW(EMI_CTRL_SET)
#define HWA_EMI_CTRL_SET (HWA_EMI_CTRL + 0x4)
#define HWT_EMI_CTRL_SET HWIO_32_WO
#define HWN_EMI_CTRL_SET EMI_CTRL
#define HWI_EMI_CTRL_SET
#define HW_EMI_CTRL_CLR HW(EMI_CTRL_CLR)
#define HWA_EMI_CTRL_CLR (HWA_EMI_CTRL + 0x8)
#define HWT_EMI_CTRL_CLR HWIO_32_WO
#define HWN_EMI_CTRL_CLR EMI_CTRL
#define HWI_EMI_CTRL_CLR
#define HW_EMI_CTRL_TOG HW(EMI_CTRL_TOG)
#define HWA_EMI_CTRL_TOG (HWA_EMI_CTRL + 0xc)
#define HWT_EMI_CTRL_TOG HWIO_32_WO
#define HWN_EMI_CTRL_TOG EMI_CTRL
#define HWI_EMI_CTRL_TOG
#define BP_EMI_CTRL_SFTRST 31
#define BM_EMI_CTRL_SFTRST 0x80000000
#define BF_EMI_CTRL_SFTRST(v) (((v) & 0x1) << 31)
#define BFM_EMI_CTRL_SFTRST(v) BM_EMI_CTRL_SFTRST
#define BF_EMI_CTRL_SFTRST_V(e) BF_EMI_CTRL_SFTRST(BV_EMI_CTRL_SFTRST__##e)
#define BFM_EMI_CTRL_SFTRST_V(v) BM_EMI_CTRL_SFTRST
#define BP_EMI_CTRL_CLKGATE 30
#define BM_EMI_CTRL_CLKGATE 0x40000000
#define BF_EMI_CTRL_CLKGATE(v) (((v) & 0x1) << 30)
#define BFM_EMI_CTRL_CLKGATE(v) BM_EMI_CTRL_CLKGATE
#define BF_EMI_CTRL_CLKGATE_V(e) BF_EMI_CTRL_CLKGATE(BV_EMI_CTRL_CLKGATE__##e)
#define BFM_EMI_CTRL_CLKGATE_V(v) BM_EMI_CTRL_CLKGATE
#define BP_EMI_CTRL_MEM_WIDTH 6
#define BM_EMI_CTRL_MEM_WIDTH 0x40
#define BF_EMI_CTRL_MEM_WIDTH(v) (((v) & 0x1) << 6)
#define BFM_EMI_CTRL_MEM_WIDTH(v) BM_EMI_CTRL_MEM_WIDTH
#define BF_EMI_CTRL_MEM_WIDTH_V(e) BF_EMI_CTRL_MEM_WIDTH(BV_EMI_CTRL_MEM_WIDTH__##e)
#define BFM_EMI_CTRL_MEM_WIDTH_V(v) BM_EMI_CTRL_MEM_WIDTH
#define BP_EMI_CTRL_WRITE_PROTECT 5
#define BM_EMI_CTRL_WRITE_PROTECT 0x20
#define BF_EMI_CTRL_WRITE_PROTECT(v) (((v) & 0x1) << 5)
#define BFM_EMI_CTRL_WRITE_PROTECT(v) BM_EMI_CTRL_WRITE_PROTECT
#define BF_EMI_CTRL_WRITE_PROTECT_V(e) BF_EMI_CTRL_WRITE_PROTECT(BV_EMI_CTRL_WRITE_PROTECT__##e)
#define BFM_EMI_CTRL_WRITE_PROTECT_V(v) BM_EMI_CTRL_WRITE_PROTECT
#define BP_EMI_CTRL_RESET_OUT 4
#define BM_EMI_CTRL_RESET_OUT 0x10
#define BF_EMI_CTRL_RESET_OUT(v) (((v) & 0x1) << 4)
#define BFM_EMI_CTRL_RESET_OUT(v) BM_EMI_CTRL_RESET_OUT
#define BF_EMI_CTRL_RESET_OUT_V(e) BF_EMI_CTRL_RESET_OUT(BV_EMI_CTRL_RESET_OUT__##e)
#define BFM_EMI_CTRL_RESET_OUT_V(v) BM_EMI_CTRL_RESET_OUT
#define BP_EMI_CTRL_CE_SELECT 0
#define BM_EMI_CTRL_CE_SELECT 0xf
#define BV_EMI_CTRL_CE_SELECT__NONE 0x0
#define BV_EMI_CTRL_CE_SELECT__CE0 0x1
#define BV_EMI_CTRL_CE_SELECT__CE1 0x2
#define BV_EMI_CTRL_CE_SELECT__CE2 0x4
#define BV_EMI_CTRL_CE_SELECT__CE3 0x8
#define BF_EMI_CTRL_CE_SELECT(v) (((v) & 0xf) << 0)
#define BFM_EMI_CTRL_CE_SELECT(v) BM_EMI_CTRL_CE_SELECT
#define BF_EMI_CTRL_CE_SELECT_V(e) BF_EMI_CTRL_CE_SELECT(BV_EMI_CTRL_CE_SELECT__##e)
#define BFM_EMI_CTRL_CE_SELECT_V(v) BM_EMI_CTRL_CE_SELECT
#define HW_EMI_STAT HW(EMI_STAT)
#define HWA_EMI_STAT (0x80020000 + 0x10)
#define HWT_EMI_STAT HWIO_32_RW
#define HWN_EMI_STAT EMI_STAT
#define HWI_EMI_STAT
#define BP_EMI_STAT_DRAM_PRESENT 31
#define BM_EMI_STAT_DRAM_PRESENT 0x80000000
#define BF_EMI_STAT_DRAM_PRESENT(v) (((v) & 0x1) << 31)
#define BFM_EMI_STAT_DRAM_PRESENT(v) BM_EMI_STAT_DRAM_PRESENT
#define BF_EMI_STAT_DRAM_PRESENT_V(e) BF_EMI_STAT_DRAM_PRESENT(BV_EMI_STAT_DRAM_PRESENT__##e)
#define BFM_EMI_STAT_DRAM_PRESENT_V(v) BM_EMI_STAT_DRAM_PRESENT
#define BP_EMI_STAT_NOR_PRESENT 30
#define BM_EMI_STAT_NOR_PRESENT 0x40000000
#define BF_EMI_STAT_NOR_PRESENT(v) (((v) & 0x1) << 30)
#define BFM_EMI_STAT_NOR_PRESENT(v) BM_EMI_STAT_NOR_PRESENT
#define BF_EMI_STAT_NOR_PRESENT_V(e) BF_EMI_STAT_NOR_PRESENT(BV_EMI_STAT_NOR_PRESENT__##e)
#define BFM_EMI_STAT_NOR_PRESENT_V(v) BM_EMI_STAT_NOR_PRESENT
#define BP_EMI_STAT_LARGE_DRAM_ENABLED 29
#define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000
#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v) (((v) & 0x1) << 29)
#define BFM_EMI_STAT_LARGE_DRAM_ENABLED(v) BM_EMI_STAT_LARGE_DRAM_ENABLED
#define BF_EMI_STAT_LARGE_DRAM_ENABLED_V(e) BF_EMI_STAT_LARGE_DRAM_ENABLED(BV_EMI_STAT_LARGE_DRAM_ENABLED__##e)
#define BFM_EMI_STAT_LARGE_DRAM_ENABLED_V(v) BM_EMI_STAT_LARGE_DRAM_ENABLED
#define BP_EMI_STAT_DRAM_HALTED 1
#define BM_EMI_STAT_DRAM_HALTED 0x2
#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0
#define BV_EMI_STAT_DRAM_HALTED__HALTED 0x1
#define BF_EMI_STAT_DRAM_HALTED(v) (((v) & 0x1) << 1)
#define BFM_EMI_STAT_DRAM_HALTED(v) BM_EMI_STAT_DRAM_HALTED
#define BF_EMI_STAT_DRAM_HALTED_V(e) BF_EMI_STAT_DRAM_HALTED(BV_EMI_STAT_DRAM_HALTED__##e)
#define BFM_EMI_STAT_DRAM_HALTED_V(v) BM_EMI_STAT_DRAM_HALTED
#define BP_EMI_STAT_NOR_BUSY 0
#define BM_EMI_STAT_NOR_BUSY 0x1
#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY 0x0
#define BV_EMI_STAT_NOR_BUSY__BUSY 0x1
#define BF_EMI_STAT_NOR_BUSY(v) (((v) & 0x1) << 0)
#define BFM_EMI_STAT_NOR_BUSY(v) BM_EMI_STAT_NOR_BUSY
#define BF_EMI_STAT_NOR_BUSY_V(e) BF_EMI_STAT_NOR_BUSY(BV_EMI_STAT_NOR_BUSY__##e)
#define BFM_EMI_STAT_NOR_BUSY_V(v) BM_EMI_STAT_NOR_BUSY
#define HW_EMI_TIME HW(EMI_TIME)
#define HWA_EMI_TIME (0x80020000 + 0x20)
#define HWT_EMI_TIME HWIO_32_RW
#define HWN_EMI_TIME EMI_TIME
#define HWI_EMI_TIME
#define HW_EMI_TIME_SET HW(EMI_TIME_SET)
#define HWA_EMI_TIME_SET (HWA_EMI_TIME + 0x4)
#define HWT_EMI_TIME_SET HWIO_32_WO
#define HWN_EMI_TIME_SET EMI_TIME
#define HWI_EMI_TIME_SET
#define HW_EMI_TIME_CLR HW(EMI_TIME_CLR)
#define HWA_EMI_TIME_CLR (HWA_EMI_TIME + 0x8)
#define HWT_EMI_TIME_CLR HWIO_32_WO
#define HWN_EMI_TIME_CLR EMI_TIME
#define HWI_EMI_TIME_CLR
#define HW_EMI_TIME_TOG HW(EMI_TIME_TOG)
#define HWA_EMI_TIME_TOG (HWA_EMI_TIME + 0xc)
#define HWT_EMI_TIME_TOG HWIO_32_WO
#define HWN_EMI_TIME_TOG EMI_TIME
#define HWI_EMI_TIME_TOG
#define BP_EMI_TIME_THZ 24
#define BM_EMI_TIME_THZ 0xf000000
#define BF_EMI_TIME_THZ(v) (((v) & 0xf) << 24)
#define BFM_EMI_TIME_THZ(v) BM_EMI_TIME_THZ
#define BF_EMI_TIME_THZ_V(e) BF_EMI_TIME_THZ(BV_EMI_TIME_THZ__##e)
#define BFM_EMI_TIME_THZ_V(v) BM_EMI_TIME_THZ
#define BP_EMI_TIME_TDH 16
#define BM_EMI_TIME_TDH 0xf0000
#define BF_EMI_TIME_TDH(v) (((v) & 0xf) << 16)
#define BFM_EMI_TIME_TDH(v) BM_EMI_TIME_TDH
#define BF_EMI_TIME_TDH_V(e) BF_EMI_TIME_TDH(BV_EMI_TIME_TDH__##e)
#define BFM_EMI_TIME_TDH_V(v) BM_EMI_TIME_TDH
#define BP_EMI_TIME_TDS 8
#define BM_EMI_TIME_TDS 0x1f00
#define BF_EMI_TIME_TDS(v) (((v) & 0x1f) << 8)
#define BFM_EMI_TIME_TDS(v) BM_EMI_TIME_TDS
#define BF_EMI_TIME_TDS_V(e) BF_EMI_TIME_TDS(BV_EMI_TIME_TDS__##e)
#define BFM_EMI_TIME_TDS_V(v) BM_EMI_TIME_TDS
#define BP_EMI_TIME_TAS 0
#define BM_EMI_TIME_TAS 0xf
#define BF_EMI_TIME_TAS(v) (((v) & 0xf) << 0)
#define BFM_EMI_TIME_TAS(v) BM_EMI_TIME_TAS
#define BF_EMI_TIME_TAS_V(e) BF_EMI_TIME_TAS(BV_EMI_TIME_TAS__##e)
#define BFM_EMI_TIME_TAS_V(v) BM_EMI_TIME_TAS
#define HW_EMI_DDR_TEST_MODE_CSR HW(EMI_DDR_TEST_MODE_CSR)
#define HWA_EMI_DDR_TEST_MODE_CSR (0x80020000 + 0x30)
#define HWT_EMI_DDR_TEST_MODE_CSR HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_CSR EMI_DDR_TEST_MODE_CSR
#define HWI_EMI_DDR_TEST_MODE_CSR
#define HW_EMI_DDR_TEST_MODE_CSR_SET HW(EMI_DDR_TEST_MODE_CSR_SET)
#define HWA_EMI_DDR_TEST_MODE_CSR_SET (HWA_EMI_DDR_TEST_MODE_CSR + 0x4)
#define HWT_EMI_DDR_TEST_MODE_CSR_SET HWIO_32_WO
#define HWN_EMI_DDR_TEST_MODE_CSR_SET EMI_DDR_TEST_MODE_CSR
#define HWI_EMI_DDR_TEST_MODE_CSR_SET
#define HW_EMI_DDR_TEST_MODE_CSR_CLR HW(EMI_DDR_TEST_MODE_CSR_CLR)
#define HWA_EMI_DDR_TEST_MODE_CSR_CLR (HWA_EMI_DDR_TEST_MODE_CSR + 0x8)
#define HWT_EMI_DDR_TEST_MODE_CSR_CLR HWIO_32_WO
#define HWN_EMI_DDR_TEST_MODE_CSR_CLR EMI_DDR_TEST_MODE_CSR
#define HWI_EMI_DDR_TEST_MODE_CSR_CLR
#define HW_EMI_DDR_TEST_MODE_CSR_TOG HW(EMI_DDR_TEST_MODE_CSR_TOG)
#define HWA_EMI_DDR_TEST_MODE_CSR_TOG (HWA_EMI_DDR_TEST_MODE_CSR + 0xc)
#define HWT_EMI_DDR_TEST_MODE_CSR_TOG HWIO_32_WO
#define HWN_EMI_DDR_TEST_MODE_CSR_TOG EMI_DDR_TEST_MODE_CSR
#define HWI_EMI_DDR_TEST_MODE_CSR_TOG
#define BP_EMI_DDR_TEST_MODE_CSR_DONE 1
#define BM_EMI_DDR_TEST_MODE_CSR_DONE 0x2
#define BF_EMI_DDR_TEST_MODE_CSR_DONE(v) (((v) & 0x1) << 1)
#define BFM_EMI_DDR_TEST_MODE_CSR_DONE(v) BM_EMI_DDR_TEST_MODE_CSR_DONE
#define BF_EMI_DDR_TEST_MODE_CSR_DONE_V(e) BF_EMI_DDR_TEST_MODE_CSR_DONE(BV_EMI_DDR_TEST_MODE_CSR_DONE__##e)
#define BFM_EMI_DDR_TEST_MODE_CSR_DONE_V(v) BM_EMI_DDR_TEST_MODE_CSR_DONE
#define BP_EMI_DDR_TEST_MODE_CSR_START 0
#define BM_EMI_DDR_TEST_MODE_CSR_START 0x1
#define BF_EMI_DDR_TEST_MODE_CSR_START(v) (((v) & 0x1) << 0)
#define BFM_EMI_DDR_TEST_MODE_CSR_START(v) BM_EMI_DDR_TEST_MODE_CSR_START
#define BF_EMI_DDR_TEST_MODE_CSR_START_V(e) BF_EMI_DDR_TEST_MODE_CSR_START(BV_EMI_DDR_TEST_MODE_CSR_START__##e)
#define BFM_EMI_DDR_TEST_MODE_CSR_START_V(v) BM_EMI_DDR_TEST_MODE_CSR_START
#define HW_EMI_DEBUG HW(EMI_DEBUG)
#define HWA_EMI_DEBUG (0x80020000 + 0x80)
#define HWT_EMI_DEBUG HWIO_32_RW
#define HWN_EMI_DEBUG EMI_DEBUG
#define HWI_EMI_DEBUG
#define BP_EMI_DEBUG_NOR_STATE 0
#define BM_EMI_DEBUG_NOR_STATE 0xf
#define BF_EMI_DEBUG_NOR_STATE(v) (((v) & 0xf) << 0)
#define BFM_EMI_DEBUG_NOR_STATE(v) BM_EMI_DEBUG_NOR_STATE
#define BF_EMI_DEBUG_NOR_STATE_V(e) BF_EMI_DEBUG_NOR_STATE(BV_EMI_DEBUG_NOR_STATE__##e)
#define BFM_EMI_DEBUG_NOR_STATE_V(v) BM_EMI_DEBUG_NOR_STATE
#define HW_EMI_DDR_TEST_MODE_STATUS0 HW(EMI_DDR_TEST_MODE_STATUS0)
#define HWA_EMI_DDR_TEST_MODE_STATUS0 (0x80020000 + 0x90)
#define HWT_EMI_DDR_TEST_MODE_STATUS0 HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_STATUS0 EMI_DDR_TEST_MODE_STATUS0
#define HWI_EMI_DDR_TEST_MODE_STATUS0
#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0
#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0x1fff
#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v) (((v) & 0x1fff) << 0)
#define BFM_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v) BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0
#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0_V(e) BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(BV_EMI_DDR_TEST_MODE_STATUS0_ADDR0__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS0_ADDR0_V(v) BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0
#define HW_EMI_DDR_TEST_MODE_STATUS1 HW(EMI_DDR_TEST_MODE_STATUS1)
#define HWA_EMI_DDR_TEST_MODE_STATUS1 (0x80020000 + 0xa0)
#define HWT_EMI_DDR_TEST_MODE_STATUS1 HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_STATUS1 EMI_DDR_TEST_MODE_STATUS1
#define HWI_EMI_DDR_TEST_MODE_STATUS1
#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0
#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0x1fff
#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v) (((v) & 0x1fff) << 0)
#define BFM_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v) BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1
#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1_V(e) BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(BV_EMI_DDR_TEST_MODE_STATUS1_ADDR1__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS1_ADDR1_V(v) BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1
#define HW_EMI_DDR_TEST_MODE_STATUS2 HW(EMI_DDR_TEST_MODE_STATUS2)
#define HWA_EMI_DDR_TEST_MODE_STATUS2 (0x80020000 + 0xb0)
#define HWT_EMI_DDR_TEST_MODE_STATUS2 HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_STATUS2 EMI_DDR_TEST_MODE_STATUS2
#define HWI_EMI_DDR_TEST_MODE_STATUS2
#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0 0
#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0 0xffffffff
#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v) (((v) & 0xffffffff) << 0)
#define BFM_EMI_DDR_TEST_MODE_STATUS2_DATA0(v) BM_EMI_DDR_TEST_MODE_STATUS2_DATA0
#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0_V(e) BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(BV_EMI_DDR_TEST_MODE_STATUS2_DATA0__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS2_DATA0_V(v) BM_EMI_DDR_TEST_MODE_STATUS2_DATA0
#define HW_EMI_DDR_TEST_MODE_STATUS3 HW(EMI_DDR_TEST_MODE_STATUS3)
#define HWA_EMI_DDR_TEST_MODE_STATUS3 (0x80020000 + 0xc0)
#define HWT_EMI_DDR_TEST_MODE_STATUS3 HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_STATUS3 EMI_DDR_TEST_MODE_STATUS3
#define HWI_EMI_DDR_TEST_MODE_STATUS3
#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1 0
#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1 0xffffffff
#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v) (((v) & 0xffffffff) << 0)
#define BFM_EMI_DDR_TEST_MODE_STATUS3_DATA1(v) BM_EMI_DDR_TEST_MODE_STATUS3_DATA1
#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1_V(e) BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(BV_EMI_DDR_TEST_MODE_STATUS3_DATA1__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS3_DATA1_V(v) BM_EMI_DDR_TEST_MODE_STATUS3_DATA1
#define HW_EMI_VERSION HW(EMI_VERSION)
#define HWA_EMI_VERSION (0x80020000 + 0xf0)
#define HWT_EMI_VERSION HWIO_32_RW
#define HWN_EMI_VERSION EMI_VERSION
#define HWI_EMI_VERSION
#define BP_EMI_VERSION_MAJOR 24
#define BM_EMI_VERSION_MAJOR 0xff000000
#define BF_EMI_VERSION_MAJOR(v) (((v) & 0xff) << 24)
#define BFM_EMI_VERSION_MAJOR(v) BM_EMI_VERSION_MAJOR
#define BF_EMI_VERSION_MAJOR_V(e) BF_EMI_VERSION_MAJOR(BV_EMI_VERSION_MAJOR__##e)
#define BFM_EMI_VERSION_MAJOR_V(v) BM_EMI_VERSION_MAJOR
#define BP_EMI_VERSION_MINOR 16
#define BM_EMI_VERSION_MINOR 0xff0000
#define BF_EMI_VERSION_MINOR(v) (((v) & 0xff) << 16)
#define BFM_EMI_VERSION_MINOR(v) BM_EMI_VERSION_MINOR
#define BF_EMI_VERSION_MINOR_V(e) BF_EMI_VERSION_MINOR(BV_EMI_VERSION_MINOR__##e)
#define BFM_EMI_VERSION_MINOR_V(v) BM_EMI_VERSION_MINOR
#define BP_EMI_VERSION_STEP 0
#define BM_EMI_VERSION_STEP 0xffff
#define BF_EMI_VERSION_STEP(v) (((v) & 0xffff) << 0)
#define BFM_EMI_VERSION_STEP(v) BM_EMI_VERSION_STEP
#define BF_EMI_VERSION_STEP_V(e) BF_EMI_VERSION_STEP(BV_EMI_VERSION_STEP__##e)
#define BFM_EMI_VERSION_STEP_V(v) BM_EMI_VERSION_STEP
#endif /* __HEADERGEN_STMP3700_EMI_H__*/
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