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rockbox/firmware/target/arm/imx233/regs/stmp3600/i2c.h
Amaury Pouly eac1ca22bd imx233: generate register headers using headergen_v2 and update code for it 
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.

The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
  BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
  BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
  its equivalent for BF_WR(reg_SET, ...)

I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".

Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml

Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-28 16:49:22 +02:00

798 lines
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stmp3600 version: 2.4.0
* stmp3600 authors: Amaury Pouly
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_STMP3600_I2C_H__
#define __HEADERGEN_STMP3600_I2C_H__
#define HW_I2C_CTRL0 HW(I2C_CTRL0)
#define HWA_I2C_CTRL0 (0x80058000 + 0x0)
#define HWT_I2C_CTRL0 HWIO_32_RW
#define HWN_I2C_CTRL0 I2C_CTRL0
#define HWI_I2C_CTRL0
#define HW_I2C_CTRL0_SET HW(I2C_CTRL0_SET)
#define HWA_I2C_CTRL0_SET (HWA_I2C_CTRL0 + 0x4)
#define HWT_I2C_CTRL0_SET HWIO_32_WO
#define HWN_I2C_CTRL0_SET I2C_CTRL0
#define HWI_I2C_CTRL0_SET
#define HW_I2C_CTRL0_CLR HW(I2C_CTRL0_CLR)
#define HWA_I2C_CTRL0_CLR (HWA_I2C_CTRL0 + 0x8)
#define HWT_I2C_CTRL0_CLR HWIO_32_WO
#define HWN_I2C_CTRL0_CLR I2C_CTRL0
#define HWI_I2C_CTRL0_CLR
#define HW_I2C_CTRL0_TOG HW(I2C_CTRL0_TOG)
#define HWA_I2C_CTRL0_TOG (HWA_I2C_CTRL0 + 0xc)
#define HWT_I2C_CTRL0_TOG HWIO_32_WO
#define HWN_I2C_CTRL0_TOG I2C_CTRL0
#define HWI_I2C_CTRL0_TOG
#define BP_I2C_CTRL0_SFTRST 31
#define BM_I2C_CTRL0_SFTRST 0x80000000
#define BV_I2C_CTRL0_SFTRST__RUN 0x0
#define BV_I2C_CTRL0_SFTRST__RESET 0x1
#define BF_I2C_CTRL0_SFTRST(v) (((v) & 0x1) << 31)
#define BFM_I2C_CTRL0_SFTRST(v) BM_I2C_CTRL0_SFTRST
#define BF_I2C_CTRL0_SFTRST_V(e) BF_I2C_CTRL0_SFTRST(BV_I2C_CTRL0_SFTRST__##e)
#define BFM_I2C_CTRL0_SFTRST_V(v) BM_I2C_CTRL0_SFTRST
#define BP_I2C_CTRL0_CLKGATE 30
#define BM_I2C_CTRL0_CLKGATE 0x40000000
#define BV_I2C_CTRL0_CLKGATE__RUN 0x0
#define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1
#define BF_I2C_CTRL0_CLKGATE(v) (((v) & 0x1) << 30)
#define BFM_I2C_CTRL0_CLKGATE(v) BM_I2C_CTRL0_CLKGATE
#define BF_I2C_CTRL0_CLKGATE_V(e) BF_I2C_CTRL0_CLKGATE(BV_I2C_CTRL0_CLKGATE__##e)
#define BFM_I2C_CTRL0_CLKGATE_V(v) BM_I2C_CTRL0_CLKGATE
#define BP_I2C_CTRL0_RUN 29
#define BM_I2C_CTRL0_RUN 0x20000000
#define BV_I2C_CTRL0_RUN__HALT 0x0
#define BV_I2C_CTRL0_RUN__RUN 0x1
#define BF_I2C_CTRL0_RUN(v) (((v) & 0x1) << 29)
#define BFM_I2C_CTRL0_RUN(v) BM_I2C_CTRL0_RUN
#define BF_I2C_CTRL0_RUN_V(e) BF_I2C_CTRL0_RUN(BV_I2C_CTRL0_RUN__##e)
#define BFM_I2C_CTRL0_RUN_V(v) BM_I2C_CTRL0_RUN
#define BP_I2C_CTRL0_PRE_ACK 27
#define BM_I2C_CTRL0_PRE_ACK 0x8000000
#define BF_I2C_CTRL0_PRE_ACK(v) (((v) & 0x1) << 27)
#define BFM_I2C_CTRL0_PRE_ACK(v) BM_I2C_CTRL0_PRE_ACK
#define BF_I2C_CTRL0_PRE_ACK_V(e) BF_I2C_CTRL0_PRE_ACK(BV_I2C_CTRL0_PRE_ACK__##e)
#define BFM_I2C_CTRL0_PRE_ACK_V(v) BM_I2C_CTRL0_PRE_ACK
#define BP_I2C_CTRL0_ACKNOWLEDGE 26
#define BM_I2C_CTRL0_ACKNOWLEDGE 0x4000000
#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0
#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1
#define BF_I2C_CTRL0_ACKNOWLEDGE(v) (((v) & 0x1) << 26)
#define BFM_I2C_CTRL0_ACKNOWLEDGE(v) BM_I2C_CTRL0_ACKNOWLEDGE
#define BF_I2C_CTRL0_ACKNOWLEDGE_V(e) BF_I2C_CTRL0_ACKNOWLEDGE(BV_I2C_CTRL0_ACKNOWLEDGE__##e)
#define BFM_I2C_CTRL0_ACKNOWLEDGE_V(v) BM_I2C_CTRL0_ACKNOWLEDGE
#define BP_I2C_CTRL0_SEND_NAK_ON_LAST 25
#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x2000000
#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0
#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1
#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v) (((v) & 0x1) << 25)
#define BFM_I2C_CTRL0_SEND_NAK_ON_LAST(v) BM_I2C_CTRL0_SEND_NAK_ON_LAST
#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(e) BF_I2C_CTRL0_SEND_NAK_ON_LAST(BV_I2C_CTRL0_SEND_NAK_ON_LAST__##e)
#define BFM_I2C_CTRL0_SEND_NAK_ON_LAST_V(v) BM_I2C_CTRL0_SEND_NAK_ON_LAST
#define BP_I2C_CTRL0_PIO_MODE 24
#define BM_I2C_CTRL0_PIO_MODE 0x1000000
#define BF_I2C_CTRL0_PIO_MODE(v) (((v) & 0x1) << 24)
#define BFM_I2C_CTRL0_PIO_MODE(v) BM_I2C_CTRL0_PIO_MODE
#define BF_I2C_CTRL0_PIO_MODE_V(e) BF_I2C_CTRL0_PIO_MODE(BV_I2C_CTRL0_PIO_MODE__##e)
#define BFM_I2C_CTRL0_PIO_MODE_V(v) BM_I2C_CTRL0_PIO_MODE
#define BP_I2C_CTRL0_MULTI_MASTER 23
#define BM_I2C_CTRL0_MULTI_MASTER 0x800000
#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0
#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1
#define BF_I2C_CTRL0_MULTI_MASTER(v) (((v) & 0x1) << 23)
#define BFM_I2C_CTRL0_MULTI_MASTER(v) BM_I2C_CTRL0_MULTI_MASTER
#define BF_I2C_CTRL0_MULTI_MASTER_V(e) BF_I2C_CTRL0_MULTI_MASTER(BV_I2C_CTRL0_MULTI_MASTER__##e)
#define BFM_I2C_CTRL0_MULTI_MASTER_V(v) BM_I2C_CTRL0_MULTI_MASTER
#define BP_I2C_CTRL0_CLOCK_HELD 22
#define BM_I2C_CTRL0_CLOCK_HELD 0x400000
#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0
#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1
#define BF_I2C_CTRL0_CLOCK_HELD(v) (((v) & 0x1) << 22)
#define BFM_I2C_CTRL0_CLOCK_HELD(v) BM_I2C_CTRL0_CLOCK_HELD
#define BF_I2C_CTRL0_CLOCK_HELD_V(e) BF_I2C_CTRL0_CLOCK_HELD(BV_I2C_CTRL0_CLOCK_HELD__##e)
#define BFM_I2C_CTRL0_CLOCK_HELD_V(v) BM_I2C_CTRL0_CLOCK_HELD
#define BP_I2C_CTRL0_RETAIN_CLOCK 21
#define BM_I2C_CTRL0_RETAIN_CLOCK 0x200000
#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0
#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1
#define BF_I2C_CTRL0_RETAIN_CLOCK(v) (((v) & 0x1) << 21)
#define BFM_I2C_CTRL0_RETAIN_CLOCK(v) BM_I2C_CTRL0_RETAIN_CLOCK
#define BF_I2C_CTRL0_RETAIN_CLOCK_V(e) BF_I2C_CTRL0_RETAIN_CLOCK(BV_I2C_CTRL0_RETAIN_CLOCK__##e)
#define BFM_I2C_CTRL0_RETAIN_CLOCK_V(v) BM_I2C_CTRL0_RETAIN_CLOCK
#define BP_I2C_CTRL0_POST_SEND_STOP 20
#define BM_I2C_CTRL0_POST_SEND_STOP 0x100000
#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0
#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1
#define BF_I2C_CTRL0_POST_SEND_STOP(v) (((v) & 0x1) << 20)
#define BFM_I2C_CTRL0_POST_SEND_STOP(v) BM_I2C_CTRL0_POST_SEND_STOP
#define BF_I2C_CTRL0_POST_SEND_STOP_V(e) BF_I2C_CTRL0_POST_SEND_STOP(BV_I2C_CTRL0_POST_SEND_STOP__##e)
#define BFM_I2C_CTRL0_POST_SEND_STOP_V(v) BM_I2C_CTRL0_POST_SEND_STOP
#define BP_I2C_CTRL0_PRE_SEND_START 19
#define BM_I2C_CTRL0_PRE_SEND_START 0x80000
#define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0
#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1
#define BF_I2C_CTRL0_PRE_SEND_START(v) (((v) & 0x1) << 19)
#define BFM_I2C_CTRL0_PRE_SEND_START(v) BM_I2C_CTRL0_PRE_SEND_START
#define BF_I2C_CTRL0_PRE_SEND_START_V(e) BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START__##e)
#define BFM_I2C_CTRL0_PRE_SEND_START_V(v) BM_I2C_CTRL0_PRE_SEND_START
#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 18
#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x40000
#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1
#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v) (((v) & 0x1) << 18)
#define BFM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v) BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE
#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(e) BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##e)
#define BFM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v) BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE
#define BP_I2C_CTRL0_MASTER_MODE 17
#define BM_I2C_CTRL0_MASTER_MODE 0x20000
#define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0
#define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1
#define BF_I2C_CTRL0_MASTER_MODE(v) (((v) & 0x1) << 17)
#define BFM_I2C_CTRL0_MASTER_MODE(v) BM_I2C_CTRL0_MASTER_MODE
#define BF_I2C_CTRL0_MASTER_MODE_V(e) BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE__##e)
#define BFM_I2C_CTRL0_MASTER_MODE_V(v) BM_I2C_CTRL0_MASTER_MODE
#define BP_I2C_CTRL0_DIRECTION 16
#define BM_I2C_CTRL0_DIRECTION 0x10000
#define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0
#define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1
#define BF_I2C_CTRL0_DIRECTION(v) (((v) & 0x1) << 16)
#define BFM_I2C_CTRL0_DIRECTION(v) BM_I2C_CTRL0_DIRECTION
#define BF_I2C_CTRL0_DIRECTION_V(e) BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION__##e)
#define BFM_I2C_CTRL0_DIRECTION_V(v) BM_I2C_CTRL0_DIRECTION
#define BP_I2C_CTRL0_XFER_COUNT 0
#define BM_I2C_CTRL0_XFER_COUNT 0xffff
#define BF_I2C_CTRL0_XFER_COUNT(v) (((v) & 0xffff) << 0)
#define BFM_I2C_CTRL0_XFER_COUNT(v) BM_I2C_CTRL0_XFER_COUNT
#define BF_I2C_CTRL0_XFER_COUNT_V(e) BF_I2C_CTRL0_XFER_COUNT(BV_I2C_CTRL0_XFER_COUNT__##e)
#define BFM_I2C_CTRL0_XFER_COUNT_V(v) BM_I2C_CTRL0_XFER_COUNT
#define HW_I2C_TIMING0 HW(I2C_TIMING0)
#define HWA_I2C_TIMING0 (0x80058000 + 0x10)
#define HWT_I2C_TIMING0 HWIO_32_RW
#define HWN_I2C_TIMING0 I2C_TIMING0
#define HWI_I2C_TIMING0
#define HW_I2C_TIMING0_SET HW(I2C_TIMING0_SET)
#define HWA_I2C_TIMING0_SET (HWA_I2C_TIMING0 + 0x4)
#define HWT_I2C_TIMING0_SET HWIO_32_WO
#define HWN_I2C_TIMING0_SET I2C_TIMING0
#define HWI_I2C_TIMING0_SET
#define HW_I2C_TIMING0_CLR HW(I2C_TIMING0_CLR)
#define HWA_I2C_TIMING0_CLR (HWA_I2C_TIMING0 + 0x8)
#define HWT_I2C_TIMING0_CLR HWIO_32_WO
#define HWN_I2C_TIMING0_CLR I2C_TIMING0
#define HWI_I2C_TIMING0_CLR
#define HW_I2C_TIMING0_TOG HW(I2C_TIMING0_TOG)
#define HWA_I2C_TIMING0_TOG (HWA_I2C_TIMING0 + 0xc)
#define HWT_I2C_TIMING0_TOG HWIO_32_WO
#define HWN_I2C_TIMING0_TOG I2C_TIMING0
#define HWI_I2C_TIMING0_TOG
#define BP_I2C_TIMING0_HIGH_COUNT 16
#define BM_I2C_TIMING0_HIGH_COUNT 0x3ff0000
#define BF_I2C_TIMING0_HIGH_COUNT(v) (((v) & 0x3ff) << 16)
#define BFM_I2C_TIMING0_HIGH_COUNT(v) BM_I2C_TIMING0_HIGH_COUNT
#define BF_I2C_TIMING0_HIGH_COUNT_V(e) BF_I2C_TIMING0_HIGH_COUNT(BV_I2C_TIMING0_HIGH_COUNT__##e)
#define BFM_I2C_TIMING0_HIGH_COUNT_V(v) BM_I2C_TIMING0_HIGH_COUNT
#define BP_I2C_TIMING0_RCV_COUNT 0
#define BM_I2C_TIMING0_RCV_COUNT 0x3ff
#define BF_I2C_TIMING0_RCV_COUNT(v) (((v) & 0x3ff) << 0)
#define BFM_I2C_TIMING0_RCV_COUNT(v) BM_I2C_TIMING0_RCV_COUNT
#define BF_I2C_TIMING0_RCV_COUNT_V(e) BF_I2C_TIMING0_RCV_COUNT(BV_I2C_TIMING0_RCV_COUNT__##e)
#define BFM_I2C_TIMING0_RCV_COUNT_V(v) BM_I2C_TIMING0_RCV_COUNT
#define HW_I2C_TIMING1 HW(I2C_TIMING1)
#define HWA_I2C_TIMING1 (0x80058000 + 0x20)
#define HWT_I2C_TIMING1 HWIO_32_RW
#define HWN_I2C_TIMING1 I2C_TIMING1
#define HWI_I2C_TIMING1
#define HW_I2C_TIMING1_SET HW(I2C_TIMING1_SET)
#define HWA_I2C_TIMING1_SET (HWA_I2C_TIMING1 + 0x4)
#define HWT_I2C_TIMING1_SET HWIO_32_WO
#define HWN_I2C_TIMING1_SET I2C_TIMING1
#define HWI_I2C_TIMING1_SET
#define HW_I2C_TIMING1_CLR HW(I2C_TIMING1_CLR)
#define HWA_I2C_TIMING1_CLR (HWA_I2C_TIMING1 + 0x8)
#define HWT_I2C_TIMING1_CLR HWIO_32_WO
#define HWN_I2C_TIMING1_CLR I2C_TIMING1
#define HWI_I2C_TIMING1_CLR
#define HW_I2C_TIMING1_TOG HW(I2C_TIMING1_TOG)
#define HWA_I2C_TIMING1_TOG (HWA_I2C_TIMING1 + 0xc)
#define HWT_I2C_TIMING1_TOG HWIO_32_WO
#define HWN_I2C_TIMING1_TOG I2C_TIMING1
#define HWI_I2C_TIMING1_TOG
#define BP_I2C_TIMING1_LOW_COUNT 16
#define BM_I2C_TIMING1_LOW_COUNT 0x3ff0000
#define BF_I2C_TIMING1_LOW_COUNT(v) (((v) & 0x3ff) << 16)
#define BFM_I2C_TIMING1_LOW_COUNT(v) BM_I2C_TIMING1_LOW_COUNT
#define BF_I2C_TIMING1_LOW_COUNT_V(e) BF_I2C_TIMING1_LOW_COUNT(BV_I2C_TIMING1_LOW_COUNT__##e)
#define BFM_I2C_TIMING1_LOW_COUNT_V(v) BM_I2C_TIMING1_LOW_COUNT
#define BP_I2C_TIMING1_XMIT_COUNT 0
#define BM_I2C_TIMING1_XMIT_COUNT 0x3ff
#define BF_I2C_TIMING1_XMIT_COUNT(v) (((v) & 0x3ff) << 0)
#define BFM_I2C_TIMING1_XMIT_COUNT(v) BM_I2C_TIMING1_XMIT_COUNT
#define BF_I2C_TIMING1_XMIT_COUNT_V(e) BF_I2C_TIMING1_XMIT_COUNT(BV_I2C_TIMING1_XMIT_COUNT__##e)
#define BFM_I2C_TIMING1_XMIT_COUNT_V(v) BM_I2C_TIMING1_XMIT_COUNT
#define HW_I2C_TIMING2 HW(I2C_TIMING2)
#define HWA_I2C_TIMING2 (0x80058000 + 0x30)
#define HWT_I2C_TIMING2 HWIO_32_RW
#define HWN_I2C_TIMING2 I2C_TIMING2
#define HWI_I2C_TIMING2
#define HW_I2C_TIMING2_SET HW(I2C_TIMING2_SET)
#define HWA_I2C_TIMING2_SET (HWA_I2C_TIMING2 + 0x4)
#define HWT_I2C_TIMING2_SET HWIO_32_WO
#define HWN_I2C_TIMING2_SET I2C_TIMING2
#define HWI_I2C_TIMING2_SET
#define HW_I2C_TIMING2_CLR HW(I2C_TIMING2_CLR)
#define HWA_I2C_TIMING2_CLR (HWA_I2C_TIMING2 + 0x8)
#define HWT_I2C_TIMING2_CLR HWIO_32_WO
#define HWN_I2C_TIMING2_CLR I2C_TIMING2
#define HWI_I2C_TIMING2_CLR
#define HW_I2C_TIMING2_TOG HW(I2C_TIMING2_TOG)
#define HWA_I2C_TIMING2_TOG (HWA_I2C_TIMING2 + 0xc)
#define HWT_I2C_TIMING2_TOG HWIO_32_WO
#define HWN_I2C_TIMING2_TOG I2C_TIMING2
#define HWI_I2C_TIMING2_TOG
#define BP_I2C_TIMING2_BUS_FREE 16
#define BM_I2C_TIMING2_BUS_FREE 0x3ff0000
#define BF_I2C_TIMING2_BUS_FREE(v) (((v) & 0x3ff) << 16)
#define BFM_I2C_TIMING2_BUS_FREE(v) BM_I2C_TIMING2_BUS_FREE
#define BF_I2C_TIMING2_BUS_FREE_V(e) BF_I2C_TIMING2_BUS_FREE(BV_I2C_TIMING2_BUS_FREE__##e)
#define BFM_I2C_TIMING2_BUS_FREE_V(v) BM_I2C_TIMING2_BUS_FREE
#define BP_I2C_TIMING2_LEADIN_COUNT 0
#define BM_I2C_TIMING2_LEADIN_COUNT 0x3ff
#define BF_I2C_TIMING2_LEADIN_COUNT(v) (((v) & 0x3ff) << 0)
#define BFM_I2C_TIMING2_LEADIN_COUNT(v) BM_I2C_TIMING2_LEADIN_COUNT
#define BF_I2C_TIMING2_LEADIN_COUNT_V(e) BF_I2C_TIMING2_LEADIN_COUNT(BV_I2C_TIMING2_LEADIN_COUNT__##e)
#define BFM_I2C_TIMING2_LEADIN_COUNT_V(v) BM_I2C_TIMING2_LEADIN_COUNT
#define HW_I2C_CTRL1 HW(I2C_CTRL1)
#define HWA_I2C_CTRL1 (0x80058000 + 0x40)
#define HWT_I2C_CTRL1 HWIO_32_RW
#define HWN_I2C_CTRL1 I2C_CTRL1
#define HWI_I2C_CTRL1
#define HW_I2C_CTRL1_SET HW(I2C_CTRL1_SET)
#define HWA_I2C_CTRL1_SET (HWA_I2C_CTRL1 + 0x4)
#define HWT_I2C_CTRL1_SET HWIO_32_WO
#define HWN_I2C_CTRL1_SET I2C_CTRL1
#define HWI_I2C_CTRL1_SET
#define HW_I2C_CTRL1_CLR HW(I2C_CTRL1_CLR)
#define HWA_I2C_CTRL1_CLR (HWA_I2C_CTRL1 + 0x8)
#define HWT_I2C_CTRL1_CLR HWIO_32_WO
#define HWN_I2C_CTRL1_CLR I2C_CTRL1
#define HWI_I2C_CTRL1_CLR
#define HW_I2C_CTRL1_TOG HW(I2C_CTRL1_TOG)
#define HWA_I2C_CTRL1_TOG (HWA_I2C_CTRL1 + 0xc)
#define HWT_I2C_CTRL1_TOG HWIO_32_WO
#define HWN_I2C_CTRL1_TOG I2C_CTRL1
#define HWI_I2C_CTRL1_TOG
#define BP_I2C_CTRL1_BCAST_SLAVE_EN 24
#define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x1000000
#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0
#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1
#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v) (((v) & 0x1) << 24)
#define BFM_I2C_CTRL1_BCAST_SLAVE_EN(v) BM_I2C_CTRL1_BCAST_SLAVE_EN
#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(e) BF_I2C_CTRL1_BCAST_SLAVE_EN(BV_I2C_CTRL1_BCAST_SLAVE_EN__##e)
#define BFM_I2C_CTRL1_BCAST_SLAVE_EN_V(v) BM_I2C_CTRL1_BCAST_SLAVE_EN
#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16
#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0xff0000
#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) (((v) & 0xff) << 16)
#define BFM_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE
#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE_V(e) BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(BV_I2C_CTRL1_SLAVE_ADDRESS_BYTE__##e)
#define BFM_I2C_CTRL1_SLAVE_ADDRESS_BYTE_V(v) BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE
#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN 15
#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x8000
#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0
#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1
#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v) (((v) & 0x1) << 15)
#define BFM_I2C_CTRL1_BUS_FREE_IRQ_EN(v) BM_I2C_CTRL1_BUS_FREE_IRQ_EN
#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(e) BF_I2C_CTRL1_BUS_FREE_IRQ_EN(BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##e)
#define BFM_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v) BM_I2C_CTRL1_BUS_FREE_IRQ_EN
#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 14
#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x4000
#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0
#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1
#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v) (((v) & 0x1) << 14)
#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v) BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN
#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(e) BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##e)
#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v) BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN
#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 13
#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x2000
#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0
#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1
#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v) (((v) & 0x1) << 13)
#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v) BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN
#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(e) BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##e)
#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v) BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN
#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 12
#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x1000
#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0
#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1
#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v) (((v) & 0x1) << 12)
#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v) BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN
#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(e) BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##e)
#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v) BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN
#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN 11
#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x800
#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0
#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1
#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v) (((v) & 0x1) << 11)
#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_EN(v) BM_I2C_CTRL1_EARLY_TERM_IRQ_EN
#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(e) BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##e)
#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v) BM_I2C_CTRL1_EARLY_TERM_IRQ_EN
#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN 10
#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x400
#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0
#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1
#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v) (((v) & 0x1) << 10)
#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v) BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN
#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(e) BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##e)
#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v) BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN
#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN 9
#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x200
#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0
#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1
#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v) (((v) & 0x1) << 9)
#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v) BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN
#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(e) BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##e)
#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v) BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN
#define BP_I2C_CTRL1_SLAVE_IRQ_EN 8
#define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x100
#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0
#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1
#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v) (((v) & 0x1) << 8)
#define BFM_I2C_CTRL1_SLAVE_IRQ_EN(v) BM_I2C_CTRL1_SLAVE_IRQ_EN
#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(e) BF_I2C_CTRL1_SLAVE_IRQ_EN(BV_I2C_CTRL1_SLAVE_IRQ_EN__##e)
#define BFM_I2C_CTRL1_SLAVE_IRQ_EN_V(v) BM_I2C_CTRL1_SLAVE_IRQ_EN
#define BP_I2C_CTRL1_BUS_FREE_IRQ 7
#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x80
#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0
#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1
#define BF_I2C_CTRL1_BUS_FREE_IRQ(v) (((v) & 0x1) << 7)
#define BFM_I2C_CTRL1_BUS_FREE_IRQ(v) BM_I2C_CTRL1_BUS_FREE_IRQ
#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(e) BF_I2C_CTRL1_BUS_FREE_IRQ(BV_I2C_CTRL1_BUS_FREE_IRQ__##e)
#define BFM_I2C_CTRL1_BUS_FREE_IRQ_V(v) BM_I2C_CTRL1_BUS_FREE_IRQ
#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 6
#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0
#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1
#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v) (((v) & 0x1) << 6)
#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v) BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(e) BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##e)
#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v) BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ 5
#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0
#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1
#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v) (((v) & 0x1) << 5)
#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v) BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ
#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(e) BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##e)
#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v) BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ
#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 4
#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0
#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1
#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v) (((v) & 0x1) << 4)
#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v) BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ
#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(e) BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##e)
#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v) BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ
#define BP_I2C_CTRL1_EARLY_TERM_IRQ 3
#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x8
#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0
#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1
#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v) (((v) & 0x1) << 3)
#define BFM_I2C_CTRL1_EARLY_TERM_IRQ(v) BM_I2C_CTRL1_EARLY_TERM_IRQ
#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(e) BF_I2C_CTRL1_EARLY_TERM_IRQ(BV_I2C_CTRL1_EARLY_TERM_IRQ__##e)
#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_V(v) BM_I2C_CTRL1_EARLY_TERM_IRQ
#define BP_I2C_CTRL1_MASTER_LOSS_IRQ 2
#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x4
#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0
#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1
#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v) (((v) & 0x1) << 2)
#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ(v) BM_I2C_CTRL1_MASTER_LOSS_IRQ
#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(e) BF_I2C_CTRL1_MASTER_LOSS_IRQ(BV_I2C_CTRL1_MASTER_LOSS_IRQ__##e)
#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_V(v) BM_I2C_CTRL1_MASTER_LOSS_IRQ
#define BP_I2C_CTRL1_SLAVE_STOP_IRQ 1
#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x2
#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0
#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1
#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v) (((v) & 0x1) << 1)
#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ(v) BM_I2C_CTRL1_SLAVE_STOP_IRQ
#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(e) BF_I2C_CTRL1_SLAVE_STOP_IRQ(BV_I2C_CTRL1_SLAVE_STOP_IRQ__##e)
#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_V(v) BM_I2C_CTRL1_SLAVE_STOP_IRQ
#define BP_I2C_CTRL1_SLAVE_IRQ 0
#define BM_I2C_CTRL1_SLAVE_IRQ 0x1
#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0
#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1
#define BF_I2C_CTRL1_SLAVE_IRQ(v) (((v) & 0x1) << 0)
#define BFM_I2C_CTRL1_SLAVE_IRQ(v) BM_I2C_CTRL1_SLAVE_IRQ
#define BF_I2C_CTRL1_SLAVE_IRQ_V(e) BF_I2C_CTRL1_SLAVE_IRQ(BV_I2C_CTRL1_SLAVE_IRQ__##e)
#define BFM_I2C_CTRL1_SLAVE_IRQ_V(v) BM_I2C_CTRL1_SLAVE_IRQ
#define HW_I2C_STAT HW(I2C_STAT)
#define HWA_I2C_STAT (0x80058000 + 0x50)
#define HWT_I2C_STAT HWIO_32_RW
#define HWN_I2C_STAT I2C_STAT
#define HWI_I2C_STAT
#define BP_I2C_STAT_MASTER_PRESENT 31
#define BM_I2C_STAT_MASTER_PRESENT 0x80000000
#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0
#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1
#define BF_I2C_STAT_MASTER_PRESENT(v) (((v) & 0x1) << 31)
#define BFM_I2C_STAT_MASTER_PRESENT(v) BM_I2C_STAT_MASTER_PRESENT
#define BF_I2C_STAT_MASTER_PRESENT_V(e) BF_I2C_STAT_MASTER_PRESENT(BV_I2C_STAT_MASTER_PRESENT__##e)
#define BFM_I2C_STAT_MASTER_PRESENT_V(v) BM_I2C_STAT_MASTER_PRESENT
#define BP_I2C_STAT_SLAVE_PRESENT 30
#define BM_I2C_STAT_SLAVE_PRESENT 0x40000000
#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0
#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1
#define BF_I2C_STAT_SLAVE_PRESENT(v) (((v) & 0x1) << 30)
#define BFM_I2C_STAT_SLAVE_PRESENT(v) BM_I2C_STAT_SLAVE_PRESENT
#define BF_I2C_STAT_SLAVE_PRESENT_V(e) BF_I2C_STAT_SLAVE_PRESENT(BV_I2C_STAT_SLAVE_PRESENT__##e)
#define BFM_I2C_STAT_SLAVE_PRESENT_V(v) BM_I2C_STAT_SLAVE_PRESENT
#define BP_I2C_STAT_ANY_ENABLED_IRQ 29
#define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000
#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0
#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1
#define BF_I2C_STAT_ANY_ENABLED_IRQ(v) (((v) & 0x1) << 29)
#define BFM_I2C_STAT_ANY_ENABLED_IRQ(v) BM_I2C_STAT_ANY_ENABLED_IRQ
#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(e) BF_I2C_STAT_ANY_ENABLED_IRQ(BV_I2C_STAT_ANY_ENABLED_IRQ__##e)
#define BFM_I2C_STAT_ANY_ENABLED_IRQ_V(v) BM_I2C_STAT_ANY_ENABLED_IRQ
#define BP_I2C_STAT_RCVD_SLAVE_ADDR 16
#define BM_I2C_STAT_RCVD_SLAVE_ADDR 0xff0000
#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) (((v) & 0xff) << 16)
#define BFM_I2C_STAT_RCVD_SLAVE_ADDR(v) BM_I2C_STAT_RCVD_SLAVE_ADDR
#define BF_I2C_STAT_RCVD_SLAVE_ADDR_V(e) BF_I2C_STAT_RCVD_SLAVE_ADDR(BV_I2C_STAT_RCVD_SLAVE_ADDR__##e)
#define BFM_I2C_STAT_RCVD_SLAVE_ADDR_V(v) BM_I2C_STAT_RCVD_SLAVE_ADDR
#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO 15
#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x8000
#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0
#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1
#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v) (((v) & 0x1) << 15)
#define BFM_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v) BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO
#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(e) BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##e)
#define BFM_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v) BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO
#define BP_I2C_STAT_SLAVE_FOUND 14
#define BM_I2C_STAT_SLAVE_FOUND 0x4000
#define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0
#define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1
#define BF_I2C_STAT_SLAVE_FOUND(v) (((v) & 0x1) << 14)
#define BFM_I2C_STAT_SLAVE_FOUND(v) BM_I2C_STAT_SLAVE_FOUND
#define BF_I2C_STAT_SLAVE_FOUND_V(e) BF_I2C_STAT_SLAVE_FOUND(BV_I2C_STAT_SLAVE_FOUND__##e)
#define BFM_I2C_STAT_SLAVE_FOUND_V(v) BM_I2C_STAT_SLAVE_FOUND
#define BP_I2C_STAT_SLAVE_SEARCHING 13
#define BM_I2C_STAT_SLAVE_SEARCHING 0x2000
#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0
#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1
#define BF_I2C_STAT_SLAVE_SEARCHING(v) (((v) & 0x1) << 13)
#define BFM_I2C_STAT_SLAVE_SEARCHING(v) BM_I2C_STAT_SLAVE_SEARCHING
#define BF_I2C_STAT_SLAVE_SEARCHING_V(e) BF_I2C_STAT_SLAVE_SEARCHING(BV_I2C_STAT_SLAVE_SEARCHING__##e)
#define BFM_I2C_STAT_SLAVE_SEARCHING_V(v) BM_I2C_STAT_SLAVE_SEARCHING
#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT 12
#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x1000
#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0
#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1
#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v) (((v) & 0x1) << 12)
#define BFM_I2C_STAT_DATA_ENGINE_DMA_WAIT(v) BM_I2C_STAT_DATA_ENGINE_DMA_WAIT
#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(e) BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##e)
#define BFM_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v) BM_I2C_STAT_DATA_ENGINE_DMA_WAIT
#define BP_I2C_STAT_BUS_BUSY 11
#define BM_I2C_STAT_BUS_BUSY 0x800
#define BV_I2C_STAT_BUS_BUSY__IDLE 0x0
#define BV_I2C_STAT_BUS_BUSY__BUSY 0x1
#define BF_I2C_STAT_BUS_BUSY(v) (((v) & 0x1) << 11)
#define BFM_I2C_STAT_BUS_BUSY(v) BM_I2C_STAT_BUS_BUSY
#define BF_I2C_STAT_BUS_BUSY_V(e) BF_I2C_STAT_BUS_BUSY(BV_I2C_STAT_BUS_BUSY__##e)
#define BFM_I2C_STAT_BUS_BUSY_V(v) BM_I2C_STAT_BUS_BUSY
#define BP_I2C_STAT_CLK_GEN_BUSY 10
#define BM_I2C_STAT_CLK_GEN_BUSY 0x400
#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0
#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1
#define BF_I2C_STAT_CLK_GEN_BUSY(v) (((v) & 0x1) << 10)
#define BFM_I2C_STAT_CLK_GEN_BUSY(v) BM_I2C_STAT_CLK_GEN_BUSY
#define BF_I2C_STAT_CLK_GEN_BUSY_V(e) BF_I2C_STAT_CLK_GEN_BUSY(BV_I2C_STAT_CLK_GEN_BUSY__##e)
#define BFM_I2C_STAT_CLK_GEN_BUSY_V(v) BM_I2C_STAT_CLK_GEN_BUSY
#define BP_I2C_STAT_DATA_ENGINE_BUSY 9
#define BM_I2C_STAT_DATA_ENGINE_BUSY 0x200
#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0
#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1
#define BF_I2C_STAT_DATA_ENGINE_BUSY(v) (((v) & 0x1) << 9)
#define BFM_I2C_STAT_DATA_ENGINE_BUSY(v) BM_I2C_STAT_DATA_ENGINE_BUSY
#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(e) BF_I2C_STAT_DATA_ENGINE_BUSY(BV_I2C_STAT_DATA_ENGINE_BUSY__##e)
#define BFM_I2C_STAT_DATA_ENGINE_BUSY_V(v) BM_I2C_STAT_DATA_ENGINE_BUSY
#define BP_I2C_STAT_SLAVE_BUSY 8
#define BM_I2C_STAT_SLAVE_BUSY 0x100
#define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0
#define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1
#define BF_I2C_STAT_SLAVE_BUSY(v) (((v) & 0x1) << 8)
#define BFM_I2C_STAT_SLAVE_BUSY(v) BM_I2C_STAT_SLAVE_BUSY
#define BF_I2C_STAT_SLAVE_BUSY_V(e) BF_I2C_STAT_SLAVE_BUSY(BV_I2C_STAT_SLAVE_BUSY__##e)
#define BFM_I2C_STAT_SLAVE_BUSY_V(v) BM_I2C_STAT_SLAVE_BUSY
#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY 7
#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x80
#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1
#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v) (((v) & 0x1) << 7)
#define BFM_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v) BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY
#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(e) BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##e)
#define BFM_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v) BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY
#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 6
#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x40
#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1
#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v) (((v) & 0x1) << 6)
#define BFM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v) BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY
#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(e) BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##e)
#define BFM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v) BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY
#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 5
#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x20
#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1
#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v) (((v) & 0x1) << 5)
#define BFM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v) BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY
#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(e) BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##e)
#define BFM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v) BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY
#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 4
#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x10
#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1
#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v) (((v) & 0x1) << 4)
#define BFM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v) BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY
#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(e) BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##e)
#define BFM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v) BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY
#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 3
#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x8
#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1
#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v) (((v) & 0x1) << 3)
#define BFM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v) BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY
#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(e) BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##e)
#define BFM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v) BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY
#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 2
#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x4
#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1
#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v) (((v) & 0x1) << 2)
#define BFM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v) BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY
#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(e) BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##e)
#define BFM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v) BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY
#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 1
#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x2
#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1
#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v) (((v) & 0x1) << 1)
#define BFM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v) BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY
#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(e) BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##e)
#define BFM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v) BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY
#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY 0
#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x1
#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1
#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v) (((v) & 0x1) << 0)
#define BFM_I2C_STAT_SLAVE_IRQ_SUMMARY(v) BM_I2C_STAT_SLAVE_IRQ_SUMMARY
#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(e) BF_I2C_STAT_SLAVE_IRQ_SUMMARY(BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##e)
#define BFM_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v) BM_I2C_STAT_SLAVE_IRQ_SUMMARY
#define HW_I2C_DATA HW(I2C_DATA)
#define HWA_I2C_DATA (0x80058000 + 0x60)
#define HWT_I2C_DATA HWIO_32_RW
#define HWN_I2C_DATA I2C_DATA
#define HWI_I2C_DATA
#define BP_I2C_DATA_DATA 0
#define BM_I2C_DATA_DATA 0xffffffff
#define BF_I2C_DATA_DATA(v) (((v) & 0xffffffff) << 0)
#define BFM_I2C_DATA_DATA(v) BM_I2C_DATA_DATA
#define BF_I2C_DATA_DATA_V(e) BF_I2C_DATA_DATA(BV_I2C_DATA_DATA__##e)
#define BFM_I2C_DATA_DATA_V(v) BM_I2C_DATA_DATA
#define HW_I2C_DEBUG0 HW(I2C_DEBUG0)
#define HWA_I2C_DEBUG0 (0x80058000 + 0x70)
#define HWT_I2C_DEBUG0 HWIO_32_RW
#define HWN_I2C_DEBUG0 I2C_DEBUG0
#define HWI_I2C_DEBUG0
#define HW_I2C_DEBUG0_SET HW(I2C_DEBUG0_SET)
#define HWA_I2C_DEBUG0_SET (HWA_I2C_DEBUG0 + 0x4)
#define HWT_I2C_DEBUG0_SET HWIO_32_WO
#define HWN_I2C_DEBUG0_SET I2C_DEBUG0
#define HWI_I2C_DEBUG0_SET
#define HW_I2C_DEBUG0_CLR HW(I2C_DEBUG0_CLR)
#define HWA_I2C_DEBUG0_CLR (HWA_I2C_DEBUG0 + 0x8)
#define HWT_I2C_DEBUG0_CLR HWIO_32_WO
#define HWN_I2C_DEBUG0_CLR I2C_DEBUG0
#define HWI_I2C_DEBUG0_CLR
#define HW_I2C_DEBUG0_TOG HW(I2C_DEBUG0_TOG)
#define HWA_I2C_DEBUG0_TOG (HWA_I2C_DEBUG0 + 0xc)
#define HWT_I2C_DEBUG0_TOG HWIO_32_WO
#define HWN_I2C_DEBUG0_TOG I2C_DEBUG0
#define HWI_I2C_DEBUG0_TOG
#define BP_I2C_DEBUG0_DMAREQ 31
#define BM_I2C_DEBUG0_DMAREQ 0x80000000
#define BF_I2C_DEBUG0_DMAREQ(v) (((v) & 0x1) << 31)
#define BFM_I2C_DEBUG0_DMAREQ(v) BM_I2C_DEBUG0_DMAREQ
#define BF_I2C_DEBUG0_DMAREQ_V(e) BF_I2C_DEBUG0_DMAREQ(BV_I2C_DEBUG0_DMAREQ__##e)
#define BFM_I2C_DEBUG0_DMAREQ_V(v) BM_I2C_DEBUG0_DMAREQ
#define BP_I2C_DEBUG0_DMAENDCMD 30
#define BM_I2C_DEBUG0_DMAENDCMD 0x40000000
#define BF_I2C_DEBUG0_DMAENDCMD(v) (((v) & 0x1) << 30)
#define BFM_I2C_DEBUG0_DMAENDCMD(v) BM_I2C_DEBUG0_DMAENDCMD
#define BF_I2C_DEBUG0_DMAENDCMD_V(e) BF_I2C_DEBUG0_DMAENDCMD(BV_I2C_DEBUG0_DMAENDCMD__##e)
#define BFM_I2C_DEBUG0_DMAENDCMD_V(v) BM_I2C_DEBUG0_DMAENDCMD
#define BP_I2C_DEBUG0_DMAKICK 29
#define BM_I2C_DEBUG0_DMAKICK 0x20000000
#define BF_I2C_DEBUG0_DMAKICK(v) (((v) & 0x1) << 29)
#define BFM_I2C_DEBUG0_DMAKICK(v) BM_I2C_DEBUG0_DMAKICK
#define BF_I2C_DEBUG0_DMAKICK_V(e) BF_I2C_DEBUG0_DMAKICK(BV_I2C_DEBUG0_DMAKICK__##e)
#define BFM_I2C_DEBUG0_DMAKICK_V(v) BM_I2C_DEBUG0_DMAKICK
#define BP_I2C_DEBUG0_TBD 26
#define BM_I2C_DEBUG0_TBD 0x1c000000
#define BF_I2C_DEBUG0_TBD(v) (((v) & 0x7) << 26)
#define BFM_I2C_DEBUG0_TBD(v) BM_I2C_DEBUG0_TBD
#define BF_I2C_DEBUG0_TBD_V(e) BF_I2C_DEBUG0_TBD(BV_I2C_DEBUG0_TBD__##e)
#define BFM_I2C_DEBUG0_TBD_V(v) BM_I2C_DEBUG0_TBD
#define BP_I2C_DEBUG0_DMA_STATE 16
#define BM_I2C_DEBUG0_DMA_STATE 0x3ff0000
#define BF_I2C_DEBUG0_DMA_STATE(v) (((v) & 0x3ff) << 16)
#define BFM_I2C_DEBUG0_DMA_STATE(v) BM_I2C_DEBUG0_DMA_STATE
#define BF_I2C_DEBUG0_DMA_STATE_V(e) BF_I2C_DEBUG0_DMA_STATE(BV_I2C_DEBUG0_DMA_STATE__##e)
#define BFM_I2C_DEBUG0_DMA_STATE_V(v) BM_I2C_DEBUG0_DMA_STATE
#define BP_I2C_DEBUG0_START_TOGGLE 15
#define BM_I2C_DEBUG0_START_TOGGLE 0x8000
#define BF_I2C_DEBUG0_START_TOGGLE(v) (((v) & 0x1) << 15)
#define BFM_I2C_DEBUG0_START_TOGGLE(v) BM_I2C_DEBUG0_START_TOGGLE
#define BF_I2C_DEBUG0_START_TOGGLE_V(e) BF_I2C_DEBUG0_START_TOGGLE(BV_I2C_DEBUG0_START_TOGGLE__##e)
#define BFM_I2C_DEBUG0_START_TOGGLE_V(v) BM_I2C_DEBUG0_START_TOGGLE
#define BP_I2C_DEBUG0_STOP_TOGGLE 14
#define BM_I2C_DEBUG0_STOP_TOGGLE 0x4000
#define BF_I2C_DEBUG0_STOP_TOGGLE(v) (((v) & 0x1) << 14)
#define BFM_I2C_DEBUG0_STOP_TOGGLE(v) BM_I2C_DEBUG0_STOP_TOGGLE
#define BF_I2C_DEBUG0_STOP_TOGGLE_V(e) BF_I2C_DEBUG0_STOP_TOGGLE(BV_I2C_DEBUG0_STOP_TOGGLE__##e)
#define BFM_I2C_DEBUG0_STOP_TOGGLE_V(v) BM_I2C_DEBUG0_STOP_TOGGLE
#define BP_I2C_DEBUG0_GRAB_TOGGLE 13
#define BM_I2C_DEBUG0_GRAB_TOGGLE 0x2000
#define BF_I2C_DEBUG0_GRAB_TOGGLE(v) (((v) & 0x1) << 13)
#define BFM_I2C_DEBUG0_GRAB_TOGGLE(v) BM_I2C_DEBUG0_GRAB_TOGGLE
#define BF_I2C_DEBUG0_GRAB_TOGGLE_V(e) BF_I2C_DEBUG0_GRAB_TOGGLE(BV_I2C_DEBUG0_GRAB_TOGGLE__##e)
#define BFM_I2C_DEBUG0_GRAB_TOGGLE_V(v) BM_I2C_DEBUG0_GRAB_TOGGLE
#define BP_I2C_DEBUG0_CHANGE_TOGGLE 12
#define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x1000
#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v) (((v) & 0x1) << 12)
#define BFM_I2C_DEBUG0_CHANGE_TOGGLE(v) BM_I2C_DEBUG0_CHANGE_TOGGLE
#define BF_I2C_DEBUG0_CHANGE_TOGGLE_V(e) BF_I2C_DEBUG0_CHANGE_TOGGLE(BV_I2C_DEBUG0_CHANGE_TOGGLE__##e)
#define BFM_I2C_DEBUG0_CHANGE_TOGGLE_V(v) BM_I2C_DEBUG0_CHANGE_TOGGLE
#define BP_I2C_DEBUG0_TESTMODE 11
#define BM_I2C_DEBUG0_TESTMODE 0x800
#define BF_I2C_DEBUG0_TESTMODE(v) (((v) & 0x1) << 11)
#define BFM_I2C_DEBUG0_TESTMODE(v) BM_I2C_DEBUG0_TESTMODE
#define BF_I2C_DEBUG0_TESTMODE_V(e) BF_I2C_DEBUG0_TESTMODE(BV_I2C_DEBUG0_TESTMODE__##e)
#define BFM_I2C_DEBUG0_TESTMODE_V(v) BM_I2C_DEBUG0_TESTMODE
#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK 10
#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x400
#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) & 0x1) << 10)
#define BFM_I2C_DEBUG0_SLAVE_HOLD_CLK(v) BM_I2C_DEBUG0_SLAVE_HOLD_CLK
#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK_V(e) BF_I2C_DEBUG0_SLAVE_HOLD_CLK(BV_I2C_DEBUG0_SLAVE_HOLD_CLK__##e)
#define BFM_I2C_DEBUG0_SLAVE_HOLD_CLK_V(v) BM_I2C_DEBUG0_SLAVE_HOLD_CLK
#define BP_I2C_DEBUG0_SLAVE_STATE 0
#define BM_I2C_DEBUG0_SLAVE_STATE 0x3ff
#define BF_I2C_DEBUG0_SLAVE_STATE(v) (((v) & 0x3ff) << 0)
#define BFM_I2C_DEBUG0_SLAVE_STATE(v) BM_I2C_DEBUG0_SLAVE_STATE
#define BF_I2C_DEBUG0_SLAVE_STATE_V(e) BF_I2C_DEBUG0_SLAVE_STATE(BV_I2C_DEBUG0_SLAVE_STATE__##e)
#define BFM_I2C_DEBUG0_SLAVE_STATE_V(v) BM_I2C_DEBUG0_SLAVE_STATE
#define HW_I2C_DEBUG1 HW(I2C_DEBUG1)
#define HWA_I2C_DEBUG1 (0x80058000 + 0x80)
#define HWT_I2C_DEBUG1 HWIO_32_RW
#define HWN_I2C_DEBUG1 I2C_DEBUG1
#define HWI_I2C_DEBUG1
#define HW_I2C_DEBUG1_SET HW(I2C_DEBUG1_SET)
#define HWA_I2C_DEBUG1_SET (HWA_I2C_DEBUG1 + 0x4)
#define HWT_I2C_DEBUG1_SET HWIO_32_WO
#define HWN_I2C_DEBUG1_SET I2C_DEBUG1
#define HWI_I2C_DEBUG1_SET
#define HW_I2C_DEBUG1_CLR HW(I2C_DEBUG1_CLR)
#define HWA_I2C_DEBUG1_CLR (HWA_I2C_DEBUG1 + 0x8)
#define HWT_I2C_DEBUG1_CLR HWIO_32_WO
#define HWN_I2C_DEBUG1_CLR I2C_DEBUG1
#define HWI_I2C_DEBUG1_CLR
#define HW_I2C_DEBUG1_TOG HW(I2C_DEBUG1_TOG)
#define HWA_I2C_DEBUG1_TOG (HWA_I2C_DEBUG1 + 0xc)
#define HWT_I2C_DEBUG1_TOG HWIO_32_WO
#define HWN_I2C_DEBUG1_TOG I2C_DEBUG1
#define HWI_I2C_DEBUG1_TOG
#define BP_I2C_DEBUG1_I2C_CLK_IN 31
#define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000
#define BF_I2C_DEBUG1_I2C_CLK_IN(v) (((v) & 0x1) << 31)
#define BFM_I2C_DEBUG1_I2C_CLK_IN(v) BM_I2C_DEBUG1_I2C_CLK_IN
#define BF_I2C_DEBUG1_I2C_CLK_IN_V(e) BF_I2C_DEBUG1_I2C_CLK_IN(BV_I2C_DEBUG1_I2C_CLK_IN__##e)
#define BFM_I2C_DEBUG1_I2C_CLK_IN_V(v) BM_I2C_DEBUG1_I2C_CLK_IN
#define BP_I2C_DEBUG1_I2C_DATA_IN 30
#define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000
#define BF_I2C_DEBUG1_I2C_DATA_IN(v) (((v) & 0x1) << 30)
#define BFM_I2C_DEBUG1_I2C_DATA_IN(v) BM_I2C_DEBUG1_I2C_DATA_IN
#define BF_I2C_DEBUG1_I2C_DATA_IN_V(e) BF_I2C_DEBUG1_I2C_DATA_IN(BV_I2C_DEBUG1_I2C_DATA_IN__##e)
#define BFM_I2C_DEBUG1_I2C_DATA_IN_V(v) BM_I2C_DEBUG1_I2C_DATA_IN
#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24
#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0xf000000
#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) (((v) & 0xf) << 24)
#define BFM_I2C_DEBUG1_DMA_BYTE_ENABLES(v) BM_I2C_DEBUG1_DMA_BYTE_ENABLES
#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES_V(e) BF_I2C_DEBUG1_DMA_BYTE_ENABLES(BV_I2C_DEBUG1_DMA_BYTE_ENABLES__##e)
#define BFM_I2C_DEBUG1_DMA_BYTE_ENABLES_V(v) BM_I2C_DEBUG1_DMA_BYTE_ENABLES
#define BP_I2C_DEBUG1_CLK_GEN_STATE 16
#define BM_I2C_DEBUG1_CLK_GEN_STATE 0x7f0000
#define BF_I2C_DEBUG1_CLK_GEN_STATE(v) (((v) & 0x7f) << 16)
#define BFM_I2C_DEBUG1_CLK_GEN_STATE(v) BM_I2C_DEBUG1_CLK_GEN_STATE
#define BF_I2C_DEBUG1_CLK_GEN_STATE_V(e) BF_I2C_DEBUG1_CLK_GEN_STATE(BV_I2C_DEBUG1_CLK_GEN_STATE__##e)
#define BFM_I2C_DEBUG1_CLK_GEN_STATE_V(v) BM_I2C_DEBUG1_CLK_GEN_STATE
#define BP_I2C_DEBUG1_LST_MODE 9
#define BM_I2C_DEBUG1_LST_MODE 0x600
#define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0
#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1
#define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2
#define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3
#define BF_I2C_DEBUG1_LST_MODE(v) (((v) & 0x3) << 9)
#define BFM_I2C_DEBUG1_LST_MODE(v) BM_I2C_DEBUG1_LST_MODE
#define BF_I2C_DEBUG1_LST_MODE_V(e) BF_I2C_DEBUG1_LST_MODE(BV_I2C_DEBUG1_LST_MODE__##e)
#define BFM_I2C_DEBUG1_LST_MODE_V(v) BM_I2C_DEBUG1_LST_MODE
#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST 8
#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x100
#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v) (((v) & 0x1) << 8)
#define BFM_I2C_DEBUG1_LOCAL_SLAVE_TEST(v) BM_I2C_DEBUG1_LOCAL_SLAVE_TEST
#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST_V(e) BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(BV_I2C_DEBUG1_LOCAL_SLAVE_TEST__##e)
#define BFM_I2C_DEBUG1_LOCAL_SLAVE_TEST_V(v) BM_I2C_DEBUG1_LOCAL_SLAVE_TEST
#define BP_I2C_DEBUG1_FORCE_CLK_ON 5
#define BM_I2C_DEBUG1_FORCE_CLK_ON 0x20
#define BF_I2C_DEBUG1_FORCE_CLK_ON(v) (((v) & 0x1) << 5)
#define BFM_I2C_DEBUG1_FORCE_CLK_ON(v) BM_I2C_DEBUG1_FORCE_CLK_ON
#define BF_I2C_DEBUG1_FORCE_CLK_ON_V(e) BF_I2C_DEBUG1_FORCE_CLK_ON(BV_I2C_DEBUG1_FORCE_CLK_ON__##e)
#define BFM_I2C_DEBUG1_FORCE_CLK_ON_V(v) BM_I2C_DEBUG1_FORCE_CLK_ON
#define BP_I2C_DEBUG1_FORCE_CLK_IDLE 4
#define BM_I2C_DEBUG1_FORCE_CLK_IDLE 0x10
#define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v) (((v) & 0x1) << 4)
#define BFM_I2C_DEBUG1_FORCE_CLK_IDLE(v) BM_I2C_DEBUG1_FORCE_CLK_IDLE
#define BF_I2C_DEBUG1_FORCE_CLK_IDLE_V(e) BF_I2C_DEBUG1_FORCE_CLK_IDLE(BV_I2C_DEBUG1_FORCE_CLK_IDLE__##e)
#define BFM_I2C_DEBUG1_FORCE_CLK_IDLE_V(v) BM_I2C_DEBUG1_FORCE_CLK_IDLE
#define BP_I2C_DEBUG1_FORCE_ARB_LOSS 3
#define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x8
#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v) (((v) & 0x1) << 3)
#define BFM_I2C_DEBUG1_FORCE_ARB_LOSS(v) BM_I2C_DEBUG1_FORCE_ARB_LOSS
#define BF_I2C_DEBUG1_FORCE_ARB_LOSS_V(e) BF_I2C_DEBUG1_FORCE_ARB_LOSS(BV_I2C_DEBUG1_FORCE_ARB_LOSS__##e)
#define BFM_I2C_DEBUG1_FORCE_ARB_LOSS_V(v) BM_I2C_DEBUG1_FORCE_ARB_LOSS
#define BP_I2C_DEBUG1_FORCE_RCV_ACK 2
#define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x4
#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v) (((v) & 0x1) << 2)
#define BFM_I2C_DEBUG1_FORCE_RCV_ACK(v) BM_I2C_DEBUG1_FORCE_RCV_ACK
#define BF_I2C_DEBUG1_FORCE_RCV_ACK_V(e) BF_I2C_DEBUG1_FORCE_RCV_ACK(BV_I2C_DEBUG1_FORCE_RCV_ACK__##e)
#define BFM_I2C_DEBUG1_FORCE_RCV_ACK_V(v) BM_I2C_DEBUG1_FORCE_RCV_ACK
#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE 1
#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x2
#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v) (((v) & 0x1) << 1)
#define BFM_I2C_DEBUG1_FORCE_I2C_DATA_OE(v) BM_I2C_DEBUG1_FORCE_I2C_DATA_OE
#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE_V(e) BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(BV_I2C_DEBUG1_FORCE_I2C_DATA_OE__##e)
#define BFM_I2C_DEBUG1_FORCE_I2C_DATA_OE_V(v) BM_I2C_DEBUG1_FORCE_I2C_DATA_OE
#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE 0
#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x1
#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v) (((v) & 0x1) << 0)
#define BFM_I2C_DEBUG1_FORCE_I2C_CLK_OE(v) BM_I2C_DEBUG1_FORCE_I2C_CLK_OE
#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE_V(e) BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(BV_I2C_DEBUG1_FORCE_I2C_CLK_OE__##e)
#define BFM_I2C_DEBUG1_FORCE_I2C_CLK_OE_V(v) BM_I2C_DEBUG1_FORCE_I2C_CLK_OE
#endif /* __HEADERGEN_STMP3600_I2C_H__*/
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