Nyaaori/rockbox
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
rockbox/firmware/target/arm/imx233/regs/stmp3600/clkctrl.h
Amaury Pouly eac1ca22bd imx233: generate register headers using headergen_v2 and update code for it 
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.

The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
  BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
  BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
  its equivalent for BF_WR(reg_SET, ...)

I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".

Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml

Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-28 16:49:22 +02:00

546 lines
36 KiB
C
Raw Blame History

/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stmp3600 version: 2.4.0
* stmp3600 authors: Amaury Pouly
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_STMP3600_CLKCTRL_H__
#define __HEADERGEN_STMP3600_CLKCTRL_H__
#define HW_CLKCTRL_PLLCTRL0 HW(CLKCTRL_PLLCTRL0)
#define HWA_CLKCTRL_PLLCTRL0 (0x80040000 + 0x0)
#define HWT_CLKCTRL_PLLCTRL0 HWIO_32_RW
#define HWN_CLKCTRL_PLLCTRL0 CLKCTRL_PLLCTRL0
#define HWI_CLKCTRL_PLLCTRL0
#define HW_CLKCTRL_PLLCTRL0_SET HW(CLKCTRL_PLLCTRL0_SET)
#define HWA_CLKCTRL_PLLCTRL0_SET (HWA_CLKCTRL_PLLCTRL0 + 0x4)
#define HWT_CLKCTRL_PLLCTRL0_SET HWIO_32_WO
#define HWN_CLKCTRL_PLLCTRL0_SET CLKCTRL_PLLCTRL0
#define HWI_CLKCTRL_PLLCTRL0_SET
#define HW_CLKCTRL_PLLCTRL0_CLR HW(CLKCTRL_PLLCTRL0_CLR)
#define HWA_CLKCTRL_PLLCTRL0_CLR (HWA_CLKCTRL_PLLCTRL0 + 0x8)
#define HWT_CLKCTRL_PLLCTRL0_CLR HWIO_32_WO
#define HWN_CLKCTRL_PLLCTRL0_CLR CLKCTRL_PLLCTRL0
#define HWI_CLKCTRL_PLLCTRL0_CLR
#define HW_CLKCTRL_PLLCTRL0_TOG HW(CLKCTRL_PLLCTRL0_TOG)
#define HWA_CLKCTRL_PLLCTRL0_TOG (HWA_CLKCTRL_PLLCTRL0 + 0xc)
#define HWT_CLKCTRL_PLLCTRL0_TOG HWIO_32_WO
#define HWN_CLKCTRL_PLLCTRL0_TOG CLKCTRL_PLLCTRL0
#define HWI_CLKCTRL_PLLCTRL0_TOG
#define BP_CLKCTRL_PLLCTRL0_PLLVCOKSTART 30
#define BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART 0x40000000
#define BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_PLLCTRL0_PLLVCOKSTART(v) BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART
#define BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART_V(e) BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART(BV_CLKCTRL_PLLCTRL0_PLLVCOKSTART__##e)
#define BFM_CLKCTRL_PLLCTRL0_PLLVCOKSTART_V(v) BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART
#define BP_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR 29
#define BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR 0x20000000
#define BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(v) BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR
#define BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR_V(e) BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(BV_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR__##e)
#define BFM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR_V(v) BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR
#define BP_CLKCTRL_PLLCTRL0_PLLCPDBLIP 28
#define BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP 0x10000000
#define BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP(v) (((v) & 0x1) << 28)
#define BFM_CLKCTRL_PLLCTRL0_PLLCPDBLIP(v) BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP
#define BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP_V(e) BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP(BV_CLKCTRL_PLLCTRL0_PLLCPDBLIP__##e)
#define BFM_CLKCTRL_PLLCTRL0_PLLCPDBLIP_V(v) BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP
#define BP_CLKCTRL_PLLCTRL0_PLLCPNSEL 24
#define BM_CLKCTRL_PLLCTRL0_PLLCPNSEL 0x7000000
#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__DEFAULT 0x0
#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_15 0x2
#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_075 0x3
#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_05 0x4
#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_04 0x7
#define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL(v) (((v) & 0x7) << 24)
#define BFM_CLKCTRL_PLLCTRL0_PLLCPNSEL(v) BM_CLKCTRL_PLLCTRL0_PLLCPNSEL
#define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL_V(e) BF_CLKCTRL_PLLCTRL0_PLLCPNSEL(BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__##e)
#define BFM_CLKCTRL_PLLCTRL0_PLLCPNSEL_V(v) BM_CLKCTRL_PLLCTRL0_PLLCPNSEL
#define BP_CLKCTRL_PLLCTRL0_PLLV2ISEL 20
#define BM_CLKCTRL_PLLCTRL0_PLLV2ISEL 0x300000
#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__NORMAL 0x0
#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWER 0x1
#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWEST 0x2
#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__HIGHEST 0x3
#define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL(v) (((v) & 0x3) << 20)
#define BFM_CLKCTRL_PLLCTRL0_PLLV2ISEL(v) BM_CLKCTRL_PLLCTRL0_PLLV2ISEL
#define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL_V(e) BF_CLKCTRL_PLLCTRL0_PLLV2ISEL(BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__##e)
#define BFM_CLKCTRL_PLLCTRL0_PLLV2ISEL_V(v) BM_CLKCTRL_PLLCTRL0_PLLV2ISEL
#define BP_CLKCTRL_PLLCTRL0_FORCE_FREQ 19
#define BM_CLKCTRL_PLLCTRL0_FORCE_FREQ 0x80000
#define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__FORCE_SAME_FREQ 0x1
#define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__HONOR_SAME_FREQ_RULE 0x0
#define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ(v) (((v) & 0x1) << 19)
#define BFM_CLKCTRL_PLLCTRL0_FORCE_FREQ(v) BM_CLKCTRL_PLLCTRL0_FORCE_FREQ
#define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ_V(e) BF_CLKCTRL_PLLCTRL0_FORCE_FREQ(BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__##e)
#define BFM_CLKCTRL_PLLCTRL0_FORCE_FREQ_V(v) BM_CLKCTRL_PLLCTRL0_FORCE_FREQ
#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000
#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) & 0x1) << 18)
#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(e) BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(BV_CLKCTRL_PLLCTRL0_EN_USB_CLKS__##e)
#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(v) BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
#define BP_CLKCTRL_PLLCTRL0_BYPASS 17
#define BM_CLKCTRL_PLLCTRL0_BYPASS 0x20000
#define BF_CLKCTRL_PLLCTRL0_BYPASS(v) (((v) & 0x1) << 17)
#define BFM_CLKCTRL_PLLCTRL0_BYPASS(v) BM_CLKCTRL_PLLCTRL0_BYPASS
#define BF_CLKCTRL_PLLCTRL0_BYPASS_V(e) BF_CLKCTRL_PLLCTRL0_BYPASS(BV_CLKCTRL_PLLCTRL0_BYPASS__##e)
#define BFM_CLKCTRL_PLLCTRL0_BYPASS_V(v) BM_CLKCTRL_PLLCTRL0_BYPASS
#define BP_CLKCTRL_PLLCTRL0_POWER 16
#define BM_CLKCTRL_PLLCTRL0_POWER 0x10000
#define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) & 0x1) << 16)
#define BFM_CLKCTRL_PLLCTRL0_POWER(v) BM_CLKCTRL_PLLCTRL0_POWER
#define BF_CLKCTRL_PLLCTRL0_POWER_V(e) BF_CLKCTRL_PLLCTRL0_POWER(BV_CLKCTRL_PLLCTRL0_POWER__##e)
#define BFM_CLKCTRL_PLLCTRL0_POWER_V(v) BM_CLKCTRL_PLLCTRL0_POWER
#define BP_CLKCTRL_PLLCTRL0_FREQ 0
#define BM_CLKCTRL_PLLCTRL0_FREQ 0x1ff
#define BF_CLKCTRL_PLLCTRL0_FREQ(v) (((v) & 0x1ff) << 0)
#define BFM_CLKCTRL_PLLCTRL0_FREQ(v) BM_CLKCTRL_PLLCTRL0_FREQ
#define BF_CLKCTRL_PLLCTRL0_FREQ_V(e) BF_CLKCTRL_PLLCTRL0_FREQ(BV_CLKCTRL_PLLCTRL0_FREQ__##e)
#define BFM_CLKCTRL_PLLCTRL0_FREQ_V(v) BM_CLKCTRL_PLLCTRL0_FREQ
#define HW_CLKCTRL_PLLCTRL1 HW(CLKCTRL_PLLCTRL1)
#define HWA_CLKCTRL_PLLCTRL1 (0x80040000 + 0x10)
#define HWT_CLKCTRL_PLLCTRL1 HWIO_32_RW
#define HWN_CLKCTRL_PLLCTRL1 CLKCTRL_PLLCTRL1
#define HWI_CLKCTRL_PLLCTRL1
#define HW_CLKCTRL_PLLCTRL1_SET HW(CLKCTRL_PLLCTRL1_SET)
#define HWA_CLKCTRL_PLLCTRL1_SET (HWA_CLKCTRL_PLLCTRL1 + 0x4)
#define HWT_CLKCTRL_PLLCTRL1_SET HWIO_32_WO
#define HWN_CLKCTRL_PLLCTRL1_SET CLKCTRL_PLLCTRL1
#define HWI_CLKCTRL_PLLCTRL1_SET
#define HW_CLKCTRL_PLLCTRL1_CLR HW(CLKCTRL_PLLCTRL1_CLR)
#define HWA_CLKCTRL_PLLCTRL1_CLR (HWA_CLKCTRL_PLLCTRL1 + 0x8)
#define HWT_CLKCTRL_PLLCTRL1_CLR HWIO_32_WO
#define HWN_CLKCTRL_PLLCTRL1_CLR CLKCTRL_PLLCTRL1
#define HWI_CLKCTRL_PLLCTRL1_CLR
#define HW_CLKCTRL_PLLCTRL1_TOG HW(CLKCTRL_PLLCTRL1_TOG)
#define HWA_CLKCTRL_PLLCTRL1_TOG (HWA_CLKCTRL_PLLCTRL1 + 0xc)
#define HWT_CLKCTRL_PLLCTRL1_TOG HWIO_32_WO
#define HWN_CLKCTRL_PLLCTRL1_TOG CLKCTRL_PLLCTRL1
#define HWI_CLKCTRL_PLLCTRL1_TOG
#define BP_CLKCTRL_PLLCTRL1_LOCK 31
#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
#define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_PLLCTRL1_LOCK(v) BM_CLKCTRL_PLLCTRL1_LOCK
#define BF_CLKCTRL_PLLCTRL1_LOCK_V(e) BF_CLKCTRL_PLLCTRL1_LOCK(BV_CLKCTRL_PLLCTRL1_LOCK__##e)
#define BFM_CLKCTRL_PLLCTRL1_LOCK_V(v) BM_CLKCTRL_PLLCTRL1_LOCK
#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30
#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(e) BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(BV_CLKCTRL_PLLCTRL1_FORCE_LOCK__##e)
#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(v) BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff
#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) & 0xffff) << 0)
#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(e) BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(BV_CLKCTRL_PLLCTRL1_LOCK_COUNT__##e)
#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(v) BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
#define HW_CLKCTRL_CPU HW(CLKCTRL_CPU)
#define HWA_CLKCTRL_CPU (0x80040000 + 0x20)
#define HWT_CLKCTRL_CPU HWIO_32_RW
#define HWN_CLKCTRL_CPU CLKCTRL_CPU
#define HWI_CLKCTRL_CPU
#define BP_CLKCTRL_CPU_WAIT_PLL_LOCK 30
#define BM_CLKCTRL_CPU_WAIT_PLL_LOCK 0x40000000
#define BF_CLKCTRL_CPU_WAIT_PLL_LOCK(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_CPU_WAIT_PLL_LOCK(v) BM_CLKCTRL_CPU_WAIT_PLL_LOCK
#define BF_CLKCTRL_CPU_WAIT_PLL_LOCK_V(e) BF_CLKCTRL_CPU_WAIT_PLL_LOCK(BV_CLKCTRL_CPU_WAIT_PLL_LOCK__##e)
#define BFM_CLKCTRL_CPU_WAIT_PLL_LOCK_V(v) BM_CLKCTRL_CPU_WAIT_PLL_LOCK
#define BP_CLKCTRL_CPU_BUSY 29
#define BM_CLKCTRL_CPU_BUSY 0x20000000
#define BF_CLKCTRL_CPU_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_CPU_BUSY(v) BM_CLKCTRL_CPU_BUSY
#define BF_CLKCTRL_CPU_BUSY_V(e) BF_CLKCTRL_CPU_BUSY(BV_CLKCTRL_CPU_BUSY__##e)
#define BFM_CLKCTRL_CPU_BUSY_V(v) BM_CLKCTRL_CPU_BUSY
#define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12
#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000
#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) & 0x1) << 12)
#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT(v) BM_CLKCTRL_CPU_INTERRUPT_WAIT
#define BF_CLKCTRL_CPU_INTERRUPT_WAIT_V(e) BF_CLKCTRL_CPU_INTERRUPT_WAIT(BV_CLKCTRL_CPU_INTERRUPT_WAIT__##e)
#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT_V(v) BM_CLKCTRL_CPU_INTERRUPT_WAIT
#define BP_CLKCTRL_CPU_DIV 0
#define BM_CLKCTRL_CPU_DIV 0x3ff
#define BF_CLKCTRL_CPU_DIV(v) (((v) & 0x3ff) << 0)
#define BFM_CLKCTRL_CPU_DIV(v) BM_CLKCTRL_CPU_DIV
#define BF_CLKCTRL_CPU_DIV_V(e) BF_CLKCTRL_CPU_DIV(BV_CLKCTRL_CPU_DIV__##e)
#define BFM_CLKCTRL_CPU_DIV_V(v) BM_CLKCTRL_CPU_DIV
#define HW_CLKCTRL_HBUS HW(CLKCTRL_HBUS)
#define HWA_CLKCTRL_HBUS (0x80040000 + 0x30)
#define HWT_CLKCTRL_HBUS HWIO_32_RW
#define HWN_CLKCTRL_HBUS CLKCTRL_HBUS
#define HWI_CLKCTRL_HBUS
#define BP_CLKCTRL_HBUS_WAIT_PLL_LOCK 30
#define BM_CLKCTRL_HBUS_WAIT_PLL_LOCK 0x40000000
#define BF_CLKCTRL_HBUS_WAIT_PLL_LOCK(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_HBUS_WAIT_PLL_LOCK(v) BM_CLKCTRL_HBUS_WAIT_PLL_LOCK
#define BF_CLKCTRL_HBUS_WAIT_PLL_LOCK_V(e) BF_CLKCTRL_HBUS_WAIT_PLL_LOCK(BV_CLKCTRL_HBUS_WAIT_PLL_LOCK__##e)
#define BFM_CLKCTRL_HBUS_WAIT_PLL_LOCK_V(v) BM_CLKCTRL_HBUS_WAIT_PLL_LOCK
#define BP_CLKCTRL_HBUS_BUSY 29
#define BM_CLKCTRL_HBUS_BUSY 0x20000000
#define BF_CLKCTRL_HBUS_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_HBUS_BUSY(v) BM_CLKCTRL_HBUS_BUSY
#define BF_CLKCTRL_HBUS_BUSY_V(e) BF_CLKCTRL_HBUS_BUSY(BV_CLKCTRL_HBUS_BUSY__##e)
#define BFM_CLKCTRL_HBUS_BUSY_V(v) BM_CLKCTRL_HBUS_BUSY
#define BP_CLKCTRL_HBUS_EMI_BUSY_FAST 27
#define BM_CLKCTRL_HBUS_EMI_BUSY_FAST 0x8000000
#define BF_CLKCTRL_HBUS_EMI_BUSY_FAST(v) (((v) & 0x1) << 27)
#define BFM_CLKCTRL_HBUS_EMI_BUSY_FAST(v) BM_CLKCTRL_HBUS_EMI_BUSY_FAST
#define BF_CLKCTRL_HBUS_EMI_BUSY_FAST_V(e) BF_CLKCTRL_HBUS_EMI_BUSY_FAST(BV_CLKCTRL_HBUS_EMI_BUSY_FAST__##e)
#define BFM_CLKCTRL_HBUS_EMI_BUSY_FAST_V(v) BM_CLKCTRL_HBUS_EMI_BUSY_FAST
#define BP_CLKCTRL_HBUS_APBHDMA_BUSY_FAST 26
#define BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST 0x4000000
#define BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(v) (((v) & 0x1) << 26)
#define BFM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(v) BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST
#define BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST_V(e) BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(BV_CLKCTRL_HBUS_APBHDMA_BUSY_FAST__##e)
#define BFM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST_V(v) BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST
#define BP_CLKCTRL_HBUS_APBXDMA_BUSY_FAST 25
#define BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST 0x2000000
#define BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(v) (((v) & 0x1) << 25)
#define BFM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(v) BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST
#define BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST_V(e) BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(BV_CLKCTRL_HBUS_APBXDMA_BUSY_FAST__##e)
#define BFM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST_V(v) BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST
#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_FAST 24
#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST 0x1000000
#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(v) (((v) & 0x1) << 24)
#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(v) BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST
#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST_V(e) BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(BV_CLKCTRL_HBUS_TRAFFIC_JAM_FAST__##e)
#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST_V(v) BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST
#define BP_CLKCTRL_HBUS_TRAFFIC_FAST 23
#define BM_CLKCTRL_HBUS_TRAFFIC_FAST 0x800000
#define BF_CLKCTRL_HBUS_TRAFFIC_FAST(v) (((v) & 0x1) << 23)
#define BFM_CLKCTRL_HBUS_TRAFFIC_FAST(v) BM_CLKCTRL_HBUS_TRAFFIC_FAST
#define BF_CLKCTRL_HBUS_TRAFFIC_FAST_V(e) BF_CLKCTRL_HBUS_TRAFFIC_FAST(BV_CLKCTRL_HBUS_TRAFFIC_FAST__##e)
#define BFM_CLKCTRL_HBUS_TRAFFIC_FAST_V(v) BM_CLKCTRL_HBUS_TRAFFIC_FAST
#define BP_CLKCTRL_HBUS_CPU_DATA_FAST 22
#define BM_CLKCTRL_HBUS_CPU_DATA_FAST 0x400000
#define BF_CLKCTRL_HBUS_CPU_DATA_FAST(v) (((v) & 0x1) << 22)
#define BFM_CLKCTRL_HBUS_CPU_DATA_FAST(v) BM_CLKCTRL_HBUS_CPU_DATA_FAST
#define BF_CLKCTRL_HBUS_CPU_DATA_FAST_V(e) BF_CLKCTRL_HBUS_CPU_DATA_FAST(BV_CLKCTRL_HBUS_CPU_DATA_FAST__##e)
#define BFM_CLKCTRL_HBUS_CPU_DATA_FAST_V(v) BM_CLKCTRL_HBUS_CPU_DATA_FAST
#define BP_CLKCTRL_HBUS_CPU_INSTR_FAST 21
#define BM_CLKCTRL_HBUS_CPU_INSTR_FAST 0x200000
#define BF_CLKCTRL_HBUS_CPU_INSTR_FAST(v) (((v) & 0x1) << 21)
#define BFM_CLKCTRL_HBUS_CPU_INSTR_FAST(v) BM_CLKCTRL_HBUS_CPU_INSTR_FAST
#define BF_CLKCTRL_HBUS_CPU_INSTR_FAST_V(e) BF_CLKCTRL_HBUS_CPU_INSTR_FAST(BV_CLKCTRL_HBUS_CPU_INSTR_FAST__##e)
#define BFM_CLKCTRL_HBUS_CPU_INSTR_FAST_V(v) BM_CLKCTRL_HBUS_CPU_INSTR_FAST
#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20
#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000
#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) & 0x1) << 20)
#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(e) BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(BV_CLKCTRL_HBUS_AUTO_SLOW_MODE__##e)
#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(v) BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
#define BP_CLKCTRL_HBUS_SLOW_DIV 16
#define BM_CLKCTRL_HBUS_SLOW_DIV 0x30000
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
#define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) & 0x3) << 16)
#define BFM_CLKCTRL_HBUS_SLOW_DIV(v) BM_CLKCTRL_HBUS_SLOW_DIV
#define BF_CLKCTRL_HBUS_SLOW_DIV_V(e) BF_CLKCTRL_HBUS_SLOW_DIV(BV_CLKCTRL_HBUS_SLOW_DIV__##e)
#define BFM_CLKCTRL_HBUS_SLOW_DIV_V(v) BM_CLKCTRL_HBUS_SLOW_DIV
#define BP_CLKCTRL_HBUS_DIV 0
#define BM_CLKCTRL_HBUS_DIV 0x1f
#define BF_CLKCTRL_HBUS_DIV(v) (((v) & 0x1f) << 0)
#define BFM_CLKCTRL_HBUS_DIV(v) BM_CLKCTRL_HBUS_DIV
#define BF_CLKCTRL_HBUS_DIV_V(e) BF_CLKCTRL_HBUS_DIV(BV_CLKCTRL_HBUS_DIV__##e)
#define BFM_CLKCTRL_HBUS_DIV_V(v) BM_CLKCTRL_HBUS_DIV
#define HW_CLKCTRL_XBUS HW(CLKCTRL_XBUS)
#define HWA_CLKCTRL_XBUS (0x80040000 + 0x40)
#define HWT_CLKCTRL_XBUS HWIO_32_RW
#define HWN_CLKCTRL_XBUS CLKCTRL_XBUS
#define HWI_CLKCTRL_XBUS
#define BP_CLKCTRL_XBUS_BUSY 31
#define BM_CLKCTRL_XBUS_BUSY 0x80000000
#define BF_CLKCTRL_XBUS_BUSY(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_XBUS_BUSY(v) BM_CLKCTRL_XBUS_BUSY
#define BF_CLKCTRL_XBUS_BUSY_V(e) BF_CLKCTRL_XBUS_BUSY(BV_CLKCTRL_XBUS_BUSY__##e)
#define BFM_CLKCTRL_XBUS_BUSY_V(v) BM_CLKCTRL_XBUS_BUSY
#define BP_CLKCTRL_XBUS_DIV 0
#define BM_CLKCTRL_XBUS_DIV 0x3ff
#define BF_CLKCTRL_XBUS_DIV(v) (((v) & 0x3ff) << 0)
#define BFM_CLKCTRL_XBUS_DIV(v) BM_CLKCTRL_XBUS_DIV
#define BF_CLKCTRL_XBUS_DIV_V(e) BF_CLKCTRL_XBUS_DIV(BV_CLKCTRL_XBUS_DIV__##e)
#define BFM_CLKCTRL_XBUS_DIV_V(v) BM_CLKCTRL_XBUS_DIV
#define HW_CLKCTRL_XTAL HW(CLKCTRL_XTAL)
#define HWA_CLKCTRL_XTAL (0x80040000 + 0x50)
#define HWT_CLKCTRL_XTAL HWIO_32_RW
#define HWN_CLKCTRL_XTAL CLKCTRL_XTAL
#define HWI_CLKCTRL_XTAL
#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_XTAL_UART_CLK_GATE(v) BM_CLKCTRL_XTAL_UART_CLK_GATE
#define BF_CLKCTRL_XTAL_UART_CLK_GATE_V(e) BF_CLKCTRL_XTAL_UART_CLK_GATE(BV_CLKCTRL_XTAL_UART_CLK_GATE__##e)
#define BFM_CLKCTRL_XTAL_UART_CLK_GATE_V(v) BM_CLKCTRL_XTAL_UART_CLK_GATE
#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30
#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(e) BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(BV_CLKCTRL_XTAL_FILT_CLK24M_GATE__##e)
#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(v) BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(e) BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(BV_CLKCTRL_XTAL_PWM_CLK24M_GATE__##e)
#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(v) BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28
#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) & 0x1) << 28)
#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(e) BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(BV_CLKCTRL_XTAL_DRI_CLK24M_GATE__##e)
#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(v) BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27
#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000
#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) & 0x1) << 27)
#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(e) BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(BV_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE__##e)
#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(v) BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000
#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) & 0x1) << 26)
#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(e) BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(BV_CLKCTRL_XTAL_TIMROT_CLK32K_GATE__##e)
#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(v) BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
#define BP_CLKCTRL_XTAL_EXRAM_CLK16K_GATE 25
#define BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE 0x2000000
#define BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(v) (((v) & 0x1) << 25)
#define BFM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(v) BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE
#define BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE_V(e) BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(BV_CLKCTRL_XTAL_EXRAM_CLK16K_GATE__##e)
#define BFM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE_V(v) BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE
#define BP_CLKCTRL_XTAL_LRADC_CLK2K_GATE 24
#define BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE 0x1000000
#define BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE(v) (((v) & 0x1) << 24)
#define BFM_CLKCTRL_XTAL_LRADC_CLK2K_GATE(v) BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE
#define BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE_V(e) BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE(BV_CLKCTRL_XTAL_LRADC_CLK2K_GATE__##e)
#define BFM_CLKCTRL_XTAL_LRADC_CLK2K_GATE_V(v) BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE
#define HW_CLKCTRL_OCRAM HW(CLKCTRL_OCRAM)
#define HWA_CLKCTRL_OCRAM (0x80040000 + 0x60)
#define HWT_CLKCTRL_OCRAM HWIO_32_RW
#define HWN_CLKCTRL_OCRAM CLKCTRL_OCRAM
#define HWI_CLKCTRL_OCRAM
#define BP_CLKCTRL_OCRAM_CLKGATE 31
#define BM_CLKCTRL_OCRAM_CLKGATE 0x80000000
#define BF_CLKCTRL_OCRAM_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_OCRAM_CLKGATE(v) BM_CLKCTRL_OCRAM_CLKGATE
#define BF_CLKCTRL_OCRAM_CLKGATE_V(e) BF_CLKCTRL_OCRAM_CLKGATE(BV_CLKCTRL_OCRAM_CLKGATE__##e)
#define BFM_CLKCTRL_OCRAM_CLKGATE_V(v) BM_CLKCTRL_OCRAM_CLKGATE
#define BP_CLKCTRL_OCRAM_BUSY 30
#define BM_CLKCTRL_OCRAM_BUSY 0x40000000
#define BF_CLKCTRL_OCRAM_BUSY(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_OCRAM_BUSY(v) BM_CLKCTRL_OCRAM_BUSY
#define BF_CLKCTRL_OCRAM_BUSY_V(e) BF_CLKCTRL_OCRAM_BUSY(BV_CLKCTRL_OCRAM_BUSY__##e)
#define BFM_CLKCTRL_OCRAM_BUSY_V(v) BM_CLKCTRL_OCRAM_BUSY
#define BP_CLKCTRL_OCRAM_DIV 0
#define BM_CLKCTRL_OCRAM_DIV 0x3ff
#define BF_CLKCTRL_OCRAM_DIV(v) (((v) & 0x3ff) << 0)
#define BFM_CLKCTRL_OCRAM_DIV(v) BM_CLKCTRL_OCRAM_DIV
#define BF_CLKCTRL_OCRAM_DIV_V(e) BF_CLKCTRL_OCRAM_DIV(BV_CLKCTRL_OCRAM_DIV__##e)
#define BFM_CLKCTRL_OCRAM_DIV_V(v) BM_CLKCTRL_OCRAM_DIV
#define HW_CLKCTRL_UTMI HW(CLKCTRL_UTMI)
#define HWA_CLKCTRL_UTMI (0x80040000 + 0x70)
#define HWT_CLKCTRL_UTMI HWIO_32_RW
#define HWN_CLKCTRL_UTMI CLKCTRL_UTMI
#define HWI_CLKCTRL_UTMI
#define BP_CLKCTRL_UTMI_UTMI_CLK120M_GATE 31
#define BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE 0x80000000
#define BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_UTMI_UTMI_CLK120M_GATE(v) BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE
#define BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE_V(e) BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE(BV_CLKCTRL_UTMI_UTMI_CLK120M_GATE__##e)
#define BFM_CLKCTRL_UTMI_UTMI_CLK120M_GATE_V(v) BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE
#define BP_CLKCTRL_UTMI_UTMI_CLK30M_GATE 30
#define BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE 0x40000000
#define BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_UTMI_UTMI_CLK30M_GATE(v) BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE
#define BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE_V(e) BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE(BV_CLKCTRL_UTMI_UTMI_CLK30M_GATE__##e)
#define BFM_CLKCTRL_UTMI_UTMI_CLK30M_GATE_V(v) BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE
#define HW_CLKCTRL_SSP HW(CLKCTRL_SSP)
#define HWA_CLKCTRL_SSP (0x80040000 + 0x80)
#define HWT_CLKCTRL_SSP HWIO_32_RW
#define HWN_CLKCTRL_SSP CLKCTRL_SSP
#define HWI_CLKCTRL_SSP
#define BP_CLKCTRL_SSP_CLKGATE 31
#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
#define BF_CLKCTRL_SSP_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_SSP_CLKGATE(v) BM_CLKCTRL_SSP_CLKGATE
#define BF_CLKCTRL_SSP_CLKGATE_V(e) BF_CLKCTRL_SSP_CLKGATE(BV_CLKCTRL_SSP_CLKGATE__##e)
#define BFM_CLKCTRL_SSP_CLKGATE_V(v) BM_CLKCTRL_SSP_CLKGATE
#define BP_CLKCTRL_SSP_WAIT_PLL_LOCK 30
#define BM_CLKCTRL_SSP_WAIT_PLL_LOCK 0x40000000
#define BF_CLKCTRL_SSP_WAIT_PLL_LOCK(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_SSP_WAIT_PLL_LOCK(v) BM_CLKCTRL_SSP_WAIT_PLL_LOCK
#define BF_CLKCTRL_SSP_WAIT_PLL_LOCK_V(e) BF_CLKCTRL_SSP_WAIT_PLL_LOCK(BV_CLKCTRL_SSP_WAIT_PLL_LOCK__##e)
#define BFM_CLKCTRL_SSP_WAIT_PLL_LOCK_V(v) BM_CLKCTRL_SSP_WAIT_PLL_LOCK
#define BP_CLKCTRL_SSP_BUSY 29
#define BM_CLKCTRL_SSP_BUSY 0x20000000
#define BF_CLKCTRL_SSP_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_SSP_BUSY(v) BM_CLKCTRL_SSP_BUSY
#define BF_CLKCTRL_SSP_BUSY_V(e) BF_CLKCTRL_SSP_BUSY(BV_CLKCTRL_SSP_BUSY__##e)
#define BFM_CLKCTRL_SSP_BUSY_V(v) BM_CLKCTRL_SSP_BUSY
#define BP_CLKCTRL_SSP_DIV 0
#define BM_CLKCTRL_SSP_DIV 0x1ff
#define BF_CLKCTRL_SSP_DIV(v) (((v) & 0x1ff) << 0)
#define BFM_CLKCTRL_SSP_DIV(v) BM_CLKCTRL_SSP_DIV
#define BF_CLKCTRL_SSP_DIV_V(e) BF_CLKCTRL_SSP_DIV(BV_CLKCTRL_SSP_DIV__##e)
#define BFM_CLKCTRL_SSP_DIV_V(v) BM_CLKCTRL_SSP_DIV
#define HW_CLKCTRL_GPMI HW(CLKCTRL_GPMI)
#define HWA_CLKCTRL_GPMI (0x80040000 + 0x90)
#define HWT_CLKCTRL_GPMI HWIO_32_RW
#define HWN_CLKCTRL_GPMI CLKCTRL_GPMI
#define HWI_CLKCTRL_GPMI
#define BP_CLKCTRL_GPMI_CLKGATE 31
#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
#define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_GPMI_CLKGATE(v) BM_CLKCTRL_GPMI_CLKGATE
#define BF_CLKCTRL_GPMI_CLKGATE_V(e) BF_CLKCTRL_GPMI_CLKGATE(BV_CLKCTRL_GPMI_CLKGATE__##e)
#define BFM_CLKCTRL_GPMI_CLKGATE_V(v) BM_CLKCTRL_GPMI_CLKGATE
#define BP_CLKCTRL_GPMI_WAIT_PLL_LOCK 30
#define BM_CLKCTRL_GPMI_WAIT_PLL_LOCK 0x40000000
#define BF_CLKCTRL_GPMI_WAIT_PLL_LOCK(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_GPMI_WAIT_PLL_LOCK(v) BM_CLKCTRL_GPMI_WAIT_PLL_LOCK
#define BF_CLKCTRL_GPMI_WAIT_PLL_LOCK_V(e) BF_CLKCTRL_GPMI_WAIT_PLL_LOCK(BV_CLKCTRL_GPMI_WAIT_PLL_LOCK__##e)
#define BFM_CLKCTRL_GPMI_WAIT_PLL_LOCK_V(v) BM_CLKCTRL_GPMI_WAIT_PLL_LOCK
#define BP_CLKCTRL_GPMI_BUSY 29
#define BM_CLKCTRL_GPMI_BUSY 0x20000000
#define BF_CLKCTRL_GPMI_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_GPMI_BUSY(v) BM_CLKCTRL_GPMI_BUSY
#define BF_CLKCTRL_GPMI_BUSY_V(e) BF_CLKCTRL_GPMI_BUSY(BV_CLKCTRL_GPMI_BUSY__##e)
#define BFM_CLKCTRL_GPMI_BUSY_V(v) BM_CLKCTRL_GPMI_BUSY
#define BP_CLKCTRL_GPMI_DIV 0
#define BM_CLKCTRL_GPMI_DIV 0x3ff
#define BF_CLKCTRL_GPMI_DIV(v) (((v) & 0x3ff) << 0)
#define BFM_CLKCTRL_GPMI_DIV(v) BM_CLKCTRL_GPMI_DIV
#define BF_CLKCTRL_GPMI_DIV_V(e) BF_CLKCTRL_GPMI_DIV(BV_CLKCTRL_GPMI_DIV__##e)
#define BFM_CLKCTRL_GPMI_DIV_V(v) BM_CLKCTRL_GPMI_DIV
#define HW_CLKCTRL_SPDIF HW(CLKCTRL_SPDIF)
#define HWA_CLKCTRL_SPDIF (0x80040000 + 0xa0)
#define HWT_CLKCTRL_SPDIF HWIO_32_RW
#define HWN_CLKCTRL_SPDIF CLKCTRL_SPDIF
#define HWI_CLKCTRL_SPDIF
#define BP_CLKCTRL_SPDIF_CLKGATE 31
#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
#define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_SPDIF_CLKGATE(v) BM_CLKCTRL_SPDIF_CLKGATE
#define BF_CLKCTRL_SPDIF_CLKGATE_V(e) BF_CLKCTRL_SPDIF_CLKGATE(BV_CLKCTRL_SPDIF_CLKGATE__##e)
#define BFM_CLKCTRL_SPDIF_CLKGATE_V(v) BM_CLKCTRL_SPDIF_CLKGATE
#define BP_CLKCTRL_SPDIF_BUSY 30
#define BM_CLKCTRL_SPDIF_BUSY 0x40000000
#define BF_CLKCTRL_SPDIF_BUSY(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_SPDIF_BUSY(v) BM_CLKCTRL_SPDIF_BUSY
#define BF_CLKCTRL_SPDIF_BUSY_V(e) BF_CLKCTRL_SPDIF_BUSY(BV_CLKCTRL_SPDIF_BUSY__##e)
#define BFM_CLKCTRL_SPDIF_BUSY_V(v) BM_CLKCTRL_SPDIF_BUSY
#define BP_CLKCTRL_SPDIF_DIV 0
#define BM_CLKCTRL_SPDIF_DIV 0x7
#define BF_CLKCTRL_SPDIF_DIV(v) (((v) & 0x7) << 0)
#define BFM_CLKCTRL_SPDIF_DIV(v) BM_CLKCTRL_SPDIF_DIV
#define BF_CLKCTRL_SPDIF_DIV_V(e) BF_CLKCTRL_SPDIF_DIV(BV_CLKCTRL_SPDIF_DIV__##e)
#define BFM_CLKCTRL_SPDIF_DIV_V(v) BM_CLKCTRL_SPDIF_DIV
#define HW_CLKCTRL_EMI HW(CLKCTRL_EMI)
#define HWA_CLKCTRL_EMI (0x80040000 + 0xb0)
#define HWT_CLKCTRL_EMI HWIO_32_RW
#define HWN_CLKCTRL_EMI CLKCTRL_EMI
#define HWI_CLKCTRL_EMI
#define BP_CLKCTRL_EMI_CLKGATE 31
#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
#define BF_CLKCTRL_EMI_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_EMI_CLKGATE(v) BM_CLKCTRL_EMI_CLKGATE
#define BF_CLKCTRL_EMI_CLKGATE_V(e) BF_CLKCTRL_EMI_CLKGATE(BV_CLKCTRL_EMI_CLKGATE__##e)
#define BFM_CLKCTRL_EMI_CLKGATE_V(v) BM_CLKCTRL_EMI_CLKGATE
#define BP_CLKCTRL_EMI_WAIT_PLL_LOCK 30
#define BM_CLKCTRL_EMI_WAIT_PLL_LOCK 0x40000000
#define BF_CLKCTRL_EMI_WAIT_PLL_LOCK(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_EMI_WAIT_PLL_LOCK(v) BM_CLKCTRL_EMI_WAIT_PLL_LOCK
#define BF_CLKCTRL_EMI_WAIT_PLL_LOCK_V(e) BF_CLKCTRL_EMI_WAIT_PLL_LOCK(BV_CLKCTRL_EMI_WAIT_PLL_LOCK__##e)
#define BFM_CLKCTRL_EMI_WAIT_PLL_LOCK_V(v) BM_CLKCTRL_EMI_WAIT_PLL_LOCK
#define BP_CLKCTRL_EMI_BUSY 29
#define BM_CLKCTRL_EMI_BUSY 0x20000000
#define BF_CLKCTRL_EMI_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_EMI_BUSY(v) BM_CLKCTRL_EMI_BUSY
#define BF_CLKCTRL_EMI_BUSY_V(e) BF_CLKCTRL_EMI_BUSY(BV_CLKCTRL_EMI_BUSY__##e)
#define BFM_CLKCTRL_EMI_BUSY_V(v) BM_CLKCTRL_EMI_BUSY
#define BP_CLKCTRL_EMI_DIV 0
#define BM_CLKCTRL_EMI_DIV 0x7
#define BF_CLKCTRL_EMI_DIV(v) (((v) & 0x7) << 0)
#define BFM_CLKCTRL_EMI_DIV(v) BM_CLKCTRL_EMI_DIV
#define BF_CLKCTRL_EMI_DIV_V(e) BF_CLKCTRL_EMI_DIV(BV_CLKCTRL_EMI_DIV__##e)
#define BFM_CLKCTRL_EMI_DIV_V(v) BM_CLKCTRL_EMI_DIV
#define HW_CLKCTRL_IR HW(CLKCTRL_IR)
#define HWA_CLKCTRL_IR (0x80040000 + 0xc0)
#define HWT_CLKCTRL_IR HWIO_32_RW
#define HWN_CLKCTRL_IR CLKCTRL_IR
#define HWI_CLKCTRL_IR
#define BP_CLKCTRL_IR_CLKGATE 31
#define BM_CLKCTRL_IR_CLKGATE 0x80000000
#define BF_CLKCTRL_IR_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_IR_CLKGATE(v) BM_CLKCTRL_IR_CLKGATE
#define BF_CLKCTRL_IR_CLKGATE_V(e) BF_CLKCTRL_IR_CLKGATE(BV_CLKCTRL_IR_CLKGATE__##e)
#define BFM_CLKCTRL_IR_CLKGATE_V(v) BM_CLKCTRL_IR_CLKGATE
#define BP_CLKCTRL_IR_WAIT_PLL_LOCK 30
#define BM_CLKCTRL_IR_WAIT_PLL_LOCK 0x40000000
#define BF_CLKCTRL_IR_WAIT_PLL_LOCK(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_IR_WAIT_PLL_LOCK(v) BM_CLKCTRL_IR_WAIT_PLL_LOCK
#define BF_CLKCTRL_IR_WAIT_PLL_LOCK_V(e) BF_CLKCTRL_IR_WAIT_PLL_LOCK(BV_CLKCTRL_IR_WAIT_PLL_LOCK__##e)
#define BFM_CLKCTRL_IR_WAIT_PLL_LOCK_V(v) BM_CLKCTRL_IR_WAIT_PLL_LOCK
#define BP_CLKCTRL_IR_AUTO_DIV 29
#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
#define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_IR_AUTO_DIV(v) BM_CLKCTRL_IR_AUTO_DIV
#define BF_CLKCTRL_IR_AUTO_DIV_V(e) BF_CLKCTRL_IR_AUTO_DIV(BV_CLKCTRL_IR_AUTO_DIV__##e)
#define BFM_CLKCTRL_IR_AUTO_DIV_V(v) BM_CLKCTRL_IR_AUTO_DIV
#define BP_CLKCTRL_IR_IR_BUSY 28
#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
#define BF_CLKCTRL_IR_IR_BUSY(v) (((v) & 0x1) << 28)
#define BFM_CLKCTRL_IR_IR_BUSY(v) BM_CLKCTRL_IR_IR_BUSY
#define BF_CLKCTRL_IR_IR_BUSY_V(e) BF_CLKCTRL_IR_IR_BUSY(BV_CLKCTRL_IR_IR_BUSY__##e)
#define BFM_CLKCTRL_IR_IR_BUSY_V(v) BM_CLKCTRL_IR_IR_BUSY
#define BP_CLKCTRL_IR_IROV_BUSY 27
#define BM_CLKCTRL_IR_IROV_BUSY 0x8000000
#define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) & 0x1) << 27)
#define BFM_CLKCTRL_IR_IROV_BUSY(v) BM_CLKCTRL_IR_IROV_BUSY
#define BF_CLKCTRL_IR_IROV_BUSY_V(e) BF_CLKCTRL_IR_IROV_BUSY(BV_CLKCTRL_IR_IROV_BUSY__##e)
#define BFM_CLKCTRL_IR_IROV_BUSY_V(v) BM_CLKCTRL_IR_IROV_BUSY
#define BP_CLKCTRL_IR_IROV_DIV 16
#define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000
#define BF_CLKCTRL_IR_IROV_DIV(v) (((v) & 0x1ff) << 16)
#define BFM_CLKCTRL_IR_IROV_DIV(v) BM_CLKCTRL_IR_IROV_DIV
#define BF_CLKCTRL_IR_IROV_DIV_V(e) BF_CLKCTRL_IR_IROV_DIV(BV_CLKCTRL_IR_IROV_DIV__##e)
#define BFM_CLKCTRL_IR_IROV_DIV_V(v) BM_CLKCTRL_IR_IROV_DIV
#define BP_CLKCTRL_IR_IR_DIV 0
#define BM_CLKCTRL_IR_IR_DIV 0x3ff
#define BF_CLKCTRL_IR_IR_DIV(v) (((v) & 0x3ff) << 0)
#define BFM_CLKCTRL_IR_IR_DIV(v) BM_CLKCTRL_IR_IR_DIV
#define BF_CLKCTRL_IR_IR_DIV_V(e) BF_CLKCTRL_IR_IR_DIV(BV_CLKCTRL_IR_IR_DIV__##e)
#define BFM_CLKCTRL_IR_IR_DIV_V(v) BM_CLKCTRL_IR_IR_DIV
#endif /* __HEADERGEN_STMP3600_CLKCTRL_H__*/
Reference in a new issue View git blame Copy permalink