11cca264ff
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
250 lines
9.3 KiB
C
250 lines
9.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by James Espinoza
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef AVIC_IMX31_H
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#define AVIC_IMX31_H
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struct avic_map
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{
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volatile uint32_t intcntl; /* 00h */
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volatile uint32_t nimask; /* 04h */
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volatile uint32_t intennum; /* 08h */
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volatile uint32_t intdisnum; /* 0Ch */
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union /* 10h */
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{
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struct
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{
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volatile uint32_t intenableh; /* 10h */
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volatile uint32_t intenablel; /* 14h */
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};
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volatile uint32_t intenable[2]; /* H,L */
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};
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union
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{
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struct
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{
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volatile uint32_t inttypeh; /* 18h */
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volatile uint32_t inttypel; /* 1Ch */
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};
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volatile uint32_t inttype[2]; /* H,L */
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};
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union
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{
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struct
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{
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volatile uint32_t nipriority7; /* 20h */
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volatile uint32_t nipriority6; /* 24h */
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volatile uint32_t nipriority5; /* 28h */
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volatile uint32_t nipriority4; /* 2Ch */
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volatile uint32_t nipriority3; /* 30h */
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volatile uint32_t nipriority2; /* 34h */
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volatile uint32_t nipriority1; /* 38h */
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volatile uint32_t nipriority0; /* 3Ch */
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};
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volatile uint32_t nipriority[8]; /* 7-0 */
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};
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volatile uint32_t nivecsr; /* 40h */
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volatile uint32_t fivecsr; /* 44h */
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union
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{
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struct
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{
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volatile uint32_t intsrch; /* 48h */
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volatile uint32_t intsrcl; /* 4Ch */
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};
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volatile uint32_t intsrc[2]; /* H,L */
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};
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union
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{
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struct
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{
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volatile uint32_t intfrch; /* 50h */
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volatile uint32_t intfrcl; /* 54h */
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};
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volatile uint32_t intfrc[2]; /* H,L */
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};
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union
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{
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struct
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{
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volatile uint32_t nipndh; /* 58h */
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volatile uint32_t nipndl; /* 5Ch */
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};
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volatile uint32_t nipnd[2]; /* H,L */
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};
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union
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{
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struct
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{
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volatile uint32_t fipndh; /* 60h */
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volatile uint32_t fipndl; /* 64h */
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};
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volatile uint32_t fipnd[2]; /* H,L */
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};
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volatile uint32_t skip1[0x26]; /* 68h */
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union /* 100h */
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{
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struct
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{
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volatile uint32_t reserved0;
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volatile uint32_t reserved1;
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volatile uint32_t reserved2;
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volatile uint32_t i2c3;
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volatile uint32_t i2c2;
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volatile uint32_t mpeg4encoder;
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volatile uint32_t rtic;
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volatile uint32_t fir;
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volatile uint32_t mmc_sdhc2;
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volatile uint32_t mmc_sdhc1;
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volatile uint32_t i2c1;
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volatile uint32_t ssi2;
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volatile uint32_t ssi1;
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volatile uint32_t cspi2;
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volatile uint32_t cspi1;
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volatile uint32_t ata;
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volatile uint32_t mbx;
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volatile uint32_t cspi3;
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volatile uint32_t uart3;
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volatile uint32_t iim;
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volatile uint32_t sim1;
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volatile uint32_t sim2;
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volatile uint32_t rnga;
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volatile uint32_t evtmon;
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volatile uint32_t kpp;
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volatile uint32_t rtc;
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volatile uint32_t pwn;
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volatile uint32_t epit2;
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volatile uint32_t epit1;
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volatile uint32_t gpt;
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volatile uint32_t pwr_fail;
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volatile uint32_t ccm_dvfs;
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volatile uint32_t uart2;
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volatile uint32_t nandfc;
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volatile uint32_t sdma;
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volatile uint32_t usb_host1;
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volatile uint32_t usb_host2;
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volatile uint32_t usb_otg;
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volatile uint32_t reserved3;
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volatile uint32_t mshc1;
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volatile uint32_t mshc2;
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volatile uint32_t ipu_err;
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volatile uint32_t ipu;
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volatile uint32_t reserved4;
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volatile uint32_t reserved5;
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volatile uint32_t uart1;
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volatile uint32_t uart4;
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volatile uint32_t uart5;
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volatile uint32_t etc_irq;
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volatile uint32_t scc_scm;
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volatile uint32_t scc_smn;
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volatile uint32_t gpio2;
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volatile uint32_t gpio1;
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volatile uint32_t ccm_clk;
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volatile uint32_t pcmcia;
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volatile uint32_t wdog;
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volatile uint32_t gpio3;
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volatile uint32_t reserved6;
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volatile uint32_t ext_pwmg;
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volatile uint32_t ext_temp;
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volatile uint32_t ext_sense1;
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volatile uint32_t ext_sense2;
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volatile uint32_t ext_wdog;
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volatile uint32_t ext_tv;
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};
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volatile uint32_t vector[0x40]; /* 100h */
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};
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};
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/* #define IRQ priorities for different modules (0-15) */
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#define INT_PRIO_DEFAULT 7
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#define INT_PRIO_DVFS (INT_PRIO_DEFAULT+1)
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#define INT_PRIO_DPTC (INT_PRIO_DEFAULT+1)
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#define INT_PRIO_SDMA (INT_PRIO_DEFAULT+2)
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enum INT_TYPE
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{
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INT_TYPE_IRQ = 0,
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INT_TYPE_FIQ
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};
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enum IMX31_INT_LIST
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{
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__IMX31_INT_FIRST = -1,
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INT_RESERVED0, INT_RESERVED1, INT_RESERVED2, INT_I2C3,
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INT_I2C2, INT_MPEG4_ENCODER, INT_RTIC, INT_FIR,
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INT_MMC_SDHC2, INT_MMC_SDHC1, INT_I2C1, INT_SSI2,
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INT_SSI1, INT_CSPI2, INT_CSPI1, INT_ATA,
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INT_MBX, INT_CSPI3, INT_UART3, INT_IIM,
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INT_SIM1, INT_SIM2, INT_RNGA, INT_EVTMON,
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INT_KPP, INT_RTC, INT_PWN, INT_EPIT2,
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INT_EPIT1, INT_GPT, INT_PWR_FAIL, INT_CCM_DVFS,
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INT_UART2, INT_NANDFC, INT_SDMA, INT_USB_HOST1,
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INT_USB_HOST2, INT_USB_OTG, INT_RESERVED3, INT_MSHC1,
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INT_MSHC2, INT_IPU_ERR, INT_IPU, INT_RESERVED4,
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INT_RESERVED5, INT_UART1, INT_UART4, INT_UART5,
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INT_ETC_IRQ, INT_SCC_SCM, INT_SCC_SMN, INT_GPIO2,
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INT_GPIO1, INT_CCM_CLK, INT_PCMCIA, INT_WDOG,
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INT_GPIO3, INT_RESERVED6, INT_EXT_PWMG, INT_EXT_TEMP,
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INT_EXT_SENS1, INT_EXT_SENS2, INT_EXT_WDOG, INT_EXT_TV,
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INT_ALL
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};
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void avic_init(void);
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void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
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unsigned long ni_priority, void (*handler)(void));
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void avic_set_int_priority(enum IMX31_INT_LIST ints,
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unsigned long ni_priority);
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void avic_disable_int(enum IMX31_INT_LIST ints);
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void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype);
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#define AVIC_NIL_DISABLE 0xf
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#define AVIC_NIL_ENABLE 0x1f
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void avic_set_ni_level(unsigned int level);
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/* Call a service routine while allowing preemption by interrupts of higher
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* priority. r4-r7 must be preserved for epilogue code to restore context. */
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#define AVIC_NESTED_NI_CALL_PROLOGUE() \
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({ asm volatile ( \
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"sub lr, lr, #4 \n" /* prepare return address */ \
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"stmfd sp!, { r0-r7, r12, lr } \n" /* preserve return context */ \
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"mov r0, #0x68000000 \n" /* AVIC_BASE_ADDR */ \
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"mrs r4, spsr \n" /* save SPSR_irq */ \
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"ldr r5, [r0, #0x04] \n" /* save NIMASK */ \
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"ldr r1, [r0, #0x40] \n" /* load NIVECSR */ \
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"mov r2, sp \n" /* remember IRQ stack to use in call */ \
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"str r1, [r0, #0x04] \n" /* copy NIVECSR to NIMASK */ \
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"cps #0x13 \n" /* switch to SVC mode (+ unmask IRQ) */ \
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"mov r6, sp \n" /* save SP_svc */ \
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"mov r7, lr \n" /* save LR_svc */ \
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"mov sp, r2 \n" /* switch to SP_irq */ \
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); })
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#define AVIC_NESTED_NI_CALL_EPILOGUE() \
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({ asm volatile ( \
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"mov sp, r6 \n" /* restore SP_svc */ \
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"mov lr, r7 \n" /* restore LR_svc */ \
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"cps #0x12 \n" /* return to IRQ mode (+ mask IRQ) */ \
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"mov r0, #0x68000000 \n" /* AVIC BASE ADDR */ \
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"msr spsr_cxsf, r4 \n" /* restore SPSR_irq */ \
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"str r5, [r0, #0x04] \n" /* restore NIMASK */ \
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"ldmfd sp!, { r0-r7, r12, pc }^ \n" /* reload context and return */ \
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); })
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#endif /* AVIC_IMX31_H */
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