2220a4b695
Fix stuff that was bugging me about the way I did it at first. While messing around I found RDS code wasn't masking its GPIO ISR as it should, which might lead to two different interrupts messing with the static data. Change-Id: I54626809ea3039a842af0cc9e3e42853326c4193
380 lines
12 KiB
C
380 lines
12 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (c) 2008 by Michael Sevakis
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "cpu.h"
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#define DEFINE_MC13783_VECTOR_TABLE
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#include "mc13783-target.h"
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#include "gpio-target.h"
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#include "debug.h"
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#include "kernel.h"
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/* Extend the basic SPI transfer descriptor with our own fields */
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struct mc13783_transfer_desc
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{
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struct spi_transfer_desc xfer;
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union
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{
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/* Pick _either_ data or semaphore */
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struct semaphore sema;
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uint32_t data[4];
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};
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};
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static uint32_t pmic_int_enb[2]; /* Enabled ints */
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static uint32_t pmic_int_sense_enb[2]; /* Enabled sense reading */
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static struct mc13783_transfer_desc int_xfers[2]; /* ISR transfer descriptor */
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static const struct mc13783_event *current_event; /* Current event in callback */
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static bool int_restore; /* Prevent SPI callback from
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unmasking GPIO interrupt
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(lockout) */
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static const struct mc13783_event * event_from_id(enum mc13783_int_ids id)
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{
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for (unsigned int i = 0; i < mc13783_event_vector_tbl_len; i++)
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{
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if (mc13783_event_vector_tbl[i].id == id)
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return &mc13783_event_vector_tbl[i];
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}
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return NULL;
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}
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/* Called when a transfer is finished and data is ready/written */
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static void mc13783_xfer_complete_cb(struct spi_transfer_desc *xfer)
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{
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semaphore_release(&((struct mc13783_transfer_desc *)xfer)->sema);
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}
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static inline bool wait_for_transfer_complete(struct mc13783_transfer_desc *xfer)
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{
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return semaphore_wait(&xfer->sema, TIMEOUT_BLOCK)
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== OBJ_WAIT_SUCCEEDED && xfer->xfer.count == 0;
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}
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static inline bool mc13783_transfer(struct spi_transfer_desc *xfer,
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uint32_t *txbuf,
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uint32_t *rxbuf,
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int count,
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spi_transfer_cb_fn_type callback)
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{
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xfer->node = &mc13783_spi;
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xfer->txbuf = txbuf;
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xfer->rxbuf = rxbuf;
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xfer->count = count;
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xfer->callback = callback;
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xfer->next = NULL;
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return spi_transfer(xfer);
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}
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static inline void sync_transfer_init(struct mc13783_transfer_desc *xfer)
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{
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semaphore_init(&xfer->sema, 1, 0);
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}
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static inline bool mc13783_sync_transfer(struct mc13783_transfer_desc *xfer,
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uint32_t *txbuf,
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uint32_t *rxbuf,
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int count)
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{
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sync_transfer_init(xfer);
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return mc13783_transfer(&xfer->xfer, txbuf, rxbuf, count, mc13783_xfer_complete_cb);
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}
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/* Efficient interrupt status and acking */
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static void mc13783_int_svc_complete_callback(struct spi_transfer_desc *xfer)
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{
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struct mc13783_transfer_desc *desc1 = (struct mc13783_transfer_desc *)xfer;
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uint32_t pnd0 = desc1->data[0], pnd1 = desc1->data[1];
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/* Restore PMIC interrupt events */
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if (int_restore)
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gpio_int_enable(MC13783_EVENT_ID);
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/* Call handlers */
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const struct mc13783_event *event = mc13783_event_vector_tbl;
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while (pnd0 | pnd1)
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{
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uint32_t id = event->id;
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uint32_t set = id / 32;
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uint32_t bit = 1 << (id % 32);
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uint32_t pnd = set == 0 ? pnd0 : pnd1;
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if (pnd & bit)
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{
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current_event = event;
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event->callback();
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set == 0 ? (pnd0 &= ~bit) : (pnd1 &= ~bit);
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}
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event++;
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}
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}
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static void mc13783_int_svc_callback(struct spi_transfer_desc *xfer)
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{
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/* Only clear interrupts with handlers */
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struct mc13783_transfer_desc *desc0 = (struct mc13783_transfer_desc *)xfer;
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struct mc13783_transfer_desc *desc1 = &int_xfers[1];
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uint32_t pnd0 = desc0->data[0] & pmic_int_enb[0];
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uint32_t pnd1 = desc0->data[1] & pmic_int_enb[1];
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desc1->data[0] = pnd0;
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desc1->data[1] = pnd1;
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/* Setup the write packets with status(es) to clear */
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desc0->data[0] = (1 << 31) | (MC13783_INTERRUPT_STATUS0 << 25) | pnd0;
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desc0->data[1] = (1 << 31) | (MC13783_INTERRUPT_STATUS1 << 25) | pnd1;
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/* Only read sense if any pending interrupts have them enabled */
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if ((pnd0 & pmic_int_sense_enb[0]) || (pnd1 & pmic_int_sense_enb[1]))
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{
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desc0->data[2] = MC13783_INTERRUPT_SENSE0 << 25;
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desc0->data[3] = MC13783_INTERRUPT_SENSE1 << 25;
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desc1->xfer.rxbuf = desc0->data;
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desc1->xfer.count = 4;
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}
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}
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/* GPIO interrupt handler for mc13783 */
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void INT_MC13783(void)
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{
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/* Mask the interrupt (unmasked after final read services it). */
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gpio_int_disable(MC13783_EVENT_ID);
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gpio_int_clear(MC13783_EVENT_ID);
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/* Setup the read packets */
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int_xfers[0].data[0] = MC13783_INTERRUPT_STATUS0 << 25;
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int_xfers[0].data[1] = MC13783_INTERRUPT_STATUS1 << 25;
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unsigned long cpsr = disable_irq_save();
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/* Do these without intervening transfers */
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if (mc13783_transfer(&int_xfers[0].xfer, int_xfers[0].data,
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int_xfers[0].data, 2, mc13783_int_svc_callback))
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{
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/* Start this provisionally and fill-in actual values during the
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first transfer's callback - set whatever could be known */
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mc13783_transfer(&int_xfers[1].xfer, int_xfers[0].data, NULL, 2,
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mc13783_int_svc_complete_callback);
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}
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restore_irq(cpsr);
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}
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void INIT_ATTR mc13783_init(void)
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{
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/* Serial interface must have been initialized first! */
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/* Enable the PMIC SPI module */
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spi_enable_node(&mc13783_spi, true);
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/* Mask any PMIC interrupts for now - modules will enable them as
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* required */
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mc13783_write(MC13783_INTERRUPT_MASK0, 0xffffff);
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mc13783_write(MC13783_INTERRUPT_MASK1, 0xffffff);
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gpio_int_clear(MC13783_EVENT_ID);
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gpio_enable_event(MC13783_EVENT_ID, true);
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}
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void mc13783_close(void)
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{
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int_restore = false;
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gpio_int_disable(MC13783_EVENT_ID);
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gpio_enable_event(MC13783_EVENT_ID, false);
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spi_enable_node(&mc13783_spi, false);
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}
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void mc13783_enable_event(enum mc13783_int_ids id, bool enable)
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{
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static const unsigned char pmic_intm_regs[2] =
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{ MC13783_INTERRUPT_MASK0, MC13783_INTERRUPT_MASK1 };
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const struct mc13783_event * const event = event_from_id(id);
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if (event == NULL)
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return;
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unsigned int set = id / 32;
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uint32_t mask = 1 << (id % 32);
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uint32_t bit = enable ? mask : 0;
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/* Mask GPIO while changing bits around */
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int_restore = false;
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gpio_int_disable(MC13783_EVENT_ID);
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mc13783_write_masked(pmic_intm_regs[set], bit ^ mask, mask);
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bitmod32(&pmic_int_sense_enb[set], event->sense ? bit : 0, mask);
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bitmod32(&pmic_int_enb[set], bit, mask);
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int_restore = true;
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gpio_int_enable(MC13783_EVENT_ID);
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}
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uint32_t mc13783_event_sense(void)
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{
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const struct mc13783_event *event = current_event;
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return int_xfers[0].data[2 + event->id / 32] & event->sense;
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}
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uint32_t mc13783_set(unsigned address, uint32_t bits)
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{
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return mc13783_write_masked(address, bits, bits);
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}
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uint32_t mc13783_clear(unsigned address, uint32_t bits)
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{
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return mc13783_write_masked(address, 0, bits);
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}
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/* Called when the first transfer of mc13783_write_masked is complete */
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static void mc13783_write_masked_cb(struct spi_transfer_desc *xfer)
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{
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struct mc13783_transfer_desc *desc = (struct mc13783_transfer_desc *)xfer;
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desc->data[1] |= desc->data[0] & desc->data[2]; /* & ~mask */
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}
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uint32_t mc13783_write_masked(unsigned address, uint32_t data, uint32_t mask)
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{
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if (address >= MC13783_NUM_REGS)
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return MC13783_DATA_ERROR;
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mask &= 0xffffff;
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struct mc13783_transfer_desc xfers[2];
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xfers[0].data[0] = address << 25;
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xfers[0].data[1] = (1 << 31) | (address << 25) | (data & mask);
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xfers[0].data[2] = ~mask;
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unsigned long cpsr = disable_irq_save();
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/* Queue up two transfers in a row */
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bool ok = mc13783_transfer(&xfers[0].xfer,
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&xfers[0].data[0], &xfers[0].data[0], 1,
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mc13783_write_masked_cb) &&
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mc13783_sync_transfer(&xfers[1], &xfers[0].data[1], NULL, 1);
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restore_irq(cpsr);
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if (ok && wait_for_transfer_complete(&xfers[1]))
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return xfers[0].data[0];
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return MC13783_DATA_ERROR;
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}
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uint32_t mc13783_read(unsigned address)
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{
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if (address >= MC13783_NUM_REGS)
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return MC13783_DATA_ERROR;
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uint32_t packet = address << 25;
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struct mc13783_transfer_desc xfer;
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if (mc13783_sync_transfer(&xfer, &packet, &packet, 1) &&
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wait_for_transfer_complete(&xfer))
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{
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return packet;
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}
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return MC13783_DATA_ERROR;
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}
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int mc13783_write(unsigned address, uint32_t data)
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{
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if (address >= MC13783_NUM_REGS)
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return -1;
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uint32_t packet = (1 << 31) | (address << 25) | (data & 0xffffff);
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struct mc13783_transfer_desc xfer;
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if (mc13783_sync_transfer(&xfer, &packet, NULL, 1) &&
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wait_for_transfer_complete(&xfer))
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{
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return 1 - xfer.xfer.count;
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}
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return -1;
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}
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int mc13783_read_regs(const unsigned char *regs, uint32_t *buffer,
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int count)
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{
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struct mc13783_transfer_desc xfer;
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sync_transfer_init(&xfer);
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if (mc13783_read_async(&xfer.xfer, regs, buffer, count,
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mc13783_xfer_complete_cb) &&
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wait_for_transfer_complete(&xfer))
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{
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return count - xfer.xfer.count;
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}
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return -1;
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}
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int mc13783_write_regs(const unsigned char *regs, uint32_t *buffer,
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int count)
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{
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struct mc13783_transfer_desc xfer;
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sync_transfer_init(&xfer);
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if (mc13783_write_async(&xfer.xfer, regs, buffer, count,
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mc13783_xfer_complete_cb) &&
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wait_for_transfer_complete(&xfer))
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{
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return count - xfer.xfer.count;
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}
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return -1;
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}
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bool mc13783_read_async(struct spi_transfer_desc *xfer,
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const unsigned char *regs, uint32_t *buffer,
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int count, spi_transfer_cb_fn_type callback)
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{
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for (int i = 0; i < count; i++)
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{
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unsigned reg = regs[i];
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if (reg >= MC13783_NUM_REGS)
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return false;
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buffer[i] = reg << 25;
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}
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return mc13783_transfer(xfer, buffer, buffer, count, callback);
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}
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bool mc13783_write_async(struct spi_transfer_desc *xfer,
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const unsigned char *regs, uint32_t *buffer,
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int count, spi_transfer_cb_fn_type callback)
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{
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for (int i = 0; i < count; i++)
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{
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unsigned reg = regs[i];
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if (reg >= MC13783_NUM_REGS)
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return false;
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buffer[i] = (1 << 31) | (reg << 25) | (buffer[i] & 0xffffff);
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}
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return mc13783_transfer(xfer, buffer, NULL, count, callback);
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}
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