6109a3b0be
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7270 a1c6a512-1295-4272-9138-f99709370657
62 lines
3 KiB
C
62 lines
3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 by Christian Gmeiner
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __MCF5250_H__
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#define __MCF5250_H__
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#include "mcf5249.h"
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/* here we undefine stuff which is different from mcf5249 */
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#undef SPURVEC
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#undef INTBASE
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#undef TER0
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#undef TER1
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/* here we remove stuff, which is not included in mfc5250 */
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#undef DACR1
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#undef DMR1
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#undef INTERRUPTSTAT3
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#undef INTERRUPTCLEAR3
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#undef INTERRUPTEN3
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#undef IPERRORADR
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/* here we define some new stuff */
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#define IPR (*(volatile unsigned long *)(MBAR + 0x040)) /* interrupt oending register */
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#define IMR (*(volatile unsigned long *)(MBAR + 0x044)) /* Interrupt Mask Register */
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#define ICR1 (*(volatile unsigned long *)(MBAR + 0x04d)) /* Primary interrupt control reg: timer 0 */
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#define ICR2 (*(volatile unsigned long *)(MBAR + 0x04e)) /* Primary interrupt control reg: timer 1 */
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#define ICR3 (*(volatile unsigned long *)(MBAR + 0x04f)) /* Primary interrupt control reg: i2c0 */
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#define ICR5 (*(volatile unsigned long *)(MBAR + 0x051)) /* Primary interrupt control reg: uart1 */
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#define ICR6 (*(volatile unsigned long *)(MBAR + 0x052)) /* Primary interrupt control reg: dma0 */
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#define ICR7 (*(volatile unsigned long *)(MBAR + 0x053)) /* Primary interrupt control reg: dam1 */
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#define ICR9 (*(volatile unsigned long *)(MBAR + 0x055)) /* Primary interrupt control reg: dam3 */
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#define ICR10 (*(volatile unsigned long *)(MBAR + 0x056)) /* Primary interrupt control reg: qspi */
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#define CSAR4 (*(volatile unsigned long *)(MBAR + 0x0b0)) /* Chip Select Address Register Bank 4 */
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#define CSMR4 (*(volatile unsigned long *)(MBAR + 0x0b4)) /* Chip Select Mask Register Bank 4 */
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#define CSCR4 (*(volatile unsigned long *)(MBAR + 0x0b8)) /* Chip Select Control Register Bank 4 */
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/* here we define changed stuff */
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#define TER0 (*(volatile unsigned short *)(MBAR + 0x151)) /* Timer0 Event Register */
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#define TER1 (*(volatile unsigned short *)(MBAR + 0x191)) /* Timer1 Event Register */
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#define SPURVEC (*(volatile unsigned char *)(MBAR2 + 0x164)) /* spurious secondary interrupt vector */
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#define INTBASE (*(volatile unsigned char *)(MBAR2 + 0x168)) /* secondary interrupt base vector register */
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#endif
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