2acc0ac542
later. We still need to hunt down snippets used that are not. 1324 modified files... http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (c) 2008 Michael Sevakis
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*
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* Clock control functions for IMX31 processor
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _CLKCTL_IMX31_H_
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#define _CLKCTL_IMX31_H_
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enum IMX31_CG_LIST
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{
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/* CGR0 */
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CG_SD_MMC1 = 0,
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CG_SD_MMC2,
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CG_GPT,
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CG_EPIT1,
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CG_EPIT2,
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CG_IIM,
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CG_ATA,
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CG_SDMA,
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CG_CSPI3,
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CG_RNG,
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CG_UART1,
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CG_UART2,
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CG_SSI1,
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CG_I2C1,
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CG_I2C2,
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CG_I2C3,
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/* CGR1 */
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CG_HANTRO,
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CG_MEMSTICK1,
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CG_MEMSTICK2,
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CG_CSI,
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CG_RTC,
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CG_WDOG,
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CG_PWM,
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CG_SIM,
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CG_ECT,
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CG_USBOTG,
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CG_KPP,
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CG_IPU,
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CG_UART3,
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CG_UART4,
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CG_UART5,
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CG_1_WIRE,
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/* CGR2 */
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CG_SSI2,
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CG_CSPI1,
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CG_CSPI2,
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CG_GACC,
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CG_EMI,
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CG_RTIC,
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CG_FIR,
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CG_NUM_CLOCKS
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};
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enum IMX31_CG_MODES
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{
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CGM_OFF = 0x0, /* Always off */
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CGM_ON_RUN = 0x1, /* On in run mode, off in wait and doze */
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CGM_ON_RUN_WAIT = 0x2, /* On in run and wait modes, off in doze */
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CGM_ON_ALL = 0x3, /* Always on */
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};
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#define CG_MASK 0x3 /* bitmask */
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/* Enable or disable module clocks independently - module must _not_ be
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* active! */
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void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg,
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enum IMX31_CG_MODES mode);
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enum IMX31_PLLS
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{
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PLL_MCU = 0,
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PLL_USB,
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PLL_SERIAL,
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NUM_PLLS,
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};
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#define CONFIG_CLK32_FREQ 32768
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#define CONFIG_HCLK_FREQ 27000000
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/* Get the PLL reference clock frequency in HZ */
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unsigned int imx31_clkctl_get_pll_ref_clk(void);
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/* Return PLL frequency in HZ */
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unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll);
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/* Return ipg_clk in HZ */
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unsigned int imx31_clkctl_get_ipg_clk(void);
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/* Return the ATA frequency in HZ */
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unsigned int imx31_clkctl_get_ata_clk(void);
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#endif /* _CLKCTL_IMX31_H_ */
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