4e8320d2ec
Might as well rename spi_enable_module to spi_enable_node for consistency as well so long as I'm being picky. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31442 a1c6a512-1295-4272-9138-f99709370657
363 lines
10 KiB
C
363 lines
10 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (c) 2008 by Michael Sevakis
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "cpu.h"
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#include "gpio-imx31.h"
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#include "mc13783.h"
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#include "mc13783-target.h"
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#include "debug.h"
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#include "kernel.h"
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extern const struct mc13783_event mc13783_events[MC13783_NUM_EVENTS];
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extern struct spi_node mc13783_spi;
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/* PMIC event service data */
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static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)];
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static const char * const mc13783_thread_name = "pmic";
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static struct semaphore mc13783_svc_wake;
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/* Tracking for which interrupts are enabled */
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static uint32_t pmic_int_enabled[2] =
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{ 0x00000000, 0x00000000 };
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static const unsigned char pmic_intm_regs[2] =
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{ MC13783_INTERRUPT_MASK0, MC13783_INTERRUPT_MASK1 };
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static const unsigned char pmic_ints_regs[2] =
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{ MC13783_INTERRUPT_STATUS0, MC13783_INTERRUPT_STATUS1 };
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static volatile unsigned int mc13783_thread_id = 0;
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/* Extend the basic SPI transfer descriptor with our own fields */
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struct mc13783_transfer_desc
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{
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struct spi_transfer_desc xfer;
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union
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{
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struct semaphore sema;
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uint32_t data;
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};
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};
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/* Called when a transfer is finished and data is ready/written */
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static void mc13783_xfer_complete_cb(struct spi_transfer_desc *xfer)
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{
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semaphore_release(&((struct mc13783_transfer_desc *)xfer)->sema);
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}
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static inline bool wait_for_transfer_complete(struct mc13783_transfer_desc *xfer)
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{
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return semaphore_wait(&xfer->sema, TIMEOUT_BLOCK)
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== OBJ_WAIT_SUCCEEDED && xfer->xfer.count == 0;
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}
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static void mc13783_interrupt_thread(void)
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{
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uint32_t pending[2];
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/* Enable mc13783 GPIO event */
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gpio_enable_event(MC13783_EVENT_ID);
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while (1)
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{
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const struct mc13783_event *event, *event_last;
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semaphore_wait(&mc13783_svc_wake, TIMEOUT_BLOCK);
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if (mc13783_thread_id == 0)
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break;
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mc13783_read_regs(pmic_ints_regs, pending, 2);
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/* Only clear interrupts being dispatched */
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pending[0] &= pmic_int_enabled[0];
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pending[1] &= pmic_int_enabled[1];
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mc13783_write_regs(pmic_ints_regs, pending, 2);
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/* Whatever is going to be serviced in this loop has been
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* acknowledged. Reenable interrupt and if anything was still
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* pending or became pending again, another signal will be
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* generated. */
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bitset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
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event = mc13783_events;
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event_last = event + MC13783_NUM_EVENTS;
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/* .count is surely expected to be > 0 */
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do
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{
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unsigned int set = event->int_id / MC13783_INT_ID_SET_DIV;
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uint32_t pnd = pending[set];
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uint32_t mask = 1 << (event->int_id & MC13783_INT_ID_NUM_MASK);
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if (pnd & mask)
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{
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event->callback();
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pending[set] = pnd & ~mask;
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}
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if ((pending[0] | pending[1]) == 0)
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break; /* Terminate early if nothing more to service */
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}
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while (++event < event_last);
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}
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gpio_disable_event(MC13783_EVENT_ID);
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}
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/* GPIO interrupt handler for mc13783 */
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void mc13783_event(void)
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{
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/* Mask the interrupt (unmasked when PMIC thread services it). */
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bitclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
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MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
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semaphore_release(&mc13783_svc_wake);
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}
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void INIT_ATTR mc13783_init(void)
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{
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/* Serial interface must have been initialized first! */
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semaphore_init(&mc13783_svc_wake, 1, 0);
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/* Enable the PMIC SPI module */
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spi_enable_node(&mc13783_spi, true);
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/* Mask any PMIC interrupts for now - modules will enable them as
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* required */
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mc13783_write(MC13783_INTERRUPT_MASK0, 0xffffff);
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mc13783_write(MC13783_INTERRUPT_MASK1, 0xffffff);
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MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
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mc13783_thread_id =
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create_thread(mc13783_interrupt_thread,
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mc13783_thread_stack, sizeof(mc13783_thread_stack), 0,
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mc13783_thread_name IF_PRIO(, PRIORITY_REALTIME) IF_COP(, CPU));
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}
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void mc13783_close(void)
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{
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unsigned int thread_id = mc13783_thread_id;
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if (thread_id == 0)
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return;
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mc13783_thread_id = 0;
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semaphore_release(&mc13783_svc_wake);
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thread_wait(thread_id);
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spi_enable_node(&mc13783_spi, false);
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}
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bool mc13783_enable_event(enum mc13783_event_ids id)
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{
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const struct mc13783_event * const event = &mc13783_events[id];
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unsigned int set = event->int_id / MC13783_INT_ID_SET_DIV;
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uint32_t mask = 1 << (event->int_id & MC13783_INT_ID_NUM_MASK);
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pmic_int_enabled[set] |= mask;
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mc13783_clear(pmic_intm_regs[set], mask);
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return true;
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}
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void mc13783_disable_event(enum mc13783_event_ids id)
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{
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const struct mc13783_event * const event = &mc13783_events[id];
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unsigned int set = event->int_id / MC13783_INT_ID_SET_DIV;
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uint32_t mask = 1 << (event->int_id & MC13783_INT_ID_NUM_MASK);
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pmic_int_enabled[set] &= ~mask;
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mc13783_set(pmic_intm_regs[set], mask);
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}
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static inline bool mc13783_transfer(struct spi_transfer_desc *xfer,
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uint32_t *txbuf,
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uint32_t *rxbuf,
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int count,
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spi_transfer_cb_fn_type callback)
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{
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xfer->node = &mc13783_spi;
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xfer->txbuf = txbuf;
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xfer->rxbuf = rxbuf;
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xfer->count = count;
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xfer->callback = callback;
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xfer->next = NULL;
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return spi_transfer(xfer);
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}
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uint32_t mc13783_set(unsigned address, uint32_t bits)
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{
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return mc13783_write_masked(address, bits, bits);
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}
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uint32_t mc13783_clear(unsigned address, uint32_t bits)
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{
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return mc13783_write_masked(address, 0, bits);
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}
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/* Called when the first transfer of mc13783_write_masked is complete */
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static void mc13783_write_masked_cb(struct spi_transfer_desc *xfer)
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{
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struct mc13783_transfer_desc *desc = (struct mc13783_transfer_desc *)xfer;
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uint32_t *packets = desc->xfer.rxbuf; /* Will have been advanced by 1 */
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packets[0] |= packets[-1] & ~desc->data;
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}
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uint32_t mc13783_write_masked(unsigned address, uint32_t data, uint32_t mask)
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{
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if (address >= MC13783_NUM_REGS)
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return MC13783_DATA_ERROR;
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mask &= 0xffffff;
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uint32_t packets[2] =
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{
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address << 25,
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(1 << 31) | (address << 25) | (data & mask)
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};
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struct mc13783_transfer_desc xfers[2];
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xfers[0].data = mask;
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semaphore_init(&xfers[1].sema, 1, 0);
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unsigned long cpsr = disable_irq_save();
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/* Queue up two transfers in a row */
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bool ok = mc13783_transfer(&xfers[0].xfer, &packets[0], &packets[0], 1,
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mc13783_write_masked_cb) &&
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mc13783_transfer(&xfers[1].xfer, &packets[1], NULL, 1,
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mc13783_xfer_complete_cb);
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restore_irq(cpsr);
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if (ok && wait_for_transfer_complete(&xfers[1]))
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return packets[0];
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return MC13783_DATA_ERROR;
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}
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uint32_t mc13783_read(unsigned address)
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{
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if (address >= MC13783_NUM_REGS)
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return MC13783_DATA_ERROR;
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uint32_t packet = address << 25;
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struct mc13783_transfer_desc xfer;
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semaphore_init(&xfer.sema, 1, 0);
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if (mc13783_transfer(&xfer.xfer, &packet, &packet, 1,
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mc13783_xfer_complete_cb) &&
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wait_for_transfer_complete(&xfer))
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{
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return packet;
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}
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return MC13783_DATA_ERROR;
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}
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int mc13783_write(unsigned address, uint32_t data)
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{
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if (address >= MC13783_NUM_REGS)
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return -1;
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uint32_t packet = (1 << 31) | (address << 25) | (data & 0xffffff);
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struct mc13783_transfer_desc xfer;
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semaphore_init(&xfer.sema, 1, 0);
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if (mc13783_transfer(&xfer.xfer, &packet, NULL, 1,
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mc13783_xfer_complete_cb) &&
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wait_for_transfer_complete(&xfer))
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{
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return 1 - xfer.xfer.count;
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}
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return -1;
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}
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int mc13783_read_regs(const unsigned char *regs, uint32_t *buffer,
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int count)
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{
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struct mc13783_transfer_desc xfer;
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semaphore_init(&xfer.sema, 1, 0);
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if (mc13783_read_async(&xfer.xfer, regs, buffer, count,
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mc13783_xfer_complete_cb) &&
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wait_for_transfer_complete(&xfer))
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{
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return count - xfer.xfer.count;
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}
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return -1;
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}
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int mc13783_write_regs(const unsigned char *regs, uint32_t *buffer,
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int count)
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{
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struct mc13783_transfer_desc xfer;
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semaphore_init(&xfer.sema, 1, 0);
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if (mc13783_write_async(&xfer.xfer, regs, buffer, count,
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mc13783_xfer_complete_cb) &&
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wait_for_transfer_complete(&xfer))
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{
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return count - xfer.xfer.count;
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}
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return -1;
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}
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bool mc13783_read_async(struct spi_transfer_desc *xfer,
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const unsigned char *regs, uint32_t *buffer,
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int count, spi_transfer_cb_fn_type callback)
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{
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for (int i = 0; i < count; i++)
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{
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unsigned reg = regs[i];
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if (reg >= MC13783_NUM_REGS)
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return false;
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buffer[i] = reg << 25;
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}
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return mc13783_transfer(xfer, buffer, buffer, count, callback);
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}
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bool mc13783_write_async(struct spi_transfer_desc *xfer,
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const unsigned char *regs, uint32_t *buffer,
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int count, spi_transfer_cb_fn_type callback)
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{
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for (int i = 0; i < count; i++)
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{
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unsigned reg = regs[i];
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if (reg >= MC13783_NUM_REGS)
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return false;
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buffer[i] = (1 << 31) | (reg << 25) | (buffer[i] & 0xffffff);
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}
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return mc13783_transfer(xfer, buffer, NULL, count, callback);
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}
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