4a483bb1bf
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21208 a1c6a512-1295-4272-9138-f99709370657
322 lines
9.9 KiB
C
322 lines
9.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Karl Kurbjun
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "cpu.h"
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#include "mmu-arm.h"
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#include "uart-target.h"
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#include "system-arm.h"
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#include "spi.h"
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#ifdef CREATIVE_ZVx
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#include "dma-target.h"
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#include "usb-mr500.h"
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#endif
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
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default_interrupt(TIMER0);
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default_interrupt(TIMER1);
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default_interrupt(TIMER2);
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default_interrupt(TIMER3);
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default_interrupt(CCD_VD0);
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default_interrupt(CCD_VD1);
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default_interrupt(CCD_WEN);
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default_interrupt(VENC);
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default_interrupt(SERIAL0);
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default_interrupt(SERIAL1);
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default_interrupt(EXT_HOST);
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default_interrupt(DSPHINT);
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default_interrupt(UART0);
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default_interrupt(UART1);
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default_interrupt(USB_DMA);
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default_interrupt(USB_CORE);
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default_interrupt(VLYNQ);
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default_interrupt(MTC0);
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default_interrupt(MTC1);
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default_interrupt(SD_MMC);
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default_interrupt(SDIO_MS);
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default_interrupt(GIO0);
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default_interrupt(GIO1);
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default_interrupt(GIO2);
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default_interrupt(GIO3);
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default_interrupt(GIO4);
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default_interrupt(GIO5);
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default_interrupt(GIO6);
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default_interrupt(GIO7);
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default_interrupt(GIO8);
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default_interrupt(GIO9);
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default_interrupt(GIO10);
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default_interrupt(GIO11);
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default_interrupt(GIO12);
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default_interrupt(GIO13);
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default_interrupt(GIO14);
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default_interrupt(GIO15);
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default_interrupt(PREVIEW0);
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default_interrupt(PREVIEW1);
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default_interrupt(WATCHDOG);
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default_interrupt(I2C);
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default_interrupt(CLKC);
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default_interrupt(ICE);
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default_interrupt(ARMCOM_RX);
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default_interrupt(ARMCOM_TX);
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default_interrupt(RESERVED);
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/* The entry address is equal to base address plus an offset.
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* The offset is based on the priority of the interrupt. So if
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* the priority of an interrupt is changed, the user should also
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* change the offset for the interrupt in the entry table.
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*/
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static const unsigned short const irqpriority[] =
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{
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IRQ_TIMER0,IRQ_TIMER1,IRQ_TIMER2,IRQ_TIMER3,IRQ_CCD_VD0,IRQ_CCD_VD1,
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IRQ_CCD_WEN,IRQ_VENC,IRQ_SERIAL0,IRQ_SERIAL1,IRQ_EXT_HOST,IRQ_DSPHINT,
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IRQ_UART0,IRQ_UART1,IRQ_USB_DMA,IRQ_USB_CORE,IRQ_VLYNQ,IRQ_MTC0,IRQ_MTC1,
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IRQ_SD_MMC,IRQ_SDIO_MS,IRQ_GIO0,IRQ_GIO1,IRQ_GIO2,IRQ_GIO3,IRQ_GIO4,IRQ_GIO5,
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IRQ_GIO6,IRQ_GIO7,IRQ_GIO8,IRQ_GIO9,IRQ_GIO10,IRQ_GIO11,IRQ_GIO12,IRQ_GIO13,
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IRQ_GIO14,IRQ_GIO15,IRQ_PREVIEW0,IRQ_PREVIEW1,IRQ_WATCHDOG,IRQ_I2C,IRQ_CLKC,
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IRQ_ICE,IRQ_ARMCOM_RX,IRQ_ARMCOM_TX,IRQ_RESERVED
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}; /* IRQ priorities, ranging from highest to lowest */
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static void (* const irqvector[])(void) =
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{
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TIMER0,TIMER1,TIMER2,TIMER3,CCD_VD0,CCD_VD1,
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CCD_WEN,VENC,SERIAL0,SERIAL1,EXT_HOST,DSPHINT,
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UART0,UART1,USB_DMA,USB_CORE,VLYNQ,MTC0,MTC1,
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SD_MMC,SDIO_MS,GIO0,GIO1,GIO2,GIO3,GIO4,GIO5,
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GIO6,GIO7,GIO8,GIO9,GIO10,GIO11,GIO12,GIO13,
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GIO14,GIO15,PREVIEW0,PREVIEW1,WATCHDOG,I2C,CLKC,
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ICE,ARMCOM_RX,ARMCOM_TX,RESERVED
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};
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static const char * const irqname[] =
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{
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"TIMER0","TIMER1","TIMER2","TIMER3","CCD_VD0","CCD_VD1",
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"CCD_WEN","VENC","SERIAL0","SERIAL1","EXT_HOST","DSPHINT",
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"UART0","UART1","USB_DMA","USB_CORE","VLYNQ","MTC0","MTC1",
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"SD_MMC","SDIO_MS","GIO0","GIO1","GIO2","GIO3","GIO4","GIO5",
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"GIO6","GIO7","GIO8","GIO9","GIO10","GIO11","GIO12","GIO13",
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"GIO14","GIO15","PREVIEW0","PREVIEW1","WATCHDOG","I2C","CLKC",
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"ICE","ARMCOM_RX","ARMCOM_TX","RESERVED"
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};
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static void UIRQ(void)
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{
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unsigned int offset = (IO_INTC_IRQENTRY0>>2)-1;
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panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
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}
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void irq_handler(void)
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{
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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unsigned short addr = IO_INTC_IRQENTRY0>>2;
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if(addr != 0)
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{
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addr--;
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irqvector[addr]();
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}
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from IRQ */
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}
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void fiq_handler(void)
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{
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile (
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"sub lr, lr, #4 \r\n"
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"stmfd sp!, {r0-r3, ip, lr} \r\n"
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"mov r0, #0x00030000 \r\n"
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"ldr r0, [r0, #0x510] \r\n" /* Fetch value from IO_INTC_FIQENTRY0 */
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"sub r0, r0, #1 \r\n"
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"ldr r1, =irqvector \r\n"
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"ldr r1, [r1, r0, lsl #2] \r\n" /* Divide value by 4 (TBA0/TBA1 is set to 0) and load appropriate pointer from the vector list */
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"blx r1 \r\n" /* Jump to handler */
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"ldmfd sp!, {r0-r3, ip, pc}^ \r\n" /* Return from FIQ */
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);
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}
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void system_reboot(void)
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{
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/* Code taken from linux/include/asm-arm/arch-itdm320-20/system.h at NeuroSVN */
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__asm__ __volatile__(
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"mov ip, #0 \n"
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"mcr p15, 0, ip, c7, c7, 0 @ invalidate cache \n"
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"mcr p15, 0, ip, c7, c10,4 @ drain WB \n"
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"mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) \n"
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"mrc p15, 0, ip, c1, c0, 0 @ get ctrl register\n"
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"bic ip, ip, #0x000f @ ............wcam \n"
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"bic ip, ip, #0x2100 @ ..v....s........ \n"
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"mcr p15, 0, ip, c1, c0, 0 @ ctrl register \n"
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"mov ip, #0xFF000000 \n"
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"orr pc, ip, #0xFF0000 @ ip = 0xFFFF0000 \n"
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:
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:
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: "cc"
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);
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}
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void system_exception_wait(void)
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{
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/* Mask all Interrupts. */
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IO_INTC_EINT0 = 0;
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IO_INTC_EINT1 = 0;
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IO_INTC_EINT2 = 0;
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while ((IO_GIO_BITSET0&0x01) != 0); /* Wait for power button */
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}
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void system_init(void)
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{
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/* taken from linux/arch/arm/mach-itdm320-20/irq.c */
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/* Clearing all FIQs and IRQs. */
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IO_INTC_IRQ0 = 0xFFFF;
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IO_INTC_IRQ1 = 0xFFFF;
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IO_INTC_IRQ2 = 0xFFFF;
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IO_INTC_FIQ0 = 0xFFFF;
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IO_INTC_FIQ1 = 0xFFFF;
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IO_INTC_FIQ2 = 0xFFFF;
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/* Masking all Interrupts. */
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IO_INTC_EINT0 = 0;
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IO_INTC_EINT1 = 0;
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IO_INTC_EINT2 = 0;
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/* Setting INTC to all IRQs. */
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IO_INTC_FISEL0 = 0;
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IO_INTC_FISEL1 = 0;
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IO_INTC_FISEL2 = 0;
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/* setup the clocks */
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IO_CLK_DIV0=0x0003;
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IO_CLK_DIV1=0x0102;
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IO_CLK_DIV2=0x021F;
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IO_CLK_DIV3=0x1FFF;
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IO_CLK_DIV4=0x1F00;
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IO_CLK_PLLA=0x80A0;
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IO_CLK_PLLB=0x80C0;
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IO_CLK_SEL0=0x017E;
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IO_CLK_SEL1=0x1000;
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IO_CLK_SEL2=0x1001;
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/* need to wait before bypassing */
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IO_CLK_BYP=0x0000;
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/* turn off some unneeded modules */
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IO_CLK_MOD0 &= ~0x0018;
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IO_CLK_MOD1 = 0x0918;
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IO_CLK_MOD2 = ~0x7C58;
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/* IRQENTRY only reflects enabled interrupts */
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IO_INTC_RAW = 0;
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IO_INTC_ENTRY_TBA0 = 0;
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IO_INTC_ENTRY_TBA1 = 0;
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int i;
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/* Set interrupt priorities to predefined values */
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for(i = 0; i < 23; i++)
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DM320_REG(0x0540+i*2) = ((irqpriority[i*2+1] & 0x3F) << 8) | (irqpriority[i*2] & 0x3F); /* IO_INTC_PRIORITYx */
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/* Turn off all timers */
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IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP;
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IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP;
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IO_TIMER2_TMMD = CONFIG_TIMER2_TMMD_STOP;
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IO_TIMER3_TMMD = CONFIG_TIMER3_TMMD_STOP;
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#ifndef CREATIVE_ZVx
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/* set GIO26 (reset pin) to output and low */
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IO_GIO_BITCLR1=(1<<10);
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IO_GIO_DIR1&=~(1<<10);
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#endif
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uart_init();
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spi_init();
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#ifdef CREATIVE_ZVx
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dma_init();
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#endif
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/* MMU initialization (Starts data and instruction cache) */
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ttb_init();
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/* Make sure everything is mapped on itself */
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map_section(0, 0, 0x1000, CACHE_NONE);
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/* Enable caching for RAM */
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map_section(CONFIG_SDRAM_START, CONFIG_SDRAM_START, MEM, CACHE_ALL);
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/* enable buffered writing for the framebuffer */
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map_section((int)FRAME, (int)FRAME, 1, BUFFERED);
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#ifdef CREATIVE_ZVx
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/* mimic OF */
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map_section(0x00100000, 0x00100000, 4, CACHE_NONE);
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map_section(0x04700000, 0x04700000, 2, BUFFERED);
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map_section(0x40000000, 0x40000000, 16, CACHE_NONE);
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map_section(0x50000000, 0x50000000, 16, CACHE_NONE);
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map_section(0x60000000, 0x60000000, 16, CACHE_NONE);
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map_section(0x80000000, 0x80000000, 1, CACHE_NONE);
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#endif
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enable_mmu();
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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if (frequency == CPUFREQ_MAX) {
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IO_CLK_DIV0 = 0x0101; /* 175 MHz ARM */
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} else {
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IO_CLK_DIV0 = 0x0003; /* 87.5 MHz ARM - not much savings, about 3 mA */
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}
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}
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#endif
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/* This function is pretty crude. It is not acurate to a usec, but errors on
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* longer.
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*/
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void udelay(int usec) {
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volatile int temp=usec*(175000/200);
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while(temp) {
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temp--;
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}
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}
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