7c007f5d87
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19178 a1c6a512-1295-4272-9138-f99709370657
360 lines
9.1 KiB
C
360 lines
9.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Michael Sevakis
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdlib.h>
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#include "system.h"
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#include "kernel.h"
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#include "audio.h"
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#include "sound.h"
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#include "avic-imx31.h"
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#include "clkctl-imx31.h"
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/* This isn't DMA-based at the moment and is handled like Portal Player but
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* will suffice for starters. */
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struct dma_data
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{
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uint16_t *p;
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size_t size;
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int locked;
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int state;
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};
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static unsigned long pcm_freq; /* 44.1 is default */
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static int sr_ctrl;
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static struct dma_data dma_play_data =
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{
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/* Initialize to a locked, stopped state */
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.p = NULL,
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.size = 0,
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.locked = 0,
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.state = 0
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};
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void pcm_play_lock(void)
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{
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if (++dma_play_data.locked == 1)
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{
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/* Atomically disable transmit interrupt */
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imx31_regmod32(&SSI_SIER1, 0, SSI_SIER_TIE);
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}
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}
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void pcm_play_unlock(void)
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{
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if (--dma_play_data.locked == 0 && dma_play_data.state != 0)
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{
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/* Atomically enable transmit interrupt */
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imx31_regmod32(&SSI_SIER1, SSI_SIER_TIE, SSI_SIER_TIE);
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}
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}
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static void _pcm_apply_settings(void)
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{
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if (pcm_freq != pcm_curr_sampr)
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{
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pcm_curr_sampr = pcm_freq;
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audiohw_set_frequency(sr_ctrl);
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}
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}
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static void __attribute__((interrupt("IRQ"))) SSI1_HANDLER(void)
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{
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register pcm_more_callback_type get_more;
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do
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{
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while (dma_play_data.size > 0)
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{
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if (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 6)
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{
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return;
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}
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SSI_STX0_1 = *dma_play_data.p++;
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SSI_STX0_1 = *dma_play_data.p++;
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dma_play_data.size -= 4;
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}
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/* p is empty, get some more data */
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get_more = pcm_callback_for_more;
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if (get_more)
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{
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get_more((unsigned char **)&dma_play_data.p,
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&dma_play_data.size);
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}
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}
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while (dma_play_data.size > 0);
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/* No more data, so disable the FIFO/interrupt */
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pcm_play_dma_stop();
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pcm_play_dma_stopped_callback();
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}
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void pcm_apply_settings(void)
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{
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pcm_play_lock();
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#ifdef HAVE_RECORDING
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pcm_rec_lock();
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#endif
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_pcm_apply_settings();
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#ifdef HAVE_RECORDING
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pcm_rec_unlock();
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#endif
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pcm_play_unlock();
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}
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void pcm_play_dma_init(void)
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{
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imx31_clkctl_module_clock_gating(CG_SSI1, CGM_ON_ALL);
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imx31_clkctl_module_clock_gating(CG_SSI2, CGM_ON_ALL);
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/* Reset & disable SSIs */
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SSI_SCR2 &= ~SSI_SCR_SSIEN;
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SSI_SCR1 &= ~SSI_SCR_SSIEN;
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SSI_SIER1 = SSI_SIER_TFE0;
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SSI_SIER2 = 0;
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/* Set up audio mux */
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/* Port 1 (internally connected to SSI1)
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* All clocking is output sourced from port 4 */
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AUDMUX_PTCR1 = AUDMUX_PTCR_TFS_DIR | AUDMUX_PTCR_TFSEL_PORT4 |
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AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT4 |
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AUDMUX_PTCR_RFSDIR | AUDMUX_PTCR_RFSSEL_PORT4 |
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AUDMUX_PTCR_RCLKDIR | AUDMUX_PTCR_RCSEL_PORT4 |
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AUDMUX_PTCR_SYN;
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/* Receive data from port 4 */
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AUDMUX_PDCR1 = AUDMUX_PDCR_RXDSEL_PORT4;
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/* All clock lines are inputs sourced from the master mode codec and
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* sent back to SSI1 through port 1 */
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AUDMUX_PTCR4 = AUDMUX_PTCR_SYN;
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/* Receive data from port 1 */
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AUDMUX_PDCR4 = AUDMUX_PDCR_RXDSEL_PORT1;
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/* Port 2 (internally connected to SSI2) routes clocking to port 5 to
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* provide MCLK to the codec */
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/* All port 2 clocks are inputs taken from SSI2 */
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AUDMUX_PTCR2 = 0;
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AUDMUX_PDCR2 = 0;
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/* Port 5 outputs TCLK sourced from port 2 */
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AUDMUX_PTCR5 = AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT2;
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AUDMUX_PDCR5 = 0;
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/* Setup SSIs */
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/* SSI1 - interface for all I2S data */
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SSI_SCR1 = SSI_SCR_SYN | SSI_SCR_I2S_MODE_SLAVE;
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SSI_STCR1 = SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSI |
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SSI_STCR_TEFS | SSI_STCR_TFEN0;
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/* 16 bits per word, 2 words per frame */
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SSI_STCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
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SSI_STRCCR_PMw(4-1);
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SSI_STMSK1 = 0;
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/* Receive */
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SSI_SRCR1 = SSI_SRCR_RXBIT0 | SSI_SRCR_RSCKP | SSI_SRCR_RFSI |
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SSI_SRCR_REFS | SSI_SRCR_RFEN0;
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/* 16 bits per word, 2 words per frame */
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SSI_SRCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
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SSI_STRCCR_PMw(4-1);
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/* Receive high watermark - 6 samples in FIFO
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* Transmit low watermark - 2 samples in FIFO */
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SSI_SFCSR1 = SSI_SFCSR_RFWM1w(8) | SSI_SFCSR_TFWM1w(1) |
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SSI_SFCSR_RFWM0w(6) | SSI_SFCSR_TFWM0w(2);
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SSI_SRMSK1 = 0;
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/* SSI2 - provides MCLK only */
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SSI_SCR2 = 0;
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SSI_SRCR2 = 0;
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SSI_STCR2 = SSI_STCR_TXDIR;
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/* f(INT_BIT_CLK) =
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* f(SYS_CLK) / [(DIV2 + 1)*(7*PSR + 1)*(PM + 1)*2] =
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* 677737600 / [(1 + 1)*(7*0 + 1)*(0 + 1)*2] =
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* 677737600 / 4 = 169344000 Hz
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*
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* 45.4.2.2 DIV2, PSR, and PM Bit Description states:
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* Bits DIV2, PSR, and PM should not be all set to zero at the same
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* time.
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*
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* The hardware seems to force a divide by 4 even if all bits are
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* zero but comply by setting DIV2 and the others to zero.
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*/
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SSI_STCCR2 = SSI_STRCCR_DIV2 | SSI_STRCCR_PMw(1-1);
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/* Enable SSI2 (codec clock) */
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SSI_SCR2 |= SSI_SCR_SSIEN;
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pcm_set_frequency(HW_SAMPR_DEFAULT);
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audiohw_init();
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}
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void pcm_postinit(void)
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{
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audiohw_postinit();
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avic_enable_int(SSI1, IRQ, 8, SSI1_HANDLER);
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}
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static void play_start_pcm(void)
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{
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/* Stop transmission (if in progress) */
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SSI_SCR1 &= ~SSI_SCR_TE;
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/* Apply new settings */
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_pcm_apply_settings();
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/* Enable interrupt on unlock */
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dma_play_data.state = 1;
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/* Fill the FIFO or start when data is used up */
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SSI_SCR1 |= SSI_SCR_SSIEN; /* Enable SSI */
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while (1)
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{
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if (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 6 || dma_play_data.size == 0)
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{
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SSI_SCR1 |= SSI_SCR_TE; /* Start transmitting */
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return;
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}
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SSI_STX0_1 = *dma_play_data.p++;
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SSI_STX0_1 = *dma_play_data.p++;
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dma_play_data.size -= 4;
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}
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}
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static void play_stop_pcm(void)
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{
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/* Disable interrupt */
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SSI_SIER1 &= ~SSI_SIER_TIE;
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/* Wait for FIFO to empty */
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while (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 0);
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/* Disable transmission */
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SSI_SCR1 &= ~(SSI_SCR_TE | SSI_SCR_SSIEN);
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/* Do not enable interrupt on unlock */
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dma_play_data.state = 0;
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}
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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dma_play_data.p = (void *)(((uintptr_t)addr + 3) & ~3);
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dma_play_data.size = (size & ~3);
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play_start_pcm();
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}
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void pcm_play_dma_stop(void)
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{
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play_stop_pcm();
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dma_play_data.size = 0;
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}
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void pcm_play_dma_pause(bool pause)
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{
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if (pause)
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{
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play_stop_pcm();
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}
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else
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{
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uint32_t addr = (uint32_t)dma_play_data.p;
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dma_play_data.p = (void *)((addr + 2) & ~3);
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dma_play_data.size &= ~3;
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play_start_pcm();
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}
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}
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/* Set the pcm frequency hardware will use when play is next started or
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when pcm_apply_settings is called. Do not apply the setting to the
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hardware here but simply cache it. */
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void pcm_set_frequency(unsigned int frequency)
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{
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int index;
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switch (frequency)
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{
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case SAMPR_48:
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index = HW_FREQ_48;
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break;
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case SAMPR_44:
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index = HW_FREQ_44;
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break;
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case SAMPR_32:
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index = HW_FREQ_32;
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break;
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case SAMPR_24:
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index = HW_FREQ_24;
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break;
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case SAMPR_22:
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index = HW_FREQ_22;
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break;
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case SAMPR_16:
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index = HW_FREQ_16;
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break;
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case SAMPR_12:
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index = HW_FREQ_12;
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break;
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case SAMPR_11:
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index = HW_FREQ_11;
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break;
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case SAMPR_8:
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index = HW_FREQ_8;
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break;
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default:
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/* Invalid = default */
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frequency = HW_SAMPR_DEFAULT;
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index = HW_FREQ_DEFAULT;
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}
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pcm_freq = frequency;
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sr_ctrl = index;
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}
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/* Return the number of bytes waiting - full L-R sample pairs only */
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size_t pcm_get_bytes_waiting(void)
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{
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return dma_play_data.size & ~3;
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}
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/* Return a pointer to the samples and the number of them in *count */
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const void * pcm_play_dma_get_peak_buffer(int *count)
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{
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uint32_t addr = (uint32_t)dma_play_data.p;
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size_t cnt = dma_play_data.size;
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*count = cnt >> 2;
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return (void *)((addr + 2) & ~3);
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}
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/* Any recording functionality should be implemented similarly */
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