405 lines
13 KiB
C
405 lines
13 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "kernel.h"
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#include "ssp-imx233.h"
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#include "clkctrl-imx233.h"
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#include "pinctrl-imx233.h"
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#include "dma-imx233.h"
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/* for debug purpose */
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#if 0
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#define ASSERT_SSP(ssp) if(ssp < 1 || ssp > 2) panicf("ssp=%d in %s", ssp, __func__);
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#else
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#define ASSERT_SSP(ssp)
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#endif
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/* Used for DMA */
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struct ssp_dma_command_t
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{
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struct apb_dma_command_t dma;
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/* PIO words */
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uint32_t ctrl0;
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uint32_t cmd0;
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uint32_t cmd1;
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/* padded to next multiple of cache line size (32 bytes) */
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uint32_t pad[2];
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} __attribute__((packed)) CACHEALIGN_ATTR;
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__ENSURE_STRUCT_CACHE_FRIENDLY(struct ssp_dma_command_t)
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static bool ssp_in_use[2];
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static int ssp_nr_in_use = 0;
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static struct mutex ssp_mutex[2];
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static struct semaphore ssp_sema[2];
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static struct ssp_dma_command_t ssp_dma_cmd[2];
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static uint32_t ssp_bus_width[2];
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static unsigned ssp_log_block_size[2];
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static ssp_detect_cb_t ssp_detect_cb[2];
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static bool ssp_detect_invert[2];
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void INT_SSP(int ssp)
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{
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/* reset dma channel on error */
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if(imx233_dma_is_channel_error_irq(APB_SSP(ssp)))
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imx233_dma_reset_channel(APB_SSP(ssp));
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/* clear irq flags */
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imx233_dma_clear_channel_interrupt(APB_SSP(ssp));
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semaphore_release(&ssp_sema[ssp - 1]);
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}
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void INT_SSP1_DMA(void)
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{
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INT_SSP(1);
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}
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void INT_SSP2_DMA(void)
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{
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INT_SSP(2);
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}
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void INT_SSP1_ERROR(void)
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{
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panicf("ssp1 error");
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}
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void INT_SSP2_ERROR(void)
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{
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panicf("ssp2 error");
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}
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void imx233_ssp_init(void)
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{
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/* power down */
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__REG_SET(HW_SSP_CTRL0(1)) = __BLOCK_CLKGATE;
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__REG_SET(HW_SSP_CTRL0(2)) = __BLOCK_CLKGATE;
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ssp_nr_in_use = 0;
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semaphore_init(&ssp_sema[0], 1, 0);
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semaphore_init(&ssp_sema[1], 1, 0);
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mutex_init(&ssp_mutex[0]);
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mutex_init(&ssp_mutex[1]);
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ssp_bus_width[0] = ssp_bus_width[1] = HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT;
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}
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void imx233_ssp_start(int ssp)
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{
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ASSERT_SSP(ssp)
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if(ssp_in_use[ssp - 1])
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return;
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ssp_in_use[ssp - 1] = true;
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/* Gate block */
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imx233_reset_block(&HW_SSP_CTRL0(ssp));
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/* Gate dma channel */
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imx233_dma_clkgate_channel(APB_SSP(ssp), true);
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/* If first block to start, start SSP clock */
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if(ssp_nr_in_use == 0)
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{
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/** 2.3.1: the clk_ssp maximum frequency is 102.858 MHz */
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/* fracdiv = 18 => clk_io = pll = 480Mhz
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* intdiv = 5 => clk_ssp = 96Mhz */
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imx233_clkctrl_set_fractional_divisor(CLK_IO, 18);
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imx233_clkctrl_enable_clock(CLK_SSP, false);
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imx233_clkctrl_set_clock_divisor(CLK_SSP, 5);
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imx233_clkctrl_set_bypass_pll(CLK_SSP, false); /* use IO */
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imx233_clkctrl_enable_clock(CLK_SSP, true);
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}
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ssp_nr_in_use++;
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}
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void imx233_ssp_stop(int ssp)
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{
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ASSERT_SSP(ssp)
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if(!ssp_in_use[ssp - 1])
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return;
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ssp_in_use[ssp - 1] = false;
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/* Gate off */
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__REG_SET(HW_SSP_CTRL0(ssp)) = __BLOCK_CLKGATE;
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/* Gate off dma */
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imx233_dma_clkgate_channel(APB_SSP(ssp), false);
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/* If last block to stop, stop SSP clock */
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ssp_nr_in_use--;
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if(ssp_nr_in_use == 0)
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{
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imx233_clkctrl_enable_clock(CLK_SSP, false);
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imx233_clkctrl_set_fractional_divisor(CLK_IO, 0);
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}
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}
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void imx233_ssp_softreset(int ssp)
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{
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ASSERT_SSP(ssp)
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imx233_reset_block(&HW_SSP_CTRL0(ssp));
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}
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void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout)
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{
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ASSERT_SSP(ssp)
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HW_SSP_TIMING(ssp) = divide << HW_SSP_TIMING__CLOCK_DIVIDE_BP | rate |
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timeout << HW_SSP_TIMING__CLOCK_TIMEOUT_BP;
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}
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void imx233_ssp_setup_ssp1_sd_mmc_pins(bool enable_pullups, unsigned bus_width,
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unsigned drive_strength, bool use_alt)
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{
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/* SSP_{CMD,SCK} */
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imx233_set_pin_drive_strength(2, 0, drive_strength);
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imx233_set_pin_drive_strength(2, 6, drive_strength);
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imx233_pinctrl_acquire_pin(2, 0, "ssp1 cmd");
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imx233_pinctrl_acquire_pin(2, 6, "ssp1 sck");
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imx233_set_pin_function(2, 0, PINCTRL_FUNCTION_MAIN);
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imx233_set_pin_function(2, 6, PINCTRL_FUNCTION_MAIN);
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imx233_enable_pin_pullup(2, 0, enable_pullups);
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/* SSP_DATA{0-3} */
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for(unsigned i = 0; i < MIN(bus_width, 4); i++)
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{
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imx233_pinctrl_acquire_pin(2, 2 + i, "ssp1 data");
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imx233_set_pin_drive_strength(2, 2 + i, drive_strength);
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imx233_set_pin_function(2, 2 + i, PINCTRL_FUNCTION_MAIN);
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imx233_enable_pin_pullup(2, 2 + i, enable_pullups);
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}
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/* SSP_DATA{4-7} */
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for(unsigned i = 4; i < bus_width; i++)
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{
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if(use_alt)
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{
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imx233_pinctrl_acquire_pin(0, 22 + i, "ssp1 data");
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imx233_set_pin_drive_strength(0, 22 + i, drive_strength);
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imx233_set_pin_function(0, 22 + i, PINCTRL_FUNCTION_ALT2);
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imx233_enable_pin_pullup(0, 22 + i, enable_pullups);
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}
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else
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{
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imx233_pinctrl_acquire_pin(0, 4 + i, "ssp1 data");
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imx233_set_pin_drive_strength(0, 4 + i, drive_strength);
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imx233_set_pin_function(0, 4 + i, PINCTRL_FUNCTION_ALT2);
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imx233_enable_pin_pullup(0, 4 + i, enable_pullups);
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}
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}
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}
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void imx233_ssp_setup_ssp2_sd_mmc_pins(bool enable_pullups, unsigned bus_width,
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unsigned drive_strength)
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{
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/* SSP_{CMD,SCK} */
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imx233_pinctrl_acquire_pin(0, 20, "ssp2 cmd");
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imx233_pinctrl_acquire_pin(0, 24, "ssp2 sck");
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imx233_set_pin_drive_strength(0, 20, drive_strength);
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imx233_set_pin_drive_strength(0, 24, drive_strength);
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imx233_set_pin_function(0, 20, PINCTRL_FUNCTION_ALT2);
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imx233_set_pin_function(0, 24, PINCTRL_FUNCTION_ALT2);
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imx233_enable_pin_pullup(0, 20, enable_pullups);
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/* SSP_DATA{0-7}*/
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for(unsigned i = 0; i < bus_width; i++)
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{
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imx233_pinctrl_acquire_pin(0, i, "ssp2 data");
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imx233_set_pin_drive_strength(0, i, drive_strength);
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imx233_set_pin_function(0, i, PINCTRL_FUNCTION_ALT2);
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imx233_enable_pin_pullup(0, i, enable_pullups);
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imx233_enable_gpio_output(0, i, false);
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imx233_set_gpio_output(0, i, false);
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}
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}
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void imx233_ssp_set_mode(int ssp, unsigned mode)
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{
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ASSERT_SSP(ssp)
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switch(mode)
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{
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case HW_SSP_CTRL1__SSP_MODE__SD_MMC:
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/* clear mode and word length */
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__REG_CLR(HW_SSP_CTRL1(ssp)) =
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HW_SSP_CTRL1__SSP_MODE_BM | HW_SSP_CTRL1__WORD_LENGTH_BM;
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/* set mode, set word length to 8-bit, polarity and enable dma */
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__REG_SET(HW_SSP_CTRL1(ssp)) = mode |
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HW_SSP_CTRL1__WORD_LENGTH__EIGHT_BITS << HW_SSP_CTRL1__WORD_LENGTH_BP |
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HW_SSP_CTRL1__POLARITY | HW_SSP_CTRL1__DMA_ENABLE;
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break;
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default: return;
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}
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}
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void imx233_ssp_set_bus_width(int ssp, unsigned width)
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{
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ASSERT_SSP(ssp)
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switch(width)
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{
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case 1: ssp_bus_width[ssp - 1] = HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT; break;
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case 4: ssp_bus_width[ssp - 1] = HW_SSP_CTRL0__BUS_WIDTH__FOUR_BIT; break;
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case 8: ssp_bus_width[ssp - 1] = HW_SSP_CTRL0__BUS_WIDTH__EIGHT_BIT; break;
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}
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}
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void imx233_ssp_set_block_size(int ssp, unsigned log_block_size)
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{
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ASSERT_SSP(ssp)
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ssp_log_block_size[ssp - 1] = log_block_size;
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}
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enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
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uint32_t cmd_arg, enum imx233_ssp_resp_t resp, void *buffer, unsigned block_count,
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bool wait4irq, bool read, uint32_t *resp_ptr)
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{
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ASSERT_SSP(ssp)
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mutex_lock(&ssp_mutex[ssp - 1]);
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/* Enable all interrupts */
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imx233_icoll_enable_interrupt(INT_SRC_SSP_DMA(ssp), true);
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imx233_dma_enable_channel_interrupt(APB_SSP(ssp), true);
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unsigned xfer_size = block_count * (1 << ssp_log_block_size[ssp - 1]);
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ssp_dma_cmd[ssp - 1].cmd0 = cmd | HW_SSP_CMD0__APPEND_8CYC |
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ssp_log_block_size[ssp - 1] << HW_SSP_CMD0__BLOCK_SIZE_BP |
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(block_count - 1) << HW_SSP_CMD0__BLOCK_COUNT_BP;
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ssp_dma_cmd[ssp - 1].cmd1 = cmd_arg;
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/* setup all flags and run */
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ssp_dma_cmd[ssp - 1].ctrl0 = xfer_size | HW_SSP_CTRL0__ENABLE |
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(buffer ? 0 : HW_SSP_CTRL0__IGNORE_CRC) |
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(wait4irq ? HW_SSP_CTRL0__WAIT_FOR_IRQ : 0) |
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(resp != SSP_NO_RESP ? HW_SSP_CTRL0__GET_RESP : 0) |
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(resp == SSP_LONG_RESP ? HW_SSP_CTRL0__LONG_RESP : 0) |
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(ssp_bus_width[ssp - 1] << HW_SSP_CTRL0__BUS_WIDTH_BP) |
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(buffer ? HW_SSP_CTRL0__DATA_XFER : 0) |
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(read ? HW_SSP_CTRL0__READ : 0);
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/* setup the dma parameters */
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ssp_dma_cmd[ssp - 1].dma.buffer = buffer;
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ssp_dma_cmd[ssp - 1].dma.next = NULL;
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ssp_dma_cmd[ssp - 1].dma.cmd =
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(buffer == NULL ? HW_APB_CHx_CMD__COMMAND__NO_XFER :
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read ? HW_APB_CHx_CMD__COMMAND__WRITE : HW_APB_CHx_CMD__COMMAND__READ) |
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HW_APB_CHx_CMD__IRQONCMPLT | HW_APB_CHx_CMD__SEMAPHORE |
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HW_APB_CHx_CMD__WAIT4ENDCMD |
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(3 << HW_APB_CHx_CMD__CMDWORDS_BP) |
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(xfer_size << HW_APB_CHx_CMD__XFER_COUNT_BP);
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__REG_CLR(HW_SSP_CTRL1(ssp)) = HW_SSP_CTRL1__ALL_IRQ;
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imx233_dma_reset_channel(APB_SSP(ssp));
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imx233_dma_start_command(APB_SSP(ssp), &ssp_dma_cmd[ssp - 1].dma);
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/* the SSP hardware already has a timeout but we never know; 1 sec is a maximum
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* for all operations */
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enum imx233_ssp_error_t ret;
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if(semaphore_wait(&ssp_sema[ssp - 1], HZ) == OBJ_WAIT_TIMEDOUT)
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{
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imx233_dma_reset_channel(APB_SSP(ssp));
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ret = SSP_TIMEOUT;
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}
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else if((HW_SSP_CTRL1(ssp) & HW_SSP_CTRL1__ALL_IRQ) == 0)
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ret = SSP_SUCCESS;
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else if(HW_SSP_CTRL1(ssp) & (HW_SSP_CTRL1__RESP_TIMEOUT_IRQ |
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HW_SSP_CTRL1__DATA_TIMEOUT_IRQ | HW_SSP_CTRL1__RECV_TIMEOUT_IRQ))
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ret = SSP_TIMEOUT;
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else
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ret = SSP_ERROR;
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if(resp_ptr != NULL)
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{
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if(resp != SSP_NO_RESP)
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*resp_ptr++ = HW_SSP_SDRESP0(ssp);
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if(resp == SSP_LONG_RESP)
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{
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*resp_ptr++ = HW_SSP_SDRESP1(ssp);
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*resp_ptr++ = HW_SSP_SDRESP2(ssp);
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*resp_ptr++ = HW_SSP_SDRESP3(ssp);
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}
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}
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mutex_unlock(&ssp_mutex[ssp - 1]);
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return ret;
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}
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void imx233_ssp_sd_mmc_power_up_sequence(int ssp)
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{
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ASSERT_SSP(ssp)
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__REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__SLOW_CLKING_EN;
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__REG_SET(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN;
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mdelay(1);
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__REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN;
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}
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static int ssp_detect_oneshot_callback(int ssp)
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{
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ASSERT_SSP(ssp)
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if(ssp_detect_cb[ssp - 1])
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ssp_detect_cb[ssp - 1](ssp);
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return 0;
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}
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static int ssp1_detect_oneshot_callback(struct timeout *tmo)
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{
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(void) tmo;
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return ssp_detect_oneshot_callback(1);
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}
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static int ssp2_detect_oneshot_callback(struct timeout *tmo)
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{
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(void) tmo;
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return ssp_detect_oneshot_callback(2);
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}
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static void detect_irq(int bank, int pin)
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{
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static struct timeout ssp1_detect_oneshot;
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static struct timeout ssp2_detect_oneshot;
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if(bank == 2 && pin == 1)
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timeout_register(&ssp1_detect_oneshot, ssp1_detect_oneshot_callback, (3*HZ/10), 0);
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else if(bank == 0 && pin == 19)
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timeout_register(&ssp2_detect_oneshot, ssp2_detect_oneshot_callback, (3*HZ/10), 0);
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}
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void imx233_ssp_sdmmc_setup_detect(int ssp, bool enable, ssp_detect_cb_t fn,
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bool first_time, bool invert)
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{
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ASSERT_SSP(ssp)
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int bank = ssp == 1 ? 2 : 0;
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int pin = ssp == 1 ? 1 : 19;
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ssp_detect_cb[ssp - 1] = fn;
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ssp_detect_invert[ssp - 1] = invert;
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if(enable)
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{
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imx233_pinctrl_acquire_pin(bank, pin, ssp == 1 ? "ssp1 detect" : "ssp2 detect");
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imx233_set_pin_function(bank, pin, PINCTRL_FUNCTION_GPIO);
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imx233_enable_gpio_output(bank, pin, false);
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}
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if(first_time && imx233_ssp_sdmmc_detect(ssp))
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detect_irq(bank, pin);
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imx233_setup_pin_irq(bank, pin, enable, true, !imx233_ssp_sdmmc_detect_raw(ssp), detect_irq);
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}
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bool imx233_ssp_sdmmc_is_detect_inverted(int ssp)
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{
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ASSERT_SSP(ssp)
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return ssp_detect_invert[ssp - 1];
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}
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bool imx233_ssp_sdmmc_detect_raw(int ssp)
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{
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ASSERT_SSP(ssp)
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return !!(HW_SSP_STATUS(ssp) & HW_SSP_STATUS__CARD_DETECT);
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}
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bool imx233_ssp_sdmmc_detect(int ssp)
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{
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ASSERT_SSP(ssp)
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return imx233_ssp_sdmmc_detect_raw(ssp) != ssp_detect_invert[ssp - 1];
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}
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