0946a1e0f2
When chaging the cpu and memory frequency we need to disable the external memory interface (EMI) for a small time. This can underflow the dma and cause some breakage. Hopefully the SSP controller handles this gracefully by stopping the clock and the I2C probably handles this naturally because the clock can be streched anyway. However the LCDIF has a special setting for this which needs to be enable, otherwise it will send garbage to the LCD. No other block is known to suffer from this currently but this issue might have more unexpected consequences. Change-Id: Ide154cad87929f2bf6cc419ac1d2ff33e30eec66
103 lines
4.9 KiB
C
103 lines
4.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (c) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __LCDIF_IMX233_H__
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#define __LCDIF_IMX233_H__
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#include <string.h>
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#include "cpu.h"
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#include "system.h"
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#include "system-target.h"
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#define HW_LCDIF_BASE 0x80030000
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#define HW_LCDIF_CTRL (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x0))
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#define HW_LCDIF_CTRL__WORD_LENGTH_16_BIT (0 << 8)
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#define HW_LCDIF_CTRL__WORD_LENGTH_8_BIT (1 << 8)
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#define HW_LCDIF_CTRL__WORD_LENGTH_18_BIT (2 << 8)
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#define HW_LCDIF_CTRL__WORD_LENGTH_24_BIT (3 << 8)
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#define HW_LCDIF_CTRL__WORD_LENGTH_BM (3 << 8)
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#define HW_LCDIF_CTRL__LCD_DATABUS_WIDTH_16_BIT (0 << 10)
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#define HW_LCDIF_CTRL__LCD_DATABUS_WIDTH_18_BIT (2 << 10)
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#define HW_LCDIF_CTRL__LCD_DATABUS_WIDTH_BM (3 << 10)
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#define HW_LCDIF_CTRL__LCDIF_MASTER (1 << 5)
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#define HW_LCDIF_CTRL__DATA_FORMAT_16_BIT (1 << 3)
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#define HW_LCDIF_CTRL__DATA_FORMAT_18_BIT (1 << 2)
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#define HW_LCDIF_CTRL__DATA_FORMAT_24_BIT (1 << 1)
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#define HW_LCDIF_CTRL__RUN 0x1
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#define HW_LCDIF_CTRL__DATA_SELECT (1 << 16)
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#define HW_LCDIF_CTRL1 (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x10))
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#define HW_LCDIF_CTRL1__RESET 1
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#define HW_LCDIF_CTRL1__BUSY_ENABLE (1 << 2)
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#define HW_LCDIF_CTRL1__MODE86 (1 << 1)
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#define HW_LCDIF_CTRL1__IRQ_EN_BP 12
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#define HW_LCDIF_CTRL1__IRQ_EN_BM (0xf << 12)
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#define HW_LCDIF_CTRL1__IRQ_BP 8
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#define HW_LCDIF_CTRL1__BYTE_PACKING_FORMAT_BM (0xf << 16)
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#define HW_LCDIF_CTRL1__BYTE_PACKING_FORMAT_BP 16
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#define HW_LCDIF_CTRL1__RECOVER_ON_UNDERFLOW (1 << 24)
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#define HW_LCDIF__VSYNC_EDGE_IRQ 1
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#define HW_LCDIF__CUR_FRAME_DONE_IRQ 2
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#define HW_LCDIF__UNDERFLOW_IRQ 4
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#define HW_LCDIF__OVERFLOW_IRQ 8
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#define HW_LCDIF_TRANSFER_COUNT (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x20))
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#define HW_LCDIF_CUR_BUF (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x30))
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#define HW_LCDIF_NEXT_BUF (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x40))
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#define HW_LCDIF_TIMING (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x60))
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#define HW_LCDIF_TIMING__DATA_SETUP_BP 0
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#define HW_LCDIF_TIMING__DATA_HOLD_BP 8
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#define HW_LCDIF_TIMING__CMD_SETUP_BP 16
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#define HW_LCDIF_TIMING__CMD_HOLD_BP 24
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#define HW_LCDIF_CSC_COEFF0 (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x110))
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#define HW_LCDIF_CSC_COEFF1 (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x120))
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#define HW_LCDIF_CSC_COEFF2 (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x130))
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#define HW_LCDIF_CSC_COEFF3 (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x140))
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#define HW_LCDIF_CSC_COEFF4 (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x150))
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#define HW_LCDIF_CSC_OFFSET (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x160))
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#define HW_LCDIF_CSC_LIMIT (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x170))
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#define HW_LCDIF_DATA (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x1b0))
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#define HW_LCDIF_STAT (*(volatile uint32_t *)(HW_LCDIF_BASE + 0x1d0))
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#define HW_LCDIF_STAT__LFIFO_FULL (1 << 29)
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#define HW_LCDIF_STAT__LFIFO_EMPTY (1 << 28)
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#define HW_LCDIF_STAT__TXFIFO_FULL (1 << 27)
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#define HW_LCDIF_STAT__TXFIFO_EMPTY (1 << 26)
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#define HW_LCDIF_STAT__BUSY (1 << 25)
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void imx233_lcdif_enable_underflow_recover(bool enable);
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void imx233_lcdif_enable_bus_master(bool enable);
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void imx233_lcdif_enable(bool enable);
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void imx233_lcdif_reset(void);// reset lcdif block
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void imx233_lcdif_set_timings(unsigned data_setup, unsigned data_hold,
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unsigned cmd_setup, unsigned cmd_hold);
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void imx233_lcdif_set_lcd_databus_width(unsigned width);
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void imx233_lcdif_set_word_length(unsigned word_length);
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void imx233_lcdif_set_byte_packing_format(unsigned byte_packing);
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void imx233_lcdif_set_data_format(bool data_fmt_16, bool data_fmt_18, bool data_fmt_24);
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unsigned imx233_lcdif_enable_irqs(unsigned irq_bm); /* return old mask */
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void imx233_lcdif_wait_ready(void);
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void imx233_lcdif_pio_send(bool data_mode, unsigned len, uint32_t *buf);
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void imx233_lcdif_dma_send(void *buf, unsigned width, unsigned height);
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#endif /* __LCDIF_IMX233_H__ */
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