9ced006c06
The icoll code now has an IRQ storm detection mechanism which will prevent the device from hard freezing in case it happen. Change-Id: I9861238dce61d29af1e48f9c534ec63a7f23465c
81 lines
2.8 KiB
C
81 lines
2.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2012 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef ICOLL_IMX233_H
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#define ICOLL_IMX233_H
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#include "config.h"
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#include "system.h"
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/* Interrupt collector */
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#define HW_ICOLL_BASE 0x80000000
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#define HW_ICOLL_VECTOR (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x0))
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#define HW_ICOLL_LEVELACK (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x10))
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#define HW_ICOLL_LEVELACK__LEVEL0 0x1
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#define HW_ICOLL_CTRL (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x20))
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#define HW_ICOLL_CTRL__IRQ_FINAL_ENABLE (1 << 16)
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#define HW_ICOLL_CTRL__ARM_RSE_MODE (1 << 18)
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#define HW_ICOLL_VBASE (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x40))
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#define HW_ICOLL_INTERRUPT(i) (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x120 + (i) * 0x10))
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#define HW_ICOLL_INTERRUPT__PRIORITY_BM 0x3
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#define HW_ICOLL_INTERRUPT__ENABLE 0x4
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#define HW_ICOLL_INTERRUPT__SOFTIRQ 0x8
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#define HW_ICOLL_INTERRUPT__ENFIQ 0x10
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#define INT_SRC_SSP2_ERROR 2
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#define INT_SRC_VDD5V 3
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#define INT_SRC_DAC_DMA 5
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#define INT_SRC_DAC_ERROR 6
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#define INT_SRC_ADC_DMA 7
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#define INT_SRC_ADC_ERROR 8
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#define INT_SRC_USB_CTRL 11
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#define INT_SRC_SSP1_DMA 14
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#define INT_SRC_SSP1_ERROR 15
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#define INT_SRC_GPIO0 16
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#define INT_SRC_GPIO1 17
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#define INT_SRC_GPIO2 18
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#define INT_SRC_GPIO(i) (INT_SRC_GPIO0 + (i))
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#define INT_SRC_SSP2_DMA 20
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#define INT_SRC_I2C_DMA 26
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#define INT_SRC_I2C_ERROR 27
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#define INT_SRC_TIMER(nr) (28 + (nr))
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#define INT_SRC_TOUCH_DETECT 36
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#define INT_SRC_LRADC_CHx(x) (37 + (x))
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#define INT_SRC_LCDIF_DMA 45
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#define INT_SRC_LCDIF_ERROR 46
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#define INT_SRC_RTC_1MSEC 48
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#define INT_SRC_DCP 54
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#define INT_SRC_NR_SOURCES 66
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struct imx233_icoll_irq_info_t
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{
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bool enabled;
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unsigned freq;
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};
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void imx233_icoll_init(void);
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void imx233_icoll_enable_interrupt(int src, bool enable);
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struct imx233_icoll_irq_info_t imx233_icoll_get_irq_info(int src);
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#endif /* ICOLL_IMX233_H */
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