286 lines
8.6 KiB
C
286 lines
8.6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021-2022 Aidan MacDonald
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* Copyright 2014 Ingenic Semiconductor Co.,Ltd
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* cscheng <shicheng.cheng@ingenic.com>
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* sound/soc/ingenic/icodec/icdc_d3.c
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* ALSA SoC Audio driver -- ingenic internal codec (icdc_d3) driver
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "x1000-codec.h"
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#include "audiohw.h"
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#include "pcm_sampr.h"
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#include "kernel.h"
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#include "x1000/aic.h"
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static const uint8_t fsel_to_hw[HW_NUM_FREQ] = {
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[0 ... HW_NUM_FREQ-1] = 0,
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HW_HAVE_8_([HW_FREQ_8] = 0,)
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HW_HAVE_11_([HW_FREQ_11] = 1,)
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HW_HAVE_12_([HW_FREQ_12] = 2,)
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HW_HAVE_16_([HW_FREQ_16] = 3,)
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HW_HAVE_22_([HW_FREQ_22] = 4,)
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HW_HAVE_24_([HW_FREQ_24] = 5,)
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HW_HAVE_32_([HW_FREQ_32] = 6,)
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HW_HAVE_44_([HW_FREQ_44] = 7,)
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HW_HAVE_48_([HW_FREQ_48] = 8,)
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HW_HAVE_88_([HW_FREQ_88] = 9,)
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HW_HAVE_96_([HW_FREQ_96] = 10,)
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HW_HAVE_176_([HW_FREQ_176] = 11,)
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HW_HAVE_192_([HW_FREQ_192] = 12,)
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};
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void x1000_icodec_open(void)
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{
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/* Ingenic does not specify any timing constraints for reset,
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* let's do a 1ms delay for fun */
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jz_writef(AIC_RGADW, ICRST(1));
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mdelay(1);
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jz_writef(AIC_RGADW, ICRST(0));
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/* Power-up and initial config sequence */
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static const uint8_t init_config[] = {
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JZCODEC_CR_VIC, 0x03, /* ensure codec is powered off */
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JZCODEC_CR_CK, 0x40, /* MCLK_DIV=1, SHUTDOWN_CLK=0, CRYSTAL=12Mhz */
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JZCODEC_AICR_DAC, 0x13, /* ADWL=0 (16bit word length)
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* SLAVE=0 (i2s master mode)
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* SB_DAC=1 (power down DAC)
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* AUDIOIF=3 (i2s mode) */
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JZCODEC_AICR_ADC, 0x13, /* ADWL=0 (16bit word length)
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* SB_ADC=1 (power down ADC)
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* AUDIOIF=3 (i2s mode)
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*/
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JZCODEC_CR_DAC, 0x91, /* DAC mute, power down */
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JZCODEC_CR_DAC2, 0x38, /* DAC power down */
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JZCODEC_CR_DMIC, 0x00, /* DMIC clock off */
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JZCODEC_CR_MIC1, 0x30, /* MIC1 power down */
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JZCODEC_CR_MIC2, 0x30, /* MIC2 power down */
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JZCODEC_CR_ADC, 0x90, /* ADC mute, power down */
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JZCODEC_ICR, 0x00, /* INT_FORM=0 (high level IRQ) */
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JZCODEC_IMR, 0xff, /* Mask all interrupts */
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JZCODEC_IMR2, 0xff,
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JZCODEC_IFR, 0xff, /* Clear all interrupt flags */
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JZCODEC_IFR2, 0xff,
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};
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for(size_t i = 0; i < ARRAYLEN(init_config); i += 2)
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x1000_icodec_write(init_config[i], init_config[i+1]);
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/* SB -> 0 (power up) */
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x1000_icodec_write(JZCODEC_CR_VIC, 0x02);
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mdelay(250);
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/* Initial gain setting. Apparently we need to set one gain and
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* then set another after 10ms; afterward it can be changed freely. */
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static const uint8_t gain_regs[] = {
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JZCODEC_GCR_DACL,
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JZCODEC_GCR_DACR,
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JZCODEC_GCR_DACL2,
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JZCODEC_GCR_DACR2,
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JZCODEC_GCR_MIC1,
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JZCODEC_GCR_MIC2,
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JZCODEC_GCR_ADCL,
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JZCODEC_GCR_ADCR,
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};
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for(size_t i = 0; i < ARRAYLEN(gain_regs); ++i)
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x1000_icodec_write(gain_regs[i], 0);
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mdelay(10);
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for(size_t i = 0; i < ARRAYLEN(gain_regs); ++i)
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x1000_icodec_write(gain_regs[i], 1);
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/* SB_SLEEP -> 0 (exit sleep/standby mode) */
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x1000_icodec_write(JZCODEC_CR_VIC, 0x00);
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mdelay(200);
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}
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void x1000_icodec_close(void)
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{
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/* SB_SLEEP -> 1 (enable sleep mode) */
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x1000_icodec_write(JZCODEC_CR_VIC, 0x02);
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/* SB -> 1 (power down) */
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x1000_icodec_write(JZCODEC_CR_VIC, 0x03);
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}
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/*
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* DAC configuration
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*/
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void x1000_icodec_dac_frequency(int fsel)
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{
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x1000_icodec_update(JZCODEC_FCR_DAC, 0x0f, fsel_to_hw[fsel]);
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}
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/*
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* ADC configuration
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*/
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void x1000_icodec_adc_enable(bool en)
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{
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x1000_icodec_update(JZCODEC_AICR_ADC, 0x10, en ? 0x00 : 0x10);
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x1000_icodec_update(JZCODEC_CR_ADC, 0x10, en ? 0x00 : 0x10);
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}
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void x1000_icodec_adc_mute(bool muted)
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{
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x1000_icodec_update(JZCODEC_CR_ADC, 0x80, muted ? 0x80 : 0x00);
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}
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void x1000_icodec_adc_mic_sel(int sel)
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{
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x1000_icodec_update(JZCODEC_CR_ADC, 0x40,
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sel == JZCODEC_MIC_SEL_DIGITAL ? 0x40 : 0x00);
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}
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void x1000_icodec_adc_frequency(int fsel)
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{
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x1000_icodec_update(JZCODEC_FCR_ADC, 0x0f, fsel_to_hw[fsel]);
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}
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void x1000_icodec_adc_highpass_filter(bool en)
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{
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x1000_icodec_update(JZCODEC_FCR_ADC, 0x40, en ? 0x40 : 0x00);
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}
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void x1000_icodec_adc_gain(int gain_dB)
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{
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if(gain_dB < X1000_ICODEC_ADC_GAIN_MIN)
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gain_dB = X1000_ICODEC_ADC_GAIN_MIN;
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else if(gain_dB > X1000_ICODEC_ADC_GAIN_MAX)
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gain_dB = X1000_ICODEC_ADC_GAIN_MAX;
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/* bit 7 = use the same gain for both channels */
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x1000_icodec_write(JZCODEC_GCR_ADCL, 0x80 | gain_dB);
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}
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/*
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* MIC1 configuration
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*/
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void x1000_icodec_mic1_enable(bool en)
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{
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x1000_icodec_update(JZCODEC_CR_MIC1, 0x10, en ? 0x00 : 0x10);
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}
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void x1000_icodec_mic1_bias_enable(bool en)
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{
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x1000_icodec_update(JZCODEC_CR_MIC1, 0x20, en ? 0x00 : 0x20);
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}
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void x1000_icodec_mic1_configure(int settings)
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{
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x1000_icodec_update(JZCODEC_CR_MIC1, JZCODEC_MIC1_CONFIGURE_MASK,
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settings & JZCODEC_MIC1_CONFIGURE_MASK);
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}
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void x1000_icodec_mic1_gain(int gain_dB)
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{
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if(gain_dB < X1000_ICODEC_MIC_GAIN_MIN)
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gain_dB = X1000_ICODEC_MIC_GAIN_MIN;
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else if(gain_dB > X1000_ICODEC_MIC_GAIN_MAX)
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gain_dB = X1000_ICODEC_MIC_GAIN_MAX;
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x1000_icodec_write(JZCODEC_GCR_MIC1, gain_dB/X1000_ICODEC_MIC_GAIN_STEP);
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}
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/*
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* Mixer configuration
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*/
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void x1000_icodec_mixer_enable(bool en)
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{
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x1000_icodec_update(JZCODEC_CR_MIX, 0x80, en ? 0x80 : 0x00);
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}
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/*
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* Register access
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*/
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static int x1000_icodec_read_direct(int reg)
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{
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jz_writef(AIC_RGADW, ADDR(reg));
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return jz_readf(AIC_RGDATA, DATA);
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}
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static void x1000_icodec_write_direct(int reg, int value)
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{
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jz_writef(AIC_RGADW, ADDR(reg), DATA(value));
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jz_writef(AIC_RGADW, RGWR(1));
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while(jz_readf(AIC_RGADW, RGWR));
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}
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static void x1000_icodec_update_direct(int reg, int mask, int value)
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{
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int x = x1000_icodec_read_direct(reg) & ~mask;
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x |= value;
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x1000_icodec_write_direct(reg, x);
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}
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static int x1000_icodec_read_indirect(int c_reg, int index)
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{
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x1000_icodec_update_direct(c_reg, 0x7f, index & 0x3f);
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return x1000_icodec_read_direct(c_reg+1);
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}
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static void x1000_icodec_write_indirect(int c_reg, int index, int value)
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{
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/* NB: The X1000 programming manual says we should write the data
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* register first, but in fact the control register needs to be
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* written first (following Ingenic's Linux driver). */
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x1000_icodec_update_direct(c_reg, 0x7f, 0x40 | (index & 0x3f));
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x1000_icodec_write_direct(c_reg+1, value);
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}
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static void x1000_icodec_update_indirect(int c_reg, int index, int mask, int value)
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{
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int x = x1000_icodec_read_indirect(c_reg, index) & ~mask;
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x |= value;
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x1000_icodec_write_indirect(c_reg, index, x);
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}
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int x1000_icodec_read(int reg)
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{
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if(reg & JZCODEC_INDIRECT_BIT)
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return x1000_icodec_read_indirect(JZCODEC_INDIRECT_CREG(reg),
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JZCODEC_INDIRECT_INDEX(reg));
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else
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return x1000_icodec_read_direct(reg);
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}
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void x1000_icodec_write(int reg, int value)
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{
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if(reg & JZCODEC_INDIRECT_BIT)
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return x1000_icodec_write_indirect(JZCODEC_INDIRECT_CREG(reg),
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JZCODEC_INDIRECT_INDEX(reg), value);
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else
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return x1000_icodec_write_direct(reg, value);
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}
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void x1000_icodec_update(int reg, int mask, int value)
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{
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if(reg & JZCODEC_INDIRECT_BIT)
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return x1000_icodec_update_indirect(JZCODEC_INDIRECT_CREG(reg),
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JZCODEC_INDIRECT_INDEX(reg),
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mask, value);
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else
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return x1000_icodec_update_direct(reg, mask, value);
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}
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