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rockbox/firmware/target/arm/imx233/regs/stmp3700/clkctrl.h
Amaury Pouly eac1ca22bd imx233: generate register headers using headergen_v2 and update code for it 
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.

The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
  BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
  BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
  its equivalent for BF_WR(reg_SET, ...)

I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".

Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml

Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-28 16:49:22 +02:00

777 lines
49 KiB
C
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stmp3700 version: 2.4.0
* stmp3700 authors: Amaury Pouly
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_STMP3700_CLKCTRL_H__
#define __HEADERGEN_STMP3700_CLKCTRL_H__
#define HW_CLKCTRL_PLLCTRL0 HW(CLKCTRL_PLLCTRL0)
#define HWA_CLKCTRL_PLLCTRL0 (0x80040000 + 0x0)
#define HWT_CLKCTRL_PLLCTRL0 HWIO_32_RW
#define HWN_CLKCTRL_PLLCTRL0 CLKCTRL_PLLCTRL0
#define HWI_CLKCTRL_PLLCTRL0
#define HW_CLKCTRL_PLLCTRL0_SET HW(CLKCTRL_PLLCTRL0_SET)
#define HWA_CLKCTRL_PLLCTRL0_SET (HWA_CLKCTRL_PLLCTRL0 + 0x4)
#define HWT_CLKCTRL_PLLCTRL0_SET HWIO_32_WO
#define HWN_CLKCTRL_PLLCTRL0_SET CLKCTRL_PLLCTRL0
#define HWI_CLKCTRL_PLLCTRL0_SET
#define HW_CLKCTRL_PLLCTRL0_CLR HW(CLKCTRL_PLLCTRL0_CLR)
#define HWA_CLKCTRL_PLLCTRL0_CLR (HWA_CLKCTRL_PLLCTRL0 + 0x8)
#define HWT_CLKCTRL_PLLCTRL0_CLR HWIO_32_WO
#define HWN_CLKCTRL_PLLCTRL0_CLR CLKCTRL_PLLCTRL0
#define HWI_CLKCTRL_PLLCTRL0_CLR
#define HW_CLKCTRL_PLLCTRL0_TOG HW(CLKCTRL_PLLCTRL0_TOG)
#define HWA_CLKCTRL_PLLCTRL0_TOG (HWA_CLKCTRL_PLLCTRL0 + 0xc)
#define HWT_CLKCTRL_PLLCTRL0_TOG HWIO_32_WO
#define HWN_CLKCTRL_PLLCTRL0_TOG CLKCTRL_PLLCTRL0
#define HWI_CLKCTRL_PLLCTRL0_TOG
#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) (((v) & 0x3) << 28)
#define BFM_CLKCTRL_PLLCTRL0_LFR_SEL(v) BM_CLKCTRL_PLLCTRL0_LFR_SEL
#define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(e) BF_CLKCTRL_PLLCTRL0_LFR_SEL(BV_CLKCTRL_PLLCTRL0_LFR_SEL__##e)
#define BFM_CLKCTRL_PLLCTRL0_LFR_SEL_V(v) BM_CLKCTRL_PLLCTRL0_LFR_SEL
#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x3000000
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) (((v) & 0x3) << 24)
#define BFM_CLKCTRL_PLLCTRL0_CP_SEL(v) BM_CLKCTRL_PLLCTRL0_CP_SEL
#define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(e) BF_CLKCTRL_PLLCTRL0_CP_SEL(BV_CLKCTRL_PLLCTRL0_CP_SEL__##e)
#define BFM_CLKCTRL_PLLCTRL0_CP_SEL_V(v) BM_CLKCTRL_PLLCTRL0_CP_SEL
#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x300000
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) (((v) & 0x3) << 20)
#define BFM_CLKCTRL_PLLCTRL0_DIV_SEL(v) BM_CLKCTRL_PLLCTRL0_DIV_SEL
#define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(e) BF_CLKCTRL_PLLCTRL0_DIV_SEL(BV_CLKCTRL_PLLCTRL0_DIV_SEL__##e)
#define BFM_CLKCTRL_PLLCTRL0_DIV_SEL_V(v) BM_CLKCTRL_PLLCTRL0_DIV_SEL
#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000
#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) & 0x1) << 18)
#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(e) BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(BV_CLKCTRL_PLLCTRL0_EN_USB_CLKS__##e)
#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(v) BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
#define BP_CLKCTRL_PLLCTRL0_POWER 16
#define BM_CLKCTRL_PLLCTRL0_POWER 0x10000
#define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) & 0x1) << 16)
#define BFM_CLKCTRL_PLLCTRL0_POWER(v) BM_CLKCTRL_PLLCTRL0_POWER
#define BF_CLKCTRL_PLLCTRL0_POWER_V(e) BF_CLKCTRL_PLLCTRL0_POWER(BV_CLKCTRL_PLLCTRL0_POWER__##e)
#define BFM_CLKCTRL_PLLCTRL0_POWER_V(v) BM_CLKCTRL_PLLCTRL0_POWER
#define HW_CLKCTRL_PLLCTRL1 HW(CLKCTRL_PLLCTRL1)
#define HWA_CLKCTRL_PLLCTRL1 (0x80040000 + 0x10)
#define HWT_CLKCTRL_PLLCTRL1 HWIO_32_RW
#define HWN_CLKCTRL_PLLCTRL1 CLKCTRL_PLLCTRL1
#define HWI_CLKCTRL_PLLCTRL1
#define BP_CLKCTRL_PLLCTRL1_LOCK 31
#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
#define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_PLLCTRL1_LOCK(v) BM_CLKCTRL_PLLCTRL1_LOCK
#define BF_CLKCTRL_PLLCTRL1_LOCK_V(e) BF_CLKCTRL_PLLCTRL1_LOCK(BV_CLKCTRL_PLLCTRL1_LOCK__##e)
#define BFM_CLKCTRL_PLLCTRL1_LOCK_V(v) BM_CLKCTRL_PLLCTRL1_LOCK
#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30
#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(e) BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(BV_CLKCTRL_PLLCTRL1_FORCE_LOCK__##e)
#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(v) BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff
#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) & 0xffff) << 0)
#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(e) BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(BV_CLKCTRL_PLLCTRL1_LOCK_COUNT__##e)
#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(v) BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
#define HW_CLKCTRL_CPU HW(CLKCTRL_CPU)
#define HWA_CLKCTRL_CPU (0x80040000 + 0x20)
#define HWT_CLKCTRL_CPU HWIO_32_RW
#define HWN_CLKCTRL_CPU CLKCTRL_CPU
#define HWI_CLKCTRL_CPU
#define HW_CLKCTRL_CPU_SET HW(CLKCTRL_CPU_SET)
#define HWA_CLKCTRL_CPU_SET (HWA_CLKCTRL_CPU + 0x4)
#define HWT_CLKCTRL_CPU_SET HWIO_32_WO
#define HWN_CLKCTRL_CPU_SET CLKCTRL_CPU
#define HWI_CLKCTRL_CPU_SET
#define HW_CLKCTRL_CPU_CLR HW(CLKCTRL_CPU_CLR)
#define HWA_CLKCTRL_CPU_CLR (HWA_CLKCTRL_CPU + 0x8)
#define HWT_CLKCTRL_CPU_CLR HWIO_32_WO
#define HWN_CLKCTRL_CPU_CLR CLKCTRL_CPU
#define HWI_CLKCTRL_CPU_CLR
#define HW_CLKCTRL_CPU_TOG HW(CLKCTRL_CPU_TOG)
#define HWA_CLKCTRL_CPU_TOG (HWA_CLKCTRL_CPU + 0xc)
#define HWT_CLKCTRL_CPU_TOG HWIO_32_WO
#define HWN_CLKCTRL_CPU_TOG CLKCTRL_CPU
#define HWI_CLKCTRL_CPU_TOG
#define BP_CLKCTRL_CPU_BUSY_REF_XTAL 29
#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
#define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_CPU_BUSY_REF_XTAL(v) BM_CLKCTRL_CPU_BUSY_REF_XTAL
#define BF_CLKCTRL_CPU_BUSY_REF_XTAL_V(e) BF_CLKCTRL_CPU_BUSY_REF_XTAL(BV_CLKCTRL_CPU_BUSY_REF_XTAL__##e)
#define BFM_CLKCTRL_CPU_BUSY_REF_XTAL_V(v) BM_CLKCTRL_CPU_BUSY_REF_XTAL
#define BP_CLKCTRL_CPU_BUSY_REF_CPU 28
#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
#define BF_CLKCTRL_CPU_BUSY_REF_CPU(v) (((v) & 0x1) << 28)
#define BFM_CLKCTRL_CPU_BUSY_REF_CPU(v) BM_CLKCTRL_CPU_BUSY_REF_CPU
#define BF_CLKCTRL_CPU_BUSY_REF_CPU_V(e) BF_CLKCTRL_CPU_BUSY_REF_CPU(BV_CLKCTRL_CPU_BUSY_REF_CPU__##e)
#define BFM_CLKCTRL_CPU_BUSY_REF_CPU_V(v) BM_CLKCTRL_CPU_BUSY_REF_CPU
#define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 26
#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x4000000
#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v) (((v) & 0x1) << 26)
#define BFM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v) BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN
#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN_V(e) BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(BV_CLKCTRL_CPU_DIV_XTAL_FRAC_EN__##e)
#define BFM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN_V(v) BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN
#define BP_CLKCTRL_CPU_DIV_XTAL 16
#define BM_CLKCTRL_CPU_DIV_XTAL 0x3ff0000
#define BF_CLKCTRL_CPU_DIV_XTAL(v) (((v) & 0x3ff) << 16)
#define BFM_CLKCTRL_CPU_DIV_XTAL(v) BM_CLKCTRL_CPU_DIV_XTAL
#define BF_CLKCTRL_CPU_DIV_XTAL_V(e) BF_CLKCTRL_CPU_DIV_XTAL(BV_CLKCTRL_CPU_DIV_XTAL__##e)
#define BFM_CLKCTRL_CPU_DIV_XTAL_V(v) BM_CLKCTRL_CPU_DIV_XTAL
#define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12
#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000
#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) & 0x1) << 12)
#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT(v) BM_CLKCTRL_CPU_INTERRUPT_WAIT
#define BF_CLKCTRL_CPU_INTERRUPT_WAIT_V(e) BF_CLKCTRL_CPU_INTERRUPT_WAIT(BV_CLKCTRL_CPU_INTERRUPT_WAIT__##e)
#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT_V(v) BM_CLKCTRL_CPU_INTERRUPT_WAIT
#define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN 10
#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x400
#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v) (((v) & 0x1) << 10)
#define BFM_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v) BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN
#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN_V(e) BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(BV_CLKCTRL_CPU_DIV_CPU_FRAC_EN__##e)
#define BFM_CLKCTRL_CPU_DIV_CPU_FRAC_EN_V(v) BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN
#define BP_CLKCTRL_CPU_DIV_CPU 0
#define BM_CLKCTRL_CPU_DIV_CPU 0x3ff
#define BF_CLKCTRL_CPU_DIV_CPU(v) (((v) & 0x3ff) << 0)
#define BFM_CLKCTRL_CPU_DIV_CPU(v) BM_CLKCTRL_CPU_DIV_CPU
#define BF_CLKCTRL_CPU_DIV_CPU_V(e) BF_CLKCTRL_CPU_DIV_CPU(BV_CLKCTRL_CPU_DIV_CPU__##e)
#define BFM_CLKCTRL_CPU_DIV_CPU_V(v) BM_CLKCTRL_CPU_DIV_CPU
#define HW_CLKCTRL_HBUS HW(CLKCTRL_HBUS)
#define HWA_CLKCTRL_HBUS (0x80040000 + 0x30)
#define HWT_CLKCTRL_HBUS HWIO_32_RW
#define HWN_CLKCTRL_HBUS CLKCTRL_HBUS
#define HWI_CLKCTRL_HBUS
#define HW_CLKCTRL_HBUS_SET HW(CLKCTRL_HBUS_SET)
#define HWA_CLKCTRL_HBUS_SET (HWA_CLKCTRL_HBUS + 0x4)
#define HWT_CLKCTRL_HBUS_SET HWIO_32_WO
#define HWN_CLKCTRL_HBUS_SET CLKCTRL_HBUS
#define HWI_CLKCTRL_HBUS_SET
#define HW_CLKCTRL_HBUS_CLR HW(CLKCTRL_HBUS_CLR)
#define HWA_CLKCTRL_HBUS_CLR (HWA_CLKCTRL_HBUS + 0x8)
#define HWT_CLKCTRL_HBUS_CLR HWIO_32_WO
#define HWN_CLKCTRL_HBUS_CLR CLKCTRL_HBUS
#define HWI_CLKCTRL_HBUS_CLR
#define HW_CLKCTRL_HBUS_TOG HW(CLKCTRL_HBUS_TOG)
#define HWA_CLKCTRL_HBUS_TOG (HWA_CLKCTRL_HBUS + 0xc)
#define HWT_CLKCTRL_HBUS_TOG HWIO_32_WO
#define HWN_CLKCTRL_HBUS_TOG CLKCTRL_HBUS
#define HWI_CLKCTRL_HBUS_TOG
#define BP_CLKCTRL_HBUS_BUSY 29
#define BM_CLKCTRL_HBUS_BUSY 0x20000000
#define BF_CLKCTRL_HBUS_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_HBUS_BUSY(v) BM_CLKCTRL_HBUS_BUSY
#define BF_CLKCTRL_HBUS_BUSY_V(e) BF_CLKCTRL_HBUS_BUSY(BV_CLKCTRL_HBUS_BUSY__##e)
#define BFM_CLKCTRL_HBUS_BUSY_V(v) BM_CLKCTRL_HBUS_BUSY
#define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 26
#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x4000000
#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v) (((v) & 0x1) << 26)
#define BFM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v) BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE
#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(BV_CLKCTRL_HBUS_APBHDMA_AS_ENABLE__##e)
#define BFM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE
#define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 25
#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x2000000
#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v) (((v) & 0x1) << 25)
#define BFM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v) BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE
#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(BV_CLKCTRL_HBUS_APBXDMA_AS_ENABLE__##e)
#define BFM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE
#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 24
#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x1000000
#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v) (((v) & 0x1) << 24)
#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v) BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE
#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(BV_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE__##e)
#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE
#define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 23
#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x800000
#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v) (((v) & 0x1) << 23)
#define BFM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v) BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE
#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(BV_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE__##e)
#define BFM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE
#define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 22
#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x400000
#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v) (((v) & 0x1) << 22)
#define BFM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v) BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE
#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(BV_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE__##e)
#define BFM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE
#define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 21
#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x200000
#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v) (((v) & 0x1) << 21)
#define BFM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v) BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE
#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(BV_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE__##e)
#define BFM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE
#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20
#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000
#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) & 0x1) << 20)
#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(e) BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(BV_CLKCTRL_HBUS_AUTO_SLOW_MODE__##e)
#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(v) BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
#define BP_CLKCTRL_HBUS_SLOW_DIV 16
#define BM_CLKCTRL_HBUS_SLOW_DIV 0x70000
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
#define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) & 0x7) << 16)
#define BFM_CLKCTRL_HBUS_SLOW_DIV(v) BM_CLKCTRL_HBUS_SLOW_DIV
#define BF_CLKCTRL_HBUS_SLOW_DIV_V(e) BF_CLKCTRL_HBUS_SLOW_DIV(BV_CLKCTRL_HBUS_SLOW_DIV__##e)
#define BFM_CLKCTRL_HBUS_SLOW_DIV_V(v) BM_CLKCTRL_HBUS_SLOW_DIV
#define BP_CLKCTRL_HBUS_DIV_FRAC_EN 5
#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x20
#define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v) (((v) & 0x1) << 5)
#define BFM_CLKCTRL_HBUS_DIV_FRAC_EN(v) BM_CLKCTRL_HBUS_DIV_FRAC_EN
#define BF_CLKCTRL_HBUS_DIV_FRAC_EN_V(e) BF_CLKCTRL_HBUS_DIV_FRAC_EN(BV_CLKCTRL_HBUS_DIV_FRAC_EN__##e)
#define BFM_CLKCTRL_HBUS_DIV_FRAC_EN_V(v) BM_CLKCTRL_HBUS_DIV_FRAC_EN
#define BP_CLKCTRL_HBUS_DIV 0
#define BM_CLKCTRL_HBUS_DIV 0x1f
#define BF_CLKCTRL_HBUS_DIV(v) (((v) & 0x1f) << 0)
#define BFM_CLKCTRL_HBUS_DIV(v) BM_CLKCTRL_HBUS_DIV
#define BF_CLKCTRL_HBUS_DIV_V(e) BF_CLKCTRL_HBUS_DIV(BV_CLKCTRL_HBUS_DIV__##e)
#define BFM_CLKCTRL_HBUS_DIV_V(v) BM_CLKCTRL_HBUS_DIV
#define HW_CLKCTRL_XBUS HW(CLKCTRL_XBUS)
#define HWA_CLKCTRL_XBUS (0x80040000 + 0x40)
#define HWT_CLKCTRL_XBUS HWIO_32_RW
#define HWN_CLKCTRL_XBUS CLKCTRL_XBUS
#define HWI_CLKCTRL_XBUS
#define BP_CLKCTRL_XBUS_BUSY 31
#define BM_CLKCTRL_XBUS_BUSY 0x80000000
#define BF_CLKCTRL_XBUS_BUSY(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_XBUS_BUSY(v) BM_CLKCTRL_XBUS_BUSY
#define BF_CLKCTRL_XBUS_BUSY_V(e) BF_CLKCTRL_XBUS_BUSY(BV_CLKCTRL_XBUS_BUSY__##e)
#define BFM_CLKCTRL_XBUS_BUSY_V(v) BM_CLKCTRL_XBUS_BUSY
#define BP_CLKCTRL_XBUS_DIV_FRAC_EN 10
#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x400
#define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v) (((v) & 0x1) << 10)
#define BFM_CLKCTRL_XBUS_DIV_FRAC_EN(v) BM_CLKCTRL_XBUS_DIV_FRAC_EN
#define BF_CLKCTRL_XBUS_DIV_FRAC_EN_V(e) BF_CLKCTRL_XBUS_DIV_FRAC_EN(BV_CLKCTRL_XBUS_DIV_FRAC_EN__##e)
#define BFM_CLKCTRL_XBUS_DIV_FRAC_EN_V(v) BM_CLKCTRL_XBUS_DIV_FRAC_EN
#define BP_CLKCTRL_XBUS_DIV 0
#define BM_CLKCTRL_XBUS_DIV 0x3ff
#define BF_CLKCTRL_XBUS_DIV(v) (((v) & 0x3ff) << 0)
#define BFM_CLKCTRL_XBUS_DIV(v) BM_CLKCTRL_XBUS_DIV
#define BF_CLKCTRL_XBUS_DIV_V(e) BF_CLKCTRL_XBUS_DIV(BV_CLKCTRL_XBUS_DIV__##e)
#define BFM_CLKCTRL_XBUS_DIV_V(v) BM_CLKCTRL_XBUS_DIV
#define HW_CLKCTRL_XTAL HW(CLKCTRL_XTAL)
#define HWA_CLKCTRL_XTAL (0x80040000 + 0x50)
#define HWT_CLKCTRL_XTAL HWIO_32_RW
#define HWN_CLKCTRL_XTAL CLKCTRL_XTAL
#define HWI_CLKCTRL_XTAL
#define HW_CLKCTRL_XTAL_SET HW(CLKCTRL_XTAL_SET)
#define HWA_CLKCTRL_XTAL_SET (HWA_CLKCTRL_XTAL + 0x4)
#define HWT_CLKCTRL_XTAL_SET HWIO_32_WO
#define HWN_CLKCTRL_XTAL_SET CLKCTRL_XTAL
#define HWI_CLKCTRL_XTAL_SET
#define HW_CLKCTRL_XTAL_CLR HW(CLKCTRL_XTAL_CLR)
#define HWA_CLKCTRL_XTAL_CLR (HWA_CLKCTRL_XTAL + 0x8)
#define HWT_CLKCTRL_XTAL_CLR HWIO_32_WO
#define HWN_CLKCTRL_XTAL_CLR CLKCTRL_XTAL
#define HWI_CLKCTRL_XTAL_CLR
#define HW_CLKCTRL_XTAL_TOG HW(CLKCTRL_XTAL_TOG)
#define HWA_CLKCTRL_XTAL_TOG (HWA_CLKCTRL_XTAL + 0xc)
#define HWT_CLKCTRL_XTAL_TOG HWIO_32_WO
#define HWN_CLKCTRL_XTAL_TOG CLKCTRL_XTAL
#define HWI_CLKCTRL_XTAL_TOG
#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_XTAL_UART_CLK_GATE(v) BM_CLKCTRL_XTAL_UART_CLK_GATE
#define BF_CLKCTRL_XTAL_UART_CLK_GATE_V(e) BF_CLKCTRL_XTAL_UART_CLK_GATE(BV_CLKCTRL_XTAL_UART_CLK_GATE__##e)
#define BFM_CLKCTRL_XTAL_UART_CLK_GATE_V(v) BM_CLKCTRL_XTAL_UART_CLK_GATE
#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30
#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(e) BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(BV_CLKCTRL_XTAL_FILT_CLK24M_GATE__##e)
#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(v) BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(e) BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(BV_CLKCTRL_XTAL_PWM_CLK24M_GATE__##e)
#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(v) BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28
#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) & 0x1) << 28)
#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(e) BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(BV_CLKCTRL_XTAL_DRI_CLK24M_GATE__##e)
#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(v) BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27
#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000
#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) & 0x1) << 27)
#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(e) BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(BV_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE__##e)
#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(v) BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000
#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) & 0x1) << 26)
#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(e) BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(BV_CLKCTRL_XTAL_TIMROT_CLK32K_GATE__##e)
#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(v) BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
#define BP_CLKCTRL_XTAL_DIV_UART 0
#define BM_CLKCTRL_XTAL_DIV_UART 0x3
#define BF_CLKCTRL_XTAL_DIV_UART(v) (((v) & 0x3) << 0)
#define BFM_CLKCTRL_XTAL_DIV_UART(v) BM_CLKCTRL_XTAL_DIV_UART
#define BF_CLKCTRL_XTAL_DIV_UART_V(e) BF_CLKCTRL_XTAL_DIV_UART(BV_CLKCTRL_XTAL_DIV_UART__##e)
#define BFM_CLKCTRL_XTAL_DIV_UART_V(v) BM_CLKCTRL_XTAL_DIV_UART
#define HW_CLKCTRL_PIX HW(CLKCTRL_PIX)
#define HWA_CLKCTRL_PIX (0x80040000 + 0x60)
#define HWT_CLKCTRL_PIX HWIO_32_RW
#define HWN_CLKCTRL_PIX CLKCTRL_PIX
#define HWI_CLKCTRL_PIX
#define BP_CLKCTRL_PIX_CLKGATE 31
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
#define BF_CLKCTRL_PIX_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_PIX_CLKGATE(v) BM_CLKCTRL_PIX_CLKGATE
#define BF_CLKCTRL_PIX_CLKGATE_V(e) BF_CLKCTRL_PIX_CLKGATE(BV_CLKCTRL_PIX_CLKGATE__##e)
#define BFM_CLKCTRL_PIX_CLKGATE_V(v) BM_CLKCTRL_PIX_CLKGATE
#define BP_CLKCTRL_PIX_BUSY 29
#define BM_CLKCTRL_PIX_BUSY 0x20000000
#define BF_CLKCTRL_PIX_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_PIX_BUSY(v) BM_CLKCTRL_PIX_BUSY
#define BF_CLKCTRL_PIX_BUSY_V(e) BF_CLKCTRL_PIX_BUSY(BV_CLKCTRL_PIX_BUSY__##e)
#define BFM_CLKCTRL_PIX_BUSY_V(v) BM_CLKCTRL_PIX_BUSY
#define BP_CLKCTRL_PIX_DIV_FRAC_EN 15
#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x8000
#define BF_CLKCTRL_PIX_DIV_FRAC_EN(v) (((v) & 0x1) << 15)
#define BFM_CLKCTRL_PIX_DIV_FRAC_EN(v) BM_CLKCTRL_PIX_DIV_FRAC_EN
#define BF_CLKCTRL_PIX_DIV_FRAC_EN_V(e) BF_CLKCTRL_PIX_DIV_FRAC_EN(BV_CLKCTRL_PIX_DIV_FRAC_EN__##e)
#define BFM_CLKCTRL_PIX_DIV_FRAC_EN_V(v) BM_CLKCTRL_PIX_DIV_FRAC_EN
#define BP_CLKCTRL_PIX_DIV 0
#define BM_CLKCTRL_PIX_DIV 0x7fff
#define BF_CLKCTRL_PIX_DIV(v) (((v) & 0x7fff) << 0)
#define BFM_CLKCTRL_PIX_DIV(v) BM_CLKCTRL_PIX_DIV
#define BF_CLKCTRL_PIX_DIV_V(e) BF_CLKCTRL_PIX_DIV(BV_CLKCTRL_PIX_DIV__##e)
#define BFM_CLKCTRL_PIX_DIV_V(v) BM_CLKCTRL_PIX_DIV
#define HW_CLKCTRL_SSP HW(CLKCTRL_SSP)
#define HWA_CLKCTRL_SSP (0x80040000 + 0x70)
#define HWT_CLKCTRL_SSP HWIO_32_RW
#define HWN_CLKCTRL_SSP CLKCTRL_SSP
#define HWI_CLKCTRL_SSP
#define BP_CLKCTRL_SSP_CLKGATE 31
#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
#define BF_CLKCTRL_SSP_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_SSP_CLKGATE(v) BM_CLKCTRL_SSP_CLKGATE
#define BF_CLKCTRL_SSP_CLKGATE_V(e) BF_CLKCTRL_SSP_CLKGATE(BV_CLKCTRL_SSP_CLKGATE__##e)
#define BFM_CLKCTRL_SSP_CLKGATE_V(v) BM_CLKCTRL_SSP_CLKGATE
#define BP_CLKCTRL_SSP_BUSY 29
#define BM_CLKCTRL_SSP_BUSY 0x20000000
#define BF_CLKCTRL_SSP_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_SSP_BUSY(v) BM_CLKCTRL_SSP_BUSY
#define BF_CLKCTRL_SSP_BUSY_V(e) BF_CLKCTRL_SSP_BUSY(BV_CLKCTRL_SSP_BUSY__##e)
#define BFM_CLKCTRL_SSP_BUSY_V(v) BM_CLKCTRL_SSP_BUSY
#define BP_CLKCTRL_SSP_DIV_FRAC_EN 9
#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x200
#define BF_CLKCTRL_SSP_DIV_FRAC_EN(v) (((v) & 0x1) << 9)
#define BFM_CLKCTRL_SSP_DIV_FRAC_EN(v) BM_CLKCTRL_SSP_DIV_FRAC_EN
#define BF_CLKCTRL_SSP_DIV_FRAC_EN_V(e) BF_CLKCTRL_SSP_DIV_FRAC_EN(BV_CLKCTRL_SSP_DIV_FRAC_EN__##e)
#define BFM_CLKCTRL_SSP_DIV_FRAC_EN_V(v) BM_CLKCTRL_SSP_DIV_FRAC_EN
#define BP_CLKCTRL_SSP_DIV 0
#define BM_CLKCTRL_SSP_DIV 0x1ff
#define BF_CLKCTRL_SSP_DIV(v) (((v) & 0x1ff) << 0)
#define BFM_CLKCTRL_SSP_DIV(v) BM_CLKCTRL_SSP_DIV
#define BF_CLKCTRL_SSP_DIV_V(e) BF_CLKCTRL_SSP_DIV(BV_CLKCTRL_SSP_DIV__##e)
#define BFM_CLKCTRL_SSP_DIV_V(v) BM_CLKCTRL_SSP_DIV
#define HW_CLKCTRL_GPMI HW(CLKCTRL_GPMI)
#define HWA_CLKCTRL_GPMI (0x80040000 + 0x80)
#define HWT_CLKCTRL_GPMI HWIO_32_RW
#define HWN_CLKCTRL_GPMI CLKCTRL_GPMI
#define HWI_CLKCTRL_GPMI
#define BP_CLKCTRL_GPMI_CLKGATE 31
#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
#define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_GPMI_CLKGATE(v) BM_CLKCTRL_GPMI_CLKGATE
#define BF_CLKCTRL_GPMI_CLKGATE_V(e) BF_CLKCTRL_GPMI_CLKGATE(BV_CLKCTRL_GPMI_CLKGATE__##e)
#define BFM_CLKCTRL_GPMI_CLKGATE_V(v) BM_CLKCTRL_GPMI_CLKGATE
#define BP_CLKCTRL_GPMI_BUSY 29
#define BM_CLKCTRL_GPMI_BUSY 0x20000000
#define BF_CLKCTRL_GPMI_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_GPMI_BUSY(v) BM_CLKCTRL_GPMI_BUSY
#define BF_CLKCTRL_GPMI_BUSY_V(e) BF_CLKCTRL_GPMI_BUSY(BV_CLKCTRL_GPMI_BUSY__##e)
#define BFM_CLKCTRL_GPMI_BUSY_V(v) BM_CLKCTRL_GPMI_BUSY
#define BP_CLKCTRL_GPMI_DIV_FRAC_EN 10
#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x400
#define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v) (((v) & 0x1) << 10)
#define BFM_CLKCTRL_GPMI_DIV_FRAC_EN(v) BM_CLKCTRL_GPMI_DIV_FRAC_EN
#define BF_CLKCTRL_GPMI_DIV_FRAC_EN_V(e) BF_CLKCTRL_GPMI_DIV_FRAC_EN(BV_CLKCTRL_GPMI_DIV_FRAC_EN__##e)
#define BFM_CLKCTRL_GPMI_DIV_FRAC_EN_V(v) BM_CLKCTRL_GPMI_DIV_FRAC_EN
#define BP_CLKCTRL_GPMI_DIV 0
#define BM_CLKCTRL_GPMI_DIV 0x3ff
#define BF_CLKCTRL_GPMI_DIV(v) (((v) & 0x3ff) << 0)
#define BFM_CLKCTRL_GPMI_DIV(v) BM_CLKCTRL_GPMI_DIV
#define BF_CLKCTRL_GPMI_DIV_V(e) BF_CLKCTRL_GPMI_DIV(BV_CLKCTRL_GPMI_DIV__##e)
#define BFM_CLKCTRL_GPMI_DIV_V(v) BM_CLKCTRL_GPMI_DIV
#define HW_CLKCTRL_SPDIF HW(CLKCTRL_SPDIF)
#define HWA_CLKCTRL_SPDIF (0x80040000 + 0x90)
#define HWT_CLKCTRL_SPDIF HWIO_32_RW
#define HWN_CLKCTRL_SPDIF CLKCTRL_SPDIF
#define HWI_CLKCTRL_SPDIF
#define BP_CLKCTRL_SPDIF_CLKGATE 31
#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
#define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_SPDIF_CLKGATE(v) BM_CLKCTRL_SPDIF_CLKGATE
#define BF_CLKCTRL_SPDIF_CLKGATE_V(e) BF_CLKCTRL_SPDIF_CLKGATE(BV_CLKCTRL_SPDIF_CLKGATE__##e)
#define BFM_CLKCTRL_SPDIF_CLKGATE_V(v) BM_CLKCTRL_SPDIF_CLKGATE
#define HW_CLKCTRL_EMI HW(CLKCTRL_EMI)
#define HWA_CLKCTRL_EMI (0x80040000 + 0xa0)
#define HWT_CLKCTRL_EMI HWIO_32_RW
#define HWN_CLKCTRL_EMI CLKCTRL_EMI
#define HWI_CLKCTRL_EMI
#define BP_CLKCTRL_EMI_CLKGATE 31
#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
#define BF_CLKCTRL_EMI_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_EMI_CLKGATE(v) BM_CLKCTRL_EMI_CLKGATE
#define BF_CLKCTRL_EMI_CLKGATE_V(e) BF_CLKCTRL_EMI_CLKGATE(BV_CLKCTRL_EMI_CLKGATE__##e)
#define BFM_CLKCTRL_EMI_CLKGATE_V(v) BM_CLKCTRL_EMI_CLKGATE
#define BP_CLKCTRL_EMI_BUSY_REF_XTAL 29
#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
#define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_EMI_BUSY_REF_XTAL(v) BM_CLKCTRL_EMI_BUSY_REF_XTAL
#define BF_CLKCTRL_EMI_BUSY_REF_XTAL_V(e) BF_CLKCTRL_EMI_BUSY_REF_XTAL(BV_CLKCTRL_EMI_BUSY_REF_XTAL__##e)
#define BFM_CLKCTRL_EMI_BUSY_REF_XTAL_V(v) BM_CLKCTRL_EMI_BUSY_REF_XTAL
#define BP_CLKCTRL_EMI_BUSY_REF_EMI 28
#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
#define BF_CLKCTRL_EMI_BUSY_REF_EMI(v) (((v) & 0x1) << 28)
#define BFM_CLKCTRL_EMI_BUSY_REF_EMI(v) BM_CLKCTRL_EMI_BUSY_REF_EMI
#define BF_CLKCTRL_EMI_BUSY_REF_EMI_V(e) BF_CLKCTRL_EMI_BUSY_REF_EMI(BV_CLKCTRL_EMI_BUSY_REF_EMI__##e)
#define BFM_CLKCTRL_EMI_BUSY_REF_EMI_V(v) BM_CLKCTRL_EMI_BUSY_REF_EMI
#define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC 17
#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x20000
#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v) (((v) & 0x1) << 17)
#define BFM_CLKCTRL_EMI_BUSY_DCC_RESYNC(v) BM_CLKCTRL_EMI_BUSY_DCC_RESYNC
#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC_V(e) BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(BV_CLKCTRL_EMI_BUSY_DCC_RESYNC__##e)
#define BFM_CLKCTRL_EMI_BUSY_DCC_RESYNC_V(v) BM_CLKCTRL_EMI_BUSY_DCC_RESYNC
#define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE 16
#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x10000
#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) & 0x1) << 16)
#define BFM_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE
#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE_V(e) BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(BV_CLKCTRL_EMI_DCC_RESYNC_ENABLE__##e)
#define BFM_CLKCTRL_EMI_DCC_RESYNC_ENABLE_V(v) BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE
#define BP_CLKCTRL_EMI_DIV_XTAL 8
#define BM_CLKCTRL_EMI_DIV_XTAL 0xf00
#define BF_CLKCTRL_EMI_DIV_XTAL(v) (((v) & 0xf) << 8)
#define BFM_CLKCTRL_EMI_DIV_XTAL(v) BM_CLKCTRL_EMI_DIV_XTAL
#define BF_CLKCTRL_EMI_DIV_XTAL_V(e) BF_CLKCTRL_EMI_DIV_XTAL(BV_CLKCTRL_EMI_DIV_XTAL__##e)
#define BFM_CLKCTRL_EMI_DIV_XTAL_V(v) BM_CLKCTRL_EMI_DIV_XTAL
#define BP_CLKCTRL_EMI_DIV_EMI 0
#define BM_CLKCTRL_EMI_DIV_EMI 0x3f
#define BF_CLKCTRL_EMI_DIV_EMI(v) (((v) & 0x3f) << 0)
#define BFM_CLKCTRL_EMI_DIV_EMI(v) BM_CLKCTRL_EMI_DIV_EMI
#define BF_CLKCTRL_EMI_DIV_EMI_V(e) BF_CLKCTRL_EMI_DIV_EMI(BV_CLKCTRL_EMI_DIV_EMI__##e)
#define BFM_CLKCTRL_EMI_DIV_EMI_V(v) BM_CLKCTRL_EMI_DIV_EMI
#define HW_CLKCTRL_IR HW(CLKCTRL_IR)
#define HWA_CLKCTRL_IR (0x80040000 + 0xb0)
#define HWT_CLKCTRL_IR HWIO_32_RW
#define HWN_CLKCTRL_IR CLKCTRL_IR
#define HWI_CLKCTRL_IR
#define BP_CLKCTRL_IR_CLKGATE 31
#define BM_CLKCTRL_IR_CLKGATE 0x80000000
#define BF_CLKCTRL_IR_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_IR_CLKGATE(v) BM_CLKCTRL_IR_CLKGATE
#define BF_CLKCTRL_IR_CLKGATE_V(e) BF_CLKCTRL_IR_CLKGATE(BV_CLKCTRL_IR_CLKGATE__##e)
#define BFM_CLKCTRL_IR_CLKGATE_V(v) BM_CLKCTRL_IR_CLKGATE
#define BP_CLKCTRL_IR_AUTO_DIV 29
#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
#define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_IR_AUTO_DIV(v) BM_CLKCTRL_IR_AUTO_DIV
#define BF_CLKCTRL_IR_AUTO_DIV_V(e) BF_CLKCTRL_IR_AUTO_DIV(BV_CLKCTRL_IR_AUTO_DIV__##e)
#define BFM_CLKCTRL_IR_AUTO_DIV_V(v) BM_CLKCTRL_IR_AUTO_DIV
#define BP_CLKCTRL_IR_IR_BUSY 28
#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
#define BF_CLKCTRL_IR_IR_BUSY(v) (((v) & 0x1) << 28)
#define BFM_CLKCTRL_IR_IR_BUSY(v) BM_CLKCTRL_IR_IR_BUSY
#define BF_CLKCTRL_IR_IR_BUSY_V(e) BF_CLKCTRL_IR_IR_BUSY(BV_CLKCTRL_IR_IR_BUSY__##e)
#define BFM_CLKCTRL_IR_IR_BUSY_V(v) BM_CLKCTRL_IR_IR_BUSY
#define BP_CLKCTRL_IR_IROV_BUSY 27
#define BM_CLKCTRL_IR_IROV_BUSY 0x8000000
#define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) & 0x1) << 27)
#define BFM_CLKCTRL_IR_IROV_BUSY(v) BM_CLKCTRL_IR_IROV_BUSY
#define BF_CLKCTRL_IR_IROV_BUSY_V(e) BF_CLKCTRL_IR_IROV_BUSY(BV_CLKCTRL_IR_IROV_BUSY__##e)
#define BFM_CLKCTRL_IR_IROV_BUSY_V(v) BM_CLKCTRL_IR_IROV_BUSY
#define BP_CLKCTRL_IR_IROV_DIV 16
#define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000
#define BF_CLKCTRL_IR_IROV_DIV(v) (((v) & 0x1ff) << 16)
#define BFM_CLKCTRL_IR_IROV_DIV(v) BM_CLKCTRL_IR_IROV_DIV
#define BF_CLKCTRL_IR_IROV_DIV_V(e) BF_CLKCTRL_IR_IROV_DIV(BV_CLKCTRL_IR_IROV_DIV__##e)
#define BFM_CLKCTRL_IR_IROV_DIV_V(v) BM_CLKCTRL_IR_IROV_DIV
#define BP_CLKCTRL_IR_IR_DIV 0
#define BM_CLKCTRL_IR_IR_DIV 0x3ff
#define BF_CLKCTRL_IR_IR_DIV(v) (((v) & 0x3ff) << 0)
#define BFM_CLKCTRL_IR_IR_DIV(v) BM_CLKCTRL_IR_IR_DIV
#define BF_CLKCTRL_IR_IR_DIV_V(e) BF_CLKCTRL_IR_IR_DIV(BV_CLKCTRL_IR_IR_DIV__##e)
#define BFM_CLKCTRL_IR_IR_DIV_V(v) BM_CLKCTRL_IR_IR_DIV
#define HW_CLKCTRL_SAIF HW(CLKCTRL_SAIF)
#define HWA_CLKCTRL_SAIF (0x80040000 + 0xc0)
#define HWT_CLKCTRL_SAIF HWIO_32_RW
#define HWN_CLKCTRL_SAIF CLKCTRL_SAIF
#define HWI_CLKCTRL_SAIF
#define BP_CLKCTRL_SAIF_CLKGATE 31
#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
#define BF_CLKCTRL_SAIF_CLKGATE(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_SAIF_CLKGATE(v) BM_CLKCTRL_SAIF_CLKGATE
#define BF_CLKCTRL_SAIF_CLKGATE_V(e) BF_CLKCTRL_SAIF_CLKGATE(BV_CLKCTRL_SAIF_CLKGATE__##e)
#define BFM_CLKCTRL_SAIF_CLKGATE_V(v) BM_CLKCTRL_SAIF_CLKGATE
#define BP_CLKCTRL_SAIF_BUSY 29
#define BM_CLKCTRL_SAIF_BUSY 0x20000000
#define BF_CLKCTRL_SAIF_BUSY(v) (((v) & 0x1) << 29)
#define BFM_CLKCTRL_SAIF_BUSY(v) BM_CLKCTRL_SAIF_BUSY
#define BF_CLKCTRL_SAIF_BUSY_V(e) BF_CLKCTRL_SAIF_BUSY(BV_CLKCTRL_SAIF_BUSY__##e)
#define BFM_CLKCTRL_SAIF_BUSY_V(v) BM_CLKCTRL_SAIF_BUSY
#define BP_CLKCTRL_SAIF_DIV_FRAC_EN 16
#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x10000
#define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v) (((v) & 0x1) << 16)
#define BFM_CLKCTRL_SAIF_DIV_FRAC_EN(v) BM_CLKCTRL_SAIF_DIV_FRAC_EN
#define BF_CLKCTRL_SAIF_DIV_FRAC_EN_V(e) BF_CLKCTRL_SAIF_DIV_FRAC_EN(BV_CLKCTRL_SAIF_DIV_FRAC_EN__##e)
#define BFM_CLKCTRL_SAIF_DIV_FRAC_EN_V(v) BM_CLKCTRL_SAIF_DIV_FRAC_EN
#define BP_CLKCTRL_SAIF_DIV 0
#define BM_CLKCTRL_SAIF_DIV 0xffff
#define BF_CLKCTRL_SAIF_DIV(v) (((v) & 0xffff) << 0)
#define BFM_CLKCTRL_SAIF_DIV(v) BM_CLKCTRL_SAIF_DIV
#define BF_CLKCTRL_SAIF_DIV_V(e) BF_CLKCTRL_SAIF_DIV(BV_CLKCTRL_SAIF_DIV__##e)
#define BFM_CLKCTRL_SAIF_DIV_V(v) BM_CLKCTRL_SAIF_DIV
#define HW_CLKCTRL_FRAC HW(CLKCTRL_FRAC)
#define HWA_CLKCTRL_FRAC (0x80040000 + 0xd0)
#define HWT_CLKCTRL_FRAC HWIO_32_RW
#define HWN_CLKCTRL_FRAC CLKCTRL_FRAC
#define HWI_CLKCTRL_FRAC
#define HW_CLKCTRL_FRAC_SET HW(CLKCTRL_FRAC_SET)
#define HWA_CLKCTRL_FRAC_SET (HWA_CLKCTRL_FRAC + 0x4)
#define HWT_CLKCTRL_FRAC_SET HWIO_32_WO
#define HWN_CLKCTRL_FRAC_SET CLKCTRL_FRAC
#define HWI_CLKCTRL_FRAC_SET
#define HW_CLKCTRL_FRAC_CLR HW(CLKCTRL_FRAC_CLR)
#define HWA_CLKCTRL_FRAC_CLR (HWA_CLKCTRL_FRAC + 0x8)
#define HWT_CLKCTRL_FRAC_CLR HWIO_32_WO
#define HWN_CLKCTRL_FRAC_CLR CLKCTRL_FRAC
#define HWI_CLKCTRL_FRAC_CLR
#define HW_CLKCTRL_FRAC_TOG HW(CLKCTRL_FRAC_TOG)
#define HWA_CLKCTRL_FRAC_TOG (HWA_CLKCTRL_FRAC + 0xc)
#define HWT_CLKCTRL_FRAC_TOG HWIO_32_WO
#define HWN_CLKCTRL_FRAC_TOG CLKCTRL_FRAC
#define HWI_CLKCTRL_FRAC_TOG
#define BP_CLKCTRL_FRAC_CLKGATEIO 31
#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
#define BF_CLKCTRL_FRAC_CLKGATEIO(v) (((v) & 0x1) << 31)
#define BFM_CLKCTRL_FRAC_CLKGATEIO(v) BM_CLKCTRL_FRAC_CLKGATEIO
#define BF_CLKCTRL_FRAC_CLKGATEIO_V(e) BF_CLKCTRL_FRAC_CLKGATEIO(BV_CLKCTRL_FRAC_CLKGATEIO__##e)
#define BFM_CLKCTRL_FRAC_CLKGATEIO_V(v) BM_CLKCTRL_FRAC_CLKGATEIO
#define BP_CLKCTRL_FRAC_IO_STABLE 30
#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
#define BF_CLKCTRL_FRAC_IO_STABLE(v) (((v) & 0x1) << 30)
#define BFM_CLKCTRL_FRAC_IO_STABLE(v) BM_CLKCTRL_FRAC_IO_STABLE
#define BF_CLKCTRL_FRAC_IO_STABLE_V(e) BF_CLKCTRL_FRAC_IO_STABLE(BV_CLKCTRL_FRAC_IO_STABLE__##e)
#define BFM_CLKCTRL_FRAC_IO_STABLE_V(v) BM_CLKCTRL_FRAC_IO_STABLE
#define BP_CLKCTRL_FRAC_IOFRAC 24
#define BM_CLKCTRL_FRAC_IOFRAC 0x3f000000
#define BF_CLKCTRL_FRAC_IOFRAC(v) (((v) & 0x3f) << 24)
#define BFM_CLKCTRL_FRAC_IOFRAC(v) BM_CLKCTRL_FRAC_IOFRAC
#define BF_CLKCTRL_FRAC_IOFRAC_V(e) BF_CLKCTRL_FRAC_IOFRAC(BV_CLKCTRL_FRAC_IOFRAC__##e)
#define BFM_CLKCTRL_FRAC_IOFRAC_V(v) BM_CLKCTRL_FRAC_IOFRAC
#define BP_CLKCTRL_FRAC_CLKGATEPIX 23
#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x800000
#define BF_CLKCTRL_FRAC_CLKGATEPIX(v) (((v) & 0x1) << 23)
#define BFM_CLKCTRL_FRAC_CLKGATEPIX(v) BM_CLKCTRL_FRAC_CLKGATEPIX
#define BF_CLKCTRL_FRAC_CLKGATEPIX_V(e) BF_CLKCTRL_FRAC_CLKGATEPIX(BV_CLKCTRL_FRAC_CLKGATEPIX__##e)
#define BFM_CLKCTRL_FRAC_CLKGATEPIX_V(v) BM_CLKCTRL_FRAC_CLKGATEPIX
#define BP_CLKCTRL_FRAC_PIX_STABLE 22
#define BM_CLKCTRL_FRAC_PIX_STABLE 0x400000
#define BF_CLKCTRL_FRAC_PIX_STABLE(v) (((v) & 0x1) << 22)
#define BFM_CLKCTRL_FRAC_PIX_STABLE(v) BM_CLKCTRL_FRAC_PIX_STABLE
#define BF_CLKCTRL_FRAC_PIX_STABLE_V(e) BF_CLKCTRL_FRAC_PIX_STABLE(BV_CLKCTRL_FRAC_PIX_STABLE__##e)
#define BFM_CLKCTRL_FRAC_PIX_STABLE_V(v) BM_CLKCTRL_FRAC_PIX_STABLE
#define BP_CLKCTRL_FRAC_PIXFRAC 16
#define BM_CLKCTRL_FRAC_PIXFRAC 0x3f0000
#define BF_CLKCTRL_FRAC_PIXFRAC(v) (((v) & 0x3f) << 16)
#define BFM_CLKCTRL_FRAC_PIXFRAC(v) BM_CLKCTRL_FRAC_PIXFRAC
#define BF_CLKCTRL_FRAC_PIXFRAC_V(e) BF_CLKCTRL_FRAC_PIXFRAC(BV_CLKCTRL_FRAC_PIXFRAC__##e)
#define BFM_CLKCTRL_FRAC_PIXFRAC_V(v) BM_CLKCTRL_FRAC_PIXFRAC
#define BP_CLKCTRL_FRAC_CLKGATEEMI 15
#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x8000
#define BF_CLKCTRL_FRAC_CLKGATEEMI(v) (((v) & 0x1) << 15)
#define BFM_CLKCTRL_FRAC_CLKGATEEMI(v) BM_CLKCTRL_FRAC_CLKGATEEMI
#define BF_CLKCTRL_FRAC_CLKGATEEMI_V(e) BF_CLKCTRL_FRAC_CLKGATEEMI(BV_CLKCTRL_FRAC_CLKGATEEMI__##e)
#define BFM_CLKCTRL_FRAC_CLKGATEEMI_V(v) BM_CLKCTRL_FRAC_CLKGATEEMI
#define BP_CLKCTRL_FRAC_EMI_STABLE 14
#define BM_CLKCTRL_FRAC_EMI_STABLE 0x4000
#define BF_CLKCTRL_FRAC_EMI_STABLE(v) (((v) & 0x1) << 14)
#define BFM_CLKCTRL_FRAC_EMI_STABLE(v) BM_CLKCTRL_FRAC_EMI_STABLE
#define BF_CLKCTRL_FRAC_EMI_STABLE_V(e) BF_CLKCTRL_FRAC_EMI_STABLE(BV_CLKCTRL_FRAC_EMI_STABLE__##e)
#define BFM_CLKCTRL_FRAC_EMI_STABLE_V(v) BM_CLKCTRL_FRAC_EMI_STABLE
#define BP_CLKCTRL_FRAC_EMIFRAC 8
#define BM_CLKCTRL_FRAC_EMIFRAC 0x3f00
#define BF_CLKCTRL_FRAC_EMIFRAC(v) (((v) & 0x3f) << 8)
#define BFM_CLKCTRL_FRAC_EMIFRAC(v) BM_CLKCTRL_FRAC_EMIFRAC
#define BF_CLKCTRL_FRAC_EMIFRAC_V(e) BF_CLKCTRL_FRAC_EMIFRAC(BV_CLKCTRL_FRAC_EMIFRAC__##e)
#define BFM_CLKCTRL_FRAC_EMIFRAC_V(v) BM_CLKCTRL_FRAC_EMIFRAC
#define BP_CLKCTRL_FRAC_CLKGATECPU 7
#define BM_CLKCTRL_FRAC_CLKGATECPU 0x80
#define BF_CLKCTRL_FRAC_CLKGATECPU(v) (((v) & 0x1) << 7)
#define BFM_CLKCTRL_FRAC_CLKGATECPU(v) BM_CLKCTRL_FRAC_CLKGATECPU
#define BF_CLKCTRL_FRAC_CLKGATECPU_V(e) BF_CLKCTRL_FRAC_CLKGATECPU(BV_CLKCTRL_FRAC_CLKGATECPU__##e)
#define BFM_CLKCTRL_FRAC_CLKGATECPU_V(v) BM_CLKCTRL_FRAC_CLKGATECPU
#define BP_CLKCTRL_FRAC_CPU_STABLE 6
#define BM_CLKCTRL_FRAC_CPU_STABLE 0x40
#define BF_CLKCTRL_FRAC_CPU_STABLE(v) (((v) & 0x1) << 6)
#define BFM_CLKCTRL_FRAC_CPU_STABLE(v) BM_CLKCTRL_FRAC_CPU_STABLE
#define BF_CLKCTRL_FRAC_CPU_STABLE_V(e) BF_CLKCTRL_FRAC_CPU_STABLE(BV_CLKCTRL_FRAC_CPU_STABLE__##e)
#define BFM_CLKCTRL_FRAC_CPU_STABLE_V(v) BM_CLKCTRL_FRAC_CPU_STABLE
#define BP_CLKCTRL_FRAC_CPUFRAC 0
#define BM_CLKCTRL_FRAC_CPUFRAC 0x3f
#define BF_CLKCTRL_FRAC_CPUFRAC(v) (((v) & 0x3f) << 0)
#define BFM_CLKCTRL_FRAC_CPUFRAC(v) BM_CLKCTRL_FRAC_CPUFRAC
#define BF_CLKCTRL_FRAC_CPUFRAC_V(e) BF_CLKCTRL_FRAC_CPUFRAC(BV_CLKCTRL_FRAC_CPUFRAC__##e)
#define BFM_CLKCTRL_FRAC_CPUFRAC_V(v) BM_CLKCTRL_FRAC_CPUFRAC
#define HW_CLKCTRL_CLKSEQ HW(CLKCTRL_CLKSEQ)
#define HWA_CLKCTRL_CLKSEQ (0x80040000 + 0xe0)
#define HWT_CLKCTRL_CLKSEQ HWIO_32_RW
#define HWN_CLKCTRL_CLKSEQ CLKCTRL_CLKSEQ
#define HWI_CLKCTRL_CLKSEQ
#define HW_CLKCTRL_CLKSEQ_SET HW(CLKCTRL_CLKSEQ_SET)
#define HWA_CLKCTRL_CLKSEQ_SET (HWA_CLKCTRL_CLKSEQ + 0x4)
#define HWT_CLKCTRL_CLKSEQ_SET HWIO_32_WO
#define HWN_CLKCTRL_CLKSEQ_SET CLKCTRL_CLKSEQ
#define HWI_CLKCTRL_CLKSEQ_SET
#define HW_CLKCTRL_CLKSEQ_CLR HW(CLKCTRL_CLKSEQ_CLR)
#define HWA_CLKCTRL_CLKSEQ_CLR (HWA_CLKCTRL_CLKSEQ + 0x8)
#define HWT_CLKCTRL_CLKSEQ_CLR HWIO_32_WO
#define HWN_CLKCTRL_CLKSEQ_CLR CLKCTRL_CLKSEQ
#define HWI_CLKCTRL_CLKSEQ_CLR
#define HW_CLKCTRL_CLKSEQ_TOG HW(CLKCTRL_CLKSEQ_TOG)
#define HWA_CLKCTRL_CLKSEQ_TOG (HWA_CLKCTRL_CLKSEQ + 0xc)
#define HWT_CLKCTRL_CLKSEQ_TOG HWIO_32_WO
#define HWN_CLKCTRL_CLKSEQ_TOG CLKCTRL_CLKSEQ
#define HWI_CLKCTRL_CLKSEQ_TOG
#define BP_CLKCTRL_CLKSEQ_BYPASS_CPU 7
#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x80
#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v) (((v) & 0x1) << 7)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_CPU(v) BM_CLKCTRL_CLKSEQ_BYPASS_CPU
#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_CPU(BV_CLKCTRL_CLKSEQ_BYPASS_CPU__##e)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_CPU_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_CPU
#define BP_CLKCTRL_CLKSEQ_BYPASS_EMI 6
#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x40
#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v) (((v) & 0x1) << 6)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_EMI(v) BM_CLKCTRL_CLKSEQ_BYPASS_EMI
#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_EMI(BV_CLKCTRL_CLKSEQ_BYPASS_EMI__##e)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_EMI_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_EMI
#define BP_CLKCTRL_CLKSEQ_BYPASS_SSP 5
#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x20
#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v) (((v) & 0x1) << 5)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_SSP(v) BM_CLKCTRL_CLKSEQ_BYPASS_SSP
#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_SSP(BV_CLKCTRL_CLKSEQ_BYPASS_SSP__##e)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_SSP_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_SSP
#define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI 4
#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x10
#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v) (((v) & 0x1) << 4)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_GPMI(v) BM_CLKCTRL_CLKSEQ_BYPASS_GPMI
#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(BV_CLKCTRL_CLKSEQ_BYPASS_GPMI__##e)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_GPMI_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_GPMI
#define BP_CLKCTRL_CLKSEQ_BYPASS_IR 3
#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x8
#define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v) (((v) & 0x1) << 3)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_IR(v) BM_CLKCTRL_CLKSEQ_BYPASS_IR
#define BF_CLKCTRL_CLKSEQ_BYPASS_IR_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_IR(BV_CLKCTRL_CLKSEQ_BYPASS_IR__##e)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_IR_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_IR
#define BP_CLKCTRL_CLKSEQ_BYPASS_PIX 1
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x2
#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v) (((v) & 0x1) << 1)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_PIX(v) BM_CLKCTRL_CLKSEQ_BYPASS_PIX
#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_PIX(BV_CLKCTRL_CLKSEQ_BYPASS_PIX__##e)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_PIX_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_PIX
#define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF 0
#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x1
#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v) (((v) & 0x1) << 0)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_SAIF(v) BM_CLKCTRL_CLKSEQ_BYPASS_SAIF
#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(BV_CLKCTRL_CLKSEQ_BYPASS_SAIF__##e)
#define BFM_CLKCTRL_CLKSEQ_BYPASS_SAIF_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_SAIF
#define HW_CLKCTRL_RESET HW(CLKCTRL_RESET)
#define HWA_CLKCTRL_RESET (0x80040000 + 0xf0)
#define HWT_CLKCTRL_RESET HWIO_32_RW
#define HWN_CLKCTRL_RESET CLKCTRL_RESET
#define HWI_CLKCTRL_RESET
#define BP_CLKCTRL_RESET_CHIP 1
#define BM_CLKCTRL_RESET_CHIP 0x2
#define BF_CLKCTRL_RESET_CHIP(v) (((v) & 0x1) << 1)
#define BFM_CLKCTRL_RESET_CHIP(v) BM_CLKCTRL_RESET_CHIP
#define BF_CLKCTRL_RESET_CHIP_V(e) BF_CLKCTRL_RESET_CHIP(BV_CLKCTRL_RESET_CHIP__##e)
#define BFM_CLKCTRL_RESET_CHIP_V(v) BM_CLKCTRL_RESET_CHIP
#define BP_CLKCTRL_RESET_DIG 0
#define BM_CLKCTRL_RESET_DIG 0x1
#define BF_CLKCTRL_RESET_DIG(v) (((v) & 0x1) << 0)
#define BFM_CLKCTRL_RESET_DIG(v) BM_CLKCTRL_RESET_DIG
#define BF_CLKCTRL_RESET_DIG_V(e) BF_CLKCTRL_RESET_DIG(BV_CLKCTRL_RESET_DIG__##e)
#define BFM_CLKCTRL_RESET_DIG_V(v) BM_CLKCTRL_RESET_DIG
#define HW_CLKCTRL_VERSION HW(CLKCTRL_VERSION)
#define HWA_CLKCTRL_VERSION (0x80040000 + 0x100)
#define HWT_CLKCTRL_VERSION HWIO_32_RW
#define HWN_CLKCTRL_VERSION CLKCTRL_VERSION
#define HWI_CLKCTRL_VERSION
#define BP_CLKCTRL_VERSION_MAJOR 24
#define BM_CLKCTRL_VERSION_MAJOR 0xff000000
#define BF_CLKCTRL_VERSION_MAJOR(v) (((v) & 0xff) << 24)
#define BFM_CLKCTRL_VERSION_MAJOR(v) BM_CLKCTRL_VERSION_MAJOR
#define BF_CLKCTRL_VERSION_MAJOR_V(e) BF_CLKCTRL_VERSION_MAJOR(BV_CLKCTRL_VERSION_MAJOR__##e)
#define BFM_CLKCTRL_VERSION_MAJOR_V(v) BM_CLKCTRL_VERSION_MAJOR
#define BP_CLKCTRL_VERSION_MINOR 16
#define BM_CLKCTRL_VERSION_MINOR 0xff0000
#define BF_CLKCTRL_VERSION_MINOR(v) (((v) & 0xff) << 16)
#define BFM_CLKCTRL_VERSION_MINOR(v) BM_CLKCTRL_VERSION_MINOR
#define BF_CLKCTRL_VERSION_MINOR_V(e) BF_CLKCTRL_VERSION_MINOR(BV_CLKCTRL_VERSION_MINOR__##e)
#define BFM_CLKCTRL_VERSION_MINOR_V(v) BM_CLKCTRL_VERSION_MINOR
#define BP_CLKCTRL_VERSION_STEP 0
#define BM_CLKCTRL_VERSION_STEP 0xffff
#define BF_CLKCTRL_VERSION_STEP(v) (((v) & 0xffff) << 0)
#define BFM_CLKCTRL_VERSION_STEP(v) BM_CLKCTRL_VERSION_STEP
#define BF_CLKCTRL_VERSION_STEP_V(e) BF_CLKCTRL_VERSION_STEP(BV_CLKCTRL_VERSION_STEP__##e)
#define BFM_CLKCTRL_VERSION_STEP_V(v) BM_CLKCTRL_VERSION_STEP
#endif /* __HEADERGEN_STMP3700_CLKCTRL_H__*/
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