105 lines
4.1 KiB
C
105 lines
4.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdint.h>
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#include <stdbool.h>
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#include "clk-x1000.h"
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#include "x1000/sfc.h"
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/* SPI flash controller interface -- this is a low-level driver upon which
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* you can build NAND/NOR flash drivers. The main function is sfc_exec(),
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* used to issue commands, transfer data, etc.
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*/
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#define SFC_FLAG_READ 0x01 /* Read data */
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#define SFC_FLAG_WRITE 0x02 /* Write data */
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#define SFC_FLAG_DUMMYFIRST 0x04 /* Do dummy bits before sending address.
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* Default is dummy bits after address.
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*/
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/* SPI transfer mode. If in doubt, check with the X1000 manual and confirm
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* the transfer format is what you expect.
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*/
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#define SFC_MODE_STANDARD 0
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#define SFC_MODE_DUAL_IN_DUAL_OUT 1
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#define SFC_MODE_DUAL_IO 2
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#define SFC_MODE_FULL_DUAL_IO 3
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#define SFC_MODE_QUAD_IN_QUAD_OUT 4
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#define SFC_MODE_QUAD_IO 5
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#define SFC_MODE_FULL_QUAD_IO 6
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/* Return status codes for sfc_exec() */
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#define SFC_STATUS_OK 0
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#define SFC_STATUS_OVERFLOW 1
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#define SFC_STATUS_UNDERFLOW 2
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#define SFC_STATUS_LOCKUP 3
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typedef struct sfc_op {
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int command; /* Command number */
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int mode; /* SPI transfer mode */
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int flags; /* Flags for this op */
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int addr_bytes; /* Number of address bytes */
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int dummy_bits; /* Number of dummy bits (yes: bits, not bytes) */
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uint32_t addr_lo; /* Lower 32 bits of address */
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uint32_t addr_hi; /* Upper 32 bits of address */
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int data_bytes; /* Number of data bytes to read/write */
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void* buffer; /* Data buffer -- MUST be word-aligned */
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} sfc_op;
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/* One-time driver init for mutexes/etc needed for handling interrupts.
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* This can be safely called multiple times; only the first call will
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* actually perform the init.
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*/
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extern void sfc_init(void);
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/* Controller mutex -- lock before touching the driver */
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extern void sfc_lock(void);
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extern void sfc_unlock(void);
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/* Open/close the driver. The driver must be open in order to do operations.
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* Closing the driver shuts off the hardware; the driver can be re-opened at
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* a later time when it's needed again.
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*
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* After opening the driver, you must also program a valid device configuration
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* and clock rate using sfc_set_dev_conf() and sfc_set_clock().
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*/
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extern void sfc_open(void);
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extern void sfc_close(void);
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/* These functions can be called at any time while the driver is open, but
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* must not be called while there is an operation in progress. It's the
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* caller's job to ensure the configuration will work with the device and
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* be capable of reading back data correctly.
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*
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* - sfc_set_dev_conf() writes its argument to the SFC_DEV_CONF register.
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* - sfc_set_wp_enable() sets the state of the write-protect pin (WP).
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* - sfc_set_clock() sets the controller clock frequency (in Hz).
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*/
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#define sfc_set_dev_conf(dev_conf) \
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do { REG_SFC_DEV_CONF = (dev_conf); } while(0)
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#define sfc_set_wp_enable(en) \
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jz_writef(SFC_GLB, WP_EN((en) ? 1 : 0))
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extern void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq);
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/* Execute an operation. Returns zero on success, nonzero on failure. */
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extern int sfc_exec(const sfc_op* op);
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