478 lines
15 KiB
C
478 lines
15 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* #define LOGF_ENABLE */
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#include "i2c-x1000.h"
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#include "system.h"
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#include "kernel.h"
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#include "panic.h"
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#include "logf.h"
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#include "gpio-x1000.h"
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#include "clk-x1000.h"
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#include "irq-x1000.h"
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#include "x1000/i2c.h"
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#include "x1000/cpm.h"
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#if I2C_ASYNC_BUS_COUNT != 3
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# error "Wrong I2C_ASYNC_BUS_COUNT (should be 3)"
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#endif
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#define FIFO_SIZE 64 /* Size of data FIFOs */
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#define FIFO_TX_THRESH 16 /* Wake up when TX FIFO gets to this level */
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#define FIFO_RX_SLACK 2 /* Slack space to leave, avoids RX FIFO overflow */
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typedef struct i2c_x1000_bus {
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/* Hardware channel, this is just equal to i2c-async bus number. */
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int chn;
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/* Buffer/count usage depends on what phase the bus is processing:
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*
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* - Phase1: writing out descriptor's buffer[0] for both READs and WRITEs.
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* - Phase2: writing out descriptor's buffer[1] for WRITEs, or issuing a
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* series of read requests for READs.
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*
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* In phase1, buffer[1] and count[1] are equal to the descriptor's copy.
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* buffer[0] and count[0] get incremented/decremented as we send bytes.
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* Phase1 is only visited if we actually need to send bytes; if there
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* would be no data in this phase then __i2c_async_submit() sets up the
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* driver to go directly to phase2.
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*
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* Phase2 begins after phase1 writes out its last byte, or if phase1 was
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* skipped at submit time. For WRITEs phase2 is identical to phase1 so we
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* copy over buffer[1] and count[1] to buffer[0] and count[0], and zero
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* out buffer[1] and count[1].
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*
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* For READs phase2 sets buffer[0] to NULL and count[0] equal to count[1].
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* Now count[0] counts the number of bytes left to request, and count[1]
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* counts the number of bytes left to receive. i2c_x1000_fifo_write() sees
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* that buffer[0] is NULL and sends read requests instead of data bytes.
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* buffer[1] is advanced by i2c_x1000_fifo_read() we receive bytes.
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*/
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unsigned char* buffer[2];
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int count[2];
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bool phase1;
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/* Copied fields from descriptor */
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uint8_t bus_cond;
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uint8_t tran_mode;
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/* Counter to keep track of when to send end conditions */
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int byte_cnt;
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int byte_cnt_end;
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/* Current bus frequency, used to calculate timeout durations */
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long freq;
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/* Timeout to reset the bus in case of buggy devices */
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struct timeout tmo;
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/* Flag used to indicate a reset is processing */
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int resetting;
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} i2c_x1000_bus;
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static i2c_x1000_bus i2c_x1000_busses[3];
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static void i2c_x1000_fifo_write(i2c_x1000_bus* bus)
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{
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int tx_free, tx_n;
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/* Get free space in FIFO */
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tx_free = FIFO_SIZE - REG_I2C_TXFLR(bus->chn);
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_again:
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/* Leave some slack space when reading. If we submit a full FIFO's worth
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* of read requests, there's a small chance that a byte "on the wire" is
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* unaccounted for and causes an RX FIFO overrun. Slack space is meant to
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* avoid this situation.
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*/
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if(bus->tran_mode == I2C_READ) {
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tx_free -= FIFO_RX_SLACK;
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if(tx_free <= 0)
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goto _end;
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}
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/* Calculate number of bytes needed to send/request */
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tx_n = MIN(tx_free, bus->count[0]);
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/* Account for bytes we're about to send/request */
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bus->count[0] -= tx_n;
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tx_free -= tx_n;
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for(; tx_n > 0; --tx_n) {
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bus->byte_cnt += 1;
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/* Read data byte or set read request bit */
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uint32_t dc = bus->buffer[0] ? *bus->buffer[0]++ : jz_orm(I2C_DC, CMD);
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/* Check for first byte & apply RESTART.
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* Note the HW handles RESTART automatically when changing the
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* direction of the transfer, so we don't need to check for that.
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*/
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if(bus->byte_cnt == 1 && (bus->bus_cond & I2C_RESTART))
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dc |= jz_orm(I2C_DC, RESTART);
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/* Check for last byte & apply STOP */
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if(bus->byte_cnt == bus->byte_cnt_end && (bus->bus_cond & I2C_STOP))
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dc |= jz_orm(I2C_DC, STOP);
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/* Add entry to FIFO */
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REG_I2C_DC(bus->chn) = dc;
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}
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/* FIFO full and current phase still has data to send.
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* Configure interrupt to fire when there's a good amount of free space.
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*/
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if(bus->count[0] > 0) {
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_end:
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REG_I2C_TXTL(bus->chn) = FIFO_TX_THRESH;
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jz_writef(I2C_INTMSK(bus->chn), TXEMP(1), RXFL(0));
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return;
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}
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/* Advance to second phase if needed */
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if(bus->phase1 && bus->count[1] > 0) {
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bus->buffer[0] = bus->tran_mode == I2C_WRITE ? bus->buffer[1] : NULL;
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bus->count[0] = bus->count[1];
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bus->phase1 = false;
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/* Submit further data if possible; else wait for TX space */
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if(tx_free > 0)
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goto _again;
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else
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goto _end;
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}
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/* All phases are done. Now we just need to wake up when the whole
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* operation is complete, either by waiting for TX to drain or RX to
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* fill to the appropriate level. */
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if(bus->tran_mode == I2C_WRITE) {
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REG_I2C_TXTL(bus->chn) = 0;
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jz_writef(I2C_INTMSK(bus->chn), TXEMP(1), RXFL(0));
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} else {
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REG_I2C_RXTL(bus->chn) = bus->count[1] - 1;
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jz_writef(I2C_INTMSK(bus->chn), TXEMP(0), RXFL(1));
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}
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}
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static void i2c_x1000_fifo_read(i2c_x1000_bus* bus)
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{
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/* Get number of bytes in the RX FIFO */
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int rx_n = REG_I2C_RXFLR(bus->chn);
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/* Shouldn't happen, but check just in case */
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if(rx_n > bus->count[1]) {
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panicf("i2c_x1000(%d): expected %d bytes in RX fifo, got %d",
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bus->chn, bus->count[1], rx_n);
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}
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/* Fill buffer with data from FIFO */
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bus->count[1] -= rx_n;
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for(; rx_n != 0; --rx_n) {
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*bus->buffer[1]++ = jz_readf(I2C_DC(bus->chn), DAT);
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}
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}
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static void i2c_x1000_interrupt(i2c_x1000_bus* bus)
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{
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int intr = REG_I2C_INTST(bus->chn);
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int status = I2C_STATUS_OK;
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/* Bus error; we can't prevent this from happening. As I understand
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* it, we cannot get a TXABT when the bus is idle, so it should be
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* safe to leave this interrupt unmasked all the time.
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*/
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if(intr & jz_orm(I2C_INTST, TXABT)) {
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logf("i2c_x1000(%d): got TXABT (%08lx)",
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bus->chn, REG_I2C_ABTSRC(bus->chn));
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REG_I2C_CTXABT(bus->chn);
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status = I2C_STATUS_ERROR;
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goto _done;
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}
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/* FIFO errors shouldn't occur unless driver did something dumb */
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if(intr & jz_orm(I2C_INTST, RXUF, TXOF, RXOF)) {
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#if 1
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panicf("i2c_x1000(%d): fifo error (%08x)", bus->chn, intr);
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#else
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/* This is how the error condition would be cleared */
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REG_I2C_CTXOF(bus->chn);
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REG_I2C_CRXOF(bus->chn);
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REG_I2C_CRXUF(bus->chn);
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status = I2C_STATUS_ERROR;
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goto _done;
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#endif
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}
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/* Read from FIFO on reads, and check if we have sent/received
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* the expected amount of data. If so, complete the descriptor. */
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if(bus->tran_mode == I2C_READ) {
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i2c_x1000_fifo_read(bus);
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if(bus->count[1] == 0)
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goto _done;
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} else if(bus->count[0] == 0) {
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goto _done;
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}
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/* Still need to send or request data -- issue commands to FIFO */
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i2c_x1000_fifo_write(bus);
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return;
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_done:
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jz_writef(I2C_INTMSK(bus->chn), TXEMP(0), RXFL(0));
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timeout_cancel(&bus->tmo);
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__i2c_async_complete_callback(bus->chn, status);
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}
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void I2C0(void)
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{
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i2c_x1000_interrupt(&i2c_x1000_busses[0]);
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}
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void I2C1(void)
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{
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i2c_x1000_interrupt(&i2c_x1000_busses[1]);
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}
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void I2C2(void)
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{
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i2c_x1000_interrupt(&i2c_x1000_busses[2]);
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}
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static int i2c_x1000_bus_timeout(struct timeout* tmo)
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{
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/* Buggy device is preventing the operation from completing, so we
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* can't do much except reset the bus and hope for the best. Device
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* drivers can aid us by detecting the TIMEOUT status we return and
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* resetting the device to get it out of a bugged state. */
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i2c_x1000_bus* bus = (i2c_x1000_bus*)tmo->data;
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switch(bus->resetting) {
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default:
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/* Start of reset. Disable the controller */
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REG_I2C_INTMSK(bus->chn) = 0;
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bus->resetting = 1;
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jz_writef(I2C_ENABLE(bus->chn), ACTIVE(0));
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return 1;
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case 1:
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/* Check if controller is disabled yet */
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if(jz_readf(I2C_ENBST(bus->chn), ACTIVE))
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return 1;
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/* Wait 10 ms after disabling to give time for bus to clear */
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bus->resetting = 2;
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return HZ/100;
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case 2:
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/* Re-enable the controller */
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bus->resetting = 3;
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jz_writef(I2C_ENABLE(bus->chn), ACTIVE(1));
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return 1;
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case 3:
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/* Check that controller is enabled */
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if(jz_readf(I2C_ENBST(bus->chn), ACTIVE) == 0)
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return 1;
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/* Reset complete */
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bus->resetting = 0;
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jz_overwritef(I2C_INTMSK(bus->chn), RXFL(0), TXEMP(0),
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TXABT(1), TXOF(1), RXOF(1), RXUF(1));
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__i2c_async_complete_callback(bus->chn, I2C_STATUS_TIMEOUT);
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return 0;
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}
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}
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void __i2c_async_submit(int busnr, i2c_descriptor* desc)
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{
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i2c_x1000_bus* bus = &i2c_x1000_busses[busnr];
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if(desc->tran_mode == I2C_READ) {
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if(desc->count[0] > 0) {
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/* Handle initial write as phase1 */
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bus->buffer[0] = desc->buffer[0];
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bus->count[0] = desc->count[0];
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bus->phase1 = true;
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} else {
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/* No initial write, skip directly to phase2 */
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bus->buffer[0] = NULL;
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bus->count[0] = desc->count[1];
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bus->phase1 = false;
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}
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/* Set buffer/count for phase2 read */
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bus->buffer[1] = desc->buffer[1];
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bus->count[1] = desc->count[1];
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} else {
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/* Writes always have to have buffer[0] populated; buffer[1] is
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* allowed to be NULL (and thus count[1] = 0). This matches our
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* phase logic so no need for anything special
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*/
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bus->buffer[0] = desc->buffer[0];
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bus->count[0] = desc->count[0];
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bus->buffer[1] = desc->buffer[1];
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bus->count[1] = desc->count[1];
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bus->phase1 = true;
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}
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/* Save bus condition and transfer mode */
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bus->bus_cond = desc->bus_cond;
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bus->tran_mode = desc->tran_mode;
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/* Byte counter is used to check for first and last byte and apply
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* the requested end mode */
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bus->byte_cnt = 0;
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bus->byte_cnt_end = desc->count[0] + desc->count[1];
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/* Ensure interrupts are cleared */
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REG_I2C_CINT(busnr);
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/* Program target address */
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jz_overwritef(I2C_TAR(busnr), ADDR(desc->slave_addr & ~I2C_10BIT_ADDR),
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10BITS(desc->slave_addr & I2C_10BIT_ADDR ? 1 : 0));
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/* Do the initial FIFO fill; this sets up the needed interrupts. */
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i2c_x1000_fifo_write(bus);
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/* Software timeout to deal with buggy slave devices that pull the bus
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* high forever and leave us hanging. Use 100ms + whatever time should
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* be needed to handle data transmission. Account for 9 bits per byte
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* because of the ACKs necessary after each byte.
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*/
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long ticks = (HZ/10) + (HZ * 9 * bus->byte_cnt_end / bus->freq);
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timeout_register(&bus->tmo, i2c_x1000_bus_timeout, ticks, (intptr_t)bus);
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}
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void i2c_init(void)
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{
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/* Initialize core */
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__i2c_async_init();
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/* Initialize our bus data structures */
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for(int i = 0; i < 3; ++i) {
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i2c_x1000_busses[i].chn = i;
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i2c_x1000_busses[i].freq = 0;
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i2c_x1000_busses[i].resetting = 0;
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}
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}
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/* Stuff only required during initialization is below, basically the same as
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* the old driver except for how the IRQs are initially set up. */
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static const struct {
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int port;
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unsigned pins;
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int func;
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} i2c_x1000_gpio_data[] = {
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{GPIO_B, 3 << 23, GPIO_DEVICE(0)},
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{GPIO_C, 3 << 26, GPIO_DEVICE(0)},
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/* Note: I2C1 is also on the following pins (normally used by LCD) */
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/* {GPIO_A, 3 << 0, GPIO_DEVICE(2)}, */
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{GPIO_D, 3 << 0, GPIO_DEVICE(1)},
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};
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static void i2c_x1000_gate(int chn, int gate)
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{
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switch(chn) {
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case 0: jz_writef(CPM_CLKGR, I2C0(gate)); break;
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case 1: jz_writef(CPM_CLKGR, I2C1(gate)); break;
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case 2: jz_writef(CPM_CLKGR, I2C2(gate)); break;
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default: break;
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}
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}
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static void i2c_x1000_enable(int chn)
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{
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/* Enable controller */
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jz_writef(I2C_ENABLE(chn), ACTIVE(1));
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while(jz_readf(I2C_ENBST(chn), ACTIVE) == 0);
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/* Set up interrutpts */
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jz_overwritef(I2C_INTMSK(chn), RXFL(0), TXEMP(0),
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TXABT(1), TXOF(1), RXOF(1), RXUF(1));
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system_enable_irq(IRQ_I2C(chn));
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}
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static void i2c_x1000_disable(int chn)
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{
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/* Disable interrupts */
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system_disable_irq(IRQ_I2C(chn));
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REG_I2C_INTMSK(chn) = 0;
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/* Disable controller */
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jz_writef(I2C_ENABLE(chn), ACTIVE(0));
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while(jz_readf(I2C_ENBST(chn), ACTIVE));
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}
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void i2c_x1000_set_freq(int chn, int freq)
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{
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/* Store frequency */
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i2c_x1000_busses[chn].freq = freq;
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/* Disable the channel if previously active */
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i2c_x1000_gate(chn, 0);
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if(jz_readf(I2C_ENBST(chn), ACTIVE) == 1)
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i2c_x1000_disable(chn);
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/* Request to shut down the channel */
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if(freq == 0) {
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i2c_x1000_gate(chn, 1);
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return;
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}
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/* Calculate timing parameters */
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unsigned pclk = clk_get(X1000_CLK_PCLK);
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unsigned t_SU_DAT = pclk / (freq * 8);
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unsigned t_HD_DAT = pclk / (freq * 12);
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unsigned t_LOW = pclk / (freq * 2);
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unsigned t_HIGH = pclk / (freq * 2);
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if(t_SU_DAT > 1) t_SU_DAT -= 1;
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if(t_SU_DAT > 255) t_SU_DAT = 255;
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if(t_SU_DAT == 0) t_SU_DAT = 0;
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if(t_HD_DAT > 0xffff) t_HD_DAT = 0xfff;
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if(t_LOW < 8) t_LOW = 8;
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if(t_HIGH < 6) t_HIGH = 6;
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/* Control register setting */
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unsigned reg = jz_orf(I2C_CON, SLVDIS(1), RESTART(1), MD(1));
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if(freq <= I2C_FREQ_100K)
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reg |= jz_orf(I2C_CON, SPEED_V(100K));
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else
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reg |= jz_orf(I2C_CON, SPEED_V(400K));
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/* Write the new controller settings */
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jz_write(I2C_CON(chn), reg);
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jz_write(I2C_SDASU(chn), t_SU_DAT);
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jz_write(I2C_SDAHD(chn), t_HD_DAT);
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|
if(freq <= I2C_FREQ_100K) {
|
|
jz_write(I2C_SLCNT(chn), t_LOW);
|
|
jz_write(I2C_SHCNT(chn), t_HIGH);
|
|
} else {
|
|
jz_write(I2C_FLCNT(chn), t_LOW);
|
|
jz_write(I2C_FHCNT(chn), t_HIGH);
|
|
}
|
|
|
|
/* Claim pins */
|
|
gpio_config(i2c_x1000_gpio_data[chn].port,
|
|
i2c_x1000_gpio_data[chn].pins,
|
|
i2c_x1000_gpio_data[chn].func);
|
|
|
|
/* Enable the controller */
|
|
i2c_x1000_enable(chn);
|
|
}
|