9f950d8bbf
This new design saves on binary size and stack usage. The API is also block- and page-based, requiring awareness of the chip layout to use properly. Out-of-band areas are also exposed for reading and writing. The byte-oriented routines are kept for compatibility with the existing installer and SPL. Change-Id: Iaacc694d2f651ab74d45330e0434ee778a0d91bc
125 lines
4.2 KiB
C
125 lines
4.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __SFC_X1000_H__
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#define __SFC_X1000_H__
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#include "x1000/sfc.h"
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#include <stdint.h>
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#include <stdbool.h>
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/* SPI transfer mode. SFC_TMODE_X_Y_Z means:
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*
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* - X lines for command phase
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* - Y lines for address+dummy phase
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* - Z lines for data phase
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*/
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#define SFC_TMODE_1_1_1 0
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#define SFC_TMODE_1_1_2 1
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#define SFC_TMODE_1_2_2 2
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#define SFC_TMODE_2_2_2 3
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#define SFC_TMODE_1_1_4 4
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#define SFC_TMODE_1_4_4 5
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#define SFC_TMODE_4_4_4 6
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/* Phase format
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* _____________________
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* / SFC_PFMT_ADDR_FIRST \
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* +-----+-------+-------+------+
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* | cmd | addr | dummy | data |
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* +-----+-------+-------+------+
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* ______________________
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* / SFC_PFMT_DUMMY_FIRST \
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* +-----+-------+-------+------+
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* | cmd | dummy | addr | data |
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* +-----+-------+-------+------+
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*/
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#define SFC_PFMT_ADDR_FIRST 0
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#define SFC_PFMT_DUMMY_FIRST 1
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/* Direction of transfer flag */
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#define SFC_READ 0
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#define SFC_WRITE (1 << 31)
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/** \brief Macro to generate an SFC command for use with sfc_exec()
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* \param cmd Command number (up to 16 bits)
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* \param tmode SPI transfer mode
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* \param awidth Number of address bytes
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* \param dwidth Number of dummy cycles (1 cycle = 1 bit)
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* \param pfmt Phase format (address first or dummy first)
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* \param data_en 1 to enable data phase, 0 to omit it
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*/
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#define SFC_CMD(cmd, tmode, awidth, dwidth, pfmt, data_en) \
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jz_orf(SFC_TRAN_CONF, COMMAND(cmd), CMD_EN(1), \
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MODE(tmode), ADDR_WIDTH(awidth), DUMMY_BITS(dwidth), \
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PHASE_FMT(pfmt), DATA_EN(data_en))
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/* Open/close SFC hardware */
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extern void sfc_open(void);
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extern void sfc_close(void);
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/* Enable IRQ mode, instead of busy waiting for operations to complete.
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* Needs to be called separately after sfc_open(), because the SPL has to
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* use busy waiting, but we cannot #ifdef it for the SPL due to limitations
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* of the build system. */
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extern void sfc_irq_begin(void);
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extern void sfc_irq_end(void);
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/* Change the SFC clock frequency */
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extern void sfc_set_clock(uint32_t freq);
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/* Set the device configuration register */
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inline void sfc_set_dev_conf(uint32_t conf)
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{
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REG_SFC_DEV_CONF = conf;
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}
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/* Control the state of the write protect pin */
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inline void sfc_set_wp_enable(bool en)
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{
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jz_writef(SFC_GLB, WP_EN(en ? 1 : 0));
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}
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/** \brief Execute a command
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* \param cmd Command encoded by `SFC_CMD` macro.
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* \param addr Address up to 32 bits; pass 0 if the command doesn't need it
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* \param data Buffer for data transfer commands, must be cache-aligned
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* \param size Number of data bytes / direction of transfer flag
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* \returns SFC status code: 0 on success and < 0 on failure.
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*
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* - Non-data commands must pass `data = NULL` and `size = 0` in order to
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* get correct results.
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*
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* - Data commands must specify a direction of transfer using the high bit
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* of the `size` argument by OR'ing in `SFC_READ` or `SFC_WRITE`.
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*/
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extern void sfc_exec(uint32_t cmd, uint32_t addr, void* data, uint32_t size);
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/* NOTE: the above will need to be changed if we need better performance
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* The hardware can do multiple commands in a sequence, including polling,
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* and emit an interrupt only at the end.
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*
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* Also, some chips need more than 4 address bytes even though the block
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* and page numbers would still fit in 32 bits; the current API cannot
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* handle this.
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*/
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#endif /* __SFC_X1000_H__ */
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