0a1d7c28b7
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25844 a1c6a512-1295-4272-9138-f99709370657
1006 lines
23 KiB
C
1006 lines
23 KiB
C
#include "rockmacros.h"
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#include "defs.h"
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#include "regs.h"
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#include "hw.h"
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#include "cpu-gb.h"
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#include "lcdc.h"
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#include "mem.h"
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#include "fastmem.h"
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#include "cpuregs.h"
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#include "cpucore.h"
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#ifdef USE_ASM
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#include "asm.h"
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#endif
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struct cpu cpu IBSS_ATTR;
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#define ZFLAG(n) ( (n) ? 0 : FZ )
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#define PUSH(w) ( (SP -= 2), (writew(xSP, (w))) )
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#define POP(w) ( ((w) = readw(xSP)), (SP += 2) )
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#define FETCH (readb(PC++))
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#define INC(r) { ((r)++); \
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F = (F & (FL|FC)) | incflag_table[(r)]; }
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#define DEC(r) { ((r)--); \
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F = (F & (FL|FC)) | decflag_table[(r)]; }
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#define INCW(r) ( (r)++ )
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#define DECW(r) ( (r)-- )
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#define ADD(n) { \
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W(acc) = (un32)A + (un32)(n); \
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F = (ZFLAG(LB(acc))) \
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| (FH & ((A ^ (n) ^ LB(acc)) << 1)) \
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| (HB(acc) << 4); \
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A = LB(acc); }
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#define ADC(n) { \
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W(acc) = (un32)A + (un32)(n) + (un32)((F&FC)>>4); \
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F = (ZFLAG(LB(acc))) \
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| (FH & ((A ^ (n) ^ LB(acc)) << 1)) \
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| (HB(acc) << 4); \
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A = LB(acc); }
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#define ADDW(n) { \
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DW(acc) = (un32)HL + (un32)(n); \
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F = (F & (FZ)) \
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| (FH & ((H ^ ((n)>>8) ^ HB(acc)) << 1)) \
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| (acc.b[HI][LO] << 4); \
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HL = W(acc); }
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#define ADDSP(n) { \
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DW(acc) = (un32)SP + (un32)(n8)(n); \
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F = (FH & (((SP>>8) ^ ((n)>>8) ^ HB(acc)) << 1)) \
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| (acc.b[HI][LO] << 4); \
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SP = W(acc); }
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#define LDHLSP(n) { \
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DW(acc) = (un32)SP + (un32)(n8)(n); \
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F = (FH & (((SP>>8) ^ ((n)>>8) ^ HB(acc)) << 1)) \
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| (acc.b[HI][LO] << 4); \
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HL = W(acc); }
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#define CP(n) { \
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W(acc) = (un32)A - (un32)(n); \
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F = FN \
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| (ZFLAG(LB(acc))) \
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| (FH & ((A ^ (n) ^ LB(acc)) << 1)) \
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| ((un8)(-(n8)HB(acc)) << 4); }
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#define SUB(n) { CP((n)); A = LB(acc); }
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#define SBC(n) { \
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W(acc) = (un32)A - (un32)(n) - (un32)((F&FC)>>4); \
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F = FN \
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| (ZFLAG((n8)LB(acc))) \
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| (FH & ((A ^ (n) ^ LB(acc)) << 1)) \
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| ((un8)(-(n8)HB(acc)) << 4); \
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A = LB(acc); }
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#define AND(n) { A &= (n); \
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F = ZFLAG(A) | FH; }
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#define XOR(n) { A ^= (n); \
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F = ZFLAG(A); }
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#define OR(n) { A |= (n); \
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F = ZFLAG(A); }
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#define RLCA(r) { (r) = ((r)>>7) | ((r)<<1); \
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F = (((r)&0x01)<<4); }
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#define RRCA(r) { (r) = ((r)<<7) | ((r)>>1); \
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F = (((r)&0x80)>>3); }
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#define RLA(r) { \
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LB(acc) = (((r)&0x80)>>3); \
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(r) = ((r)<<1) | ((F&FC)>>4); \
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F = LB(acc); }
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#define RRA(r) { \
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LB(acc) = (((r)&0x01)<<4); \
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(r) = ((r)>>1) | ((F&FC)<<3); \
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F = LB(acc); }
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#define RLC(r) { RLCA(r); F |= ZFLAG(r); }
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#define RRC(r) { RRCA(r); F |= ZFLAG(r); }
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#define RL(r) { RLA(r); F |= ZFLAG(r); }
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#define RR(r) { RRA(r); F |= ZFLAG(r); }
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#define SLA(r) { \
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LB(acc) = (((r)&0x80)>>3); \
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(r) <<= 1; \
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F = ZFLAG((r)) | LB(acc); }
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#define SRA(r) { \
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LB(acc) = (((r)&0x01)<<4); \
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(r) = (un8)(((n8)(r))>>1); \
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F = ZFLAG((r)) | LB(acc); }
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#define SRL(r) { \
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LB(acc) = (((r)&0x01)<<4); \
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(r) >>= 1; \
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F = ZFLAG((r)) | LB(acc); }
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#define CPL(r) { \
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(r) = ~(r); \
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F |= (FH|FN); }
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#define SCF { F = (F & (FZ)) | FC; }
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#define CCF { F = (F & (FZ|FC)) ^ FC; }
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#define DAA { \
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A += (LB(acc) = daa_table[((((int)F)&0x70)<<4) | A]); \
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F = (F & (FN)) | ZFLAG(A) | daa_carry_table[LB(acc)>>2]; }
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#define SWAP(r) { \
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(r) = swap_table[(r)]; \
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F = ZFLAG((r)); }
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#define BIT(n,r) { F = (F & FC) | ZFLAG(((r) & BIT_N(n))) | FH; }
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#define RES(n,r) { (r) &= ~BIT_N(n); }
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#define SET(n,r) { (r) |= BIT_N(n); }
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#define CB_REG_CASES(r, n) \
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case 0x00|(n): RLC(r); break; \
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case 0x08|(n): RRC(r); break; \
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case 0x10|(n): RL(r); break; \
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case 0x18|(n): RR(r); break; \
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case 0x20|(n): SLA(r); break; \
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case 0x28|(n): SRA(r); break; \
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case 0x30|(n): SWAP(r); break; \
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case 0x38|(n): SRL(r); break; \
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case 0x40|(n): BIT(0, r); break; \
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case 0x48|(n): BIT(1, r); break; \
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case 0x50|(n): BIT(2, r); break; \
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case 0x58|(n): BIT(3, r); break; \
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case 0x60|(n): BIT(4, r); break; \
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case 0x68|(n): BIT(5, r); break; \
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case 0x70|(n): BIT(6, r); break; \
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case 0x78|(n): BIT(7, r); break; \
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case 0x80|(n): RES(0, r); break; \
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case 0x88|(n): RES(1, r); break; \
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case 0x90|(n): RES(2, r); break; \
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case 0x98|(n): RES(3, r); break; \
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case 0xA0|(n): RES(4, r); break; \
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case 0xA8|(n): RES(5, r); break; \
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case 0xB0|(n): RES(6, r); break; \
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case 0xB8|(n): RES(7, r); break; \
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case 0xC0|(n): SET(0, r); break; \
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case 0xC8|(n): SET(1, r); break; \
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case 0xD0|(n): SET(2, r); break; \
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case 0xD8|(n): SET(3, r); break; \
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case 0xE0|(n): SET(4, r); break; \
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case 0xE8|(n): SET(5, r); break; \
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case 0xF0|(n): SET(6, r); break; \
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case 0xF8|(n): SET(7, r); break;
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#define ALU_CASES(base, imm, op, label) \
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case (imm): b = FETCH; goto label; \
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case (base): b = B; goto label; \
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case (base)+1: b = C; goto label; \
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case (base)+2: b = D; goto label; \
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case (base)+3: b = E; goto label; \
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case (base)+4: b = H; goto label; \
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case (base)+5: b = L; goto label; \
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case (base)+6: b = readb(HL); goto label; \
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case (base)+7: b = A; \
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label: op(b); break;
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#define JR ( PC += 1+(n8)readb(PC) )
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#define JP ( PC = readw(PC) )
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#define CALL ( PUSH(PC+2), JP )
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#define NOJR ( clen--, PC++ )
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#define NOJP ( clen--, PC+=2 )
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#define NOCALL ( clen-=3, PC+=2 )
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#define NORET ( clen-=3 )
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#define RST(n) { PUSH(PC); PC = (n); }
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#define RET ( POP(PC) )
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#define EI ( IMA = 1 )
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#define DI ( IMA = IME = 0 )
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#define PRE_INT ( DI, PUSH(PC) )
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#define THROW_INT(n) ( (IF &= ~BIT_N(n)), (PC = 0x40+((n)<<3)) )
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#ifdef DYNAREC
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un32 reg_backup[16];
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struct dynarec_block *address_map[1<<HASH_SIGNIFICANT_LOWER_BITS];
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extern void *dynapointer;
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int blockcount;
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#define MAXBLOCK 6
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#endif
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void cpu_reset(void)
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{
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union reg acc;
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#ifdef DYNAREC
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int i;
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dynapointer=0;
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#endif
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cpu.speed = 0;
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cpu.halt = 0;
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cpu.div = 0;
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cpu.tim = 0;
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cpu.lcdc = 40;
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IME = 0;
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IMA = 0;
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PC = 0x0100;
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SP = 0xFFFE;
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W(acc) = 0x01B0;
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A=HB(acc);
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F=LB(acc);
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W(acc) = 0x0013;
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B=HB(acc);
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C=LB(acc);
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W(acc) = 0x00D8;
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D=HB(acc);
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E=LB(acc);
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HL = 0x014D;
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if (hw.cgb) A = 0x11;
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#ifdef DYNAREC
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for(i=0;i<(1<<HASH_SIGNIFICANT_LOWER_BITS);i++)
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address_map[i]=0;
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#endif
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}
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static void div_advance(int cnt) ICODE_ATTR;
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static void div_advance(int cnt)
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{
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cpu.div += (cnt<<1);
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if (cpu.div >> 8)
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{
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R_DIV += (cpu.div >> 8);
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cpu.div &= 0xff;
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}
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}
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static void timer_advance(int cnt) ICODE_ATTR;
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static void timer_advance(int cnt)
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{
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int unit, tima;
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if (!(R_TAC & 0x04)) return;
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unit = ((-R_TAC) & 3) << 1;
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cpu.tim += (cnt<<unit);
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if (cpu.tim >> 9)
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{
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tima = R_TIMA + (cpu.tim >> 9);
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cpu.tim &= 0x1ff;
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if (tima >> 8)
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{
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hw_interrupt(IF_TIMER, IF_TIMER);
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hw_interrupt(0, IF_TIMER);
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}
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while (tima >> 8)
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tima = tima - 256 + R_TMA;
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R_TIMA = tima;
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}
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}
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static void lcdc_advance(int cnt) ICODE_ATTR;
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static void lcdc_advance(int cnt)
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{
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cpu.lcdc -= cnt;
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if (cpu.lcdc <= 0) lcdc_trans();
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}
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static void sound_advance(int cnt) ICODE_ATTR;
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static void sound_advance(int cnt)
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{
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cpu.snd += cnt;
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}
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void cpu_timers(int cnt)
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{
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div_advance(cnt << cpu.speed);
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timer_advance(cnt << cpu.speed);
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lcdc_advance(cnt);
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if(options.sound)
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sound_advance(cnt);
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}
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static int cpu_idle(int max)
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{
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int cnt, unit;
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if (!(cpu.halt && IME)) return 0;
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if (R_IF & R_IE)
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{
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cpu.halt = 0;
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return 0;
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}
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/* Make sure we don't miss lcdc status events! */
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if ((R_IE & (IF_VBLANK | IF_STAT)) && (max > cpu.lcdc))
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max = cpu.lcdc;
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/* If timer interrupt cannot happen, this is very simple! */
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if (!((R_IE & IF_TIMER) && (R_TAC & 0x04)))
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{
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cpu_timers(max);
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return max;
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}
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/* Figure out when the next timer interrupt will happen */
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unit = ((-R_TAC) & 3) << 1;
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cnt = (511 - cpu.tim + BIT_N(unit)) >> unit;
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cnt += (255 - R_TIMA) << (9 - unit);
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if (max < cnt)
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cnt = max;
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cpu_timers(cnt);
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return cnt;
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}
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#ifndef ASM_CPU_EMULATE
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extern int debug_trace;
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int cpu_emulate(int cycles)
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{
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int i;
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static byte op IBSS_ATTR;
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static byte cbop IBSS_ATTR;
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int clen;
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static union reg acc IBSS_ATTR;
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static byte b IBSS_ATTR;
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static word w IBSS_ATTR;
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i = cycles;
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next:
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#ifdef DYNAREC
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if(shut)
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return cycles-i;
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#endif
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if ((clen = cpu_idle(i)))
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{
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i -= clen;
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if (i > 0) goto next;
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return cycles-i;
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}
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if (IME && (IF & IE))
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{
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PRE_INT;
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switch ((byte)(IF & IE))
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{
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case 0x01: case 0x03: case 0x05: case 0x07:
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case 0x09: case 0x0B: case 0x0D: case 0x0F:
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case 0x11: case 0x13: case 0x15: case 0x17:
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case 0x19: case 0x1B: case 0x1D: case 0x1F:
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THROW_INT(0); break;
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case 0x02: case 0x06: case 0x0A: case 0x0E:
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case 0x12: case 0x16: case 0x1A: case 0x1E:
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THROW_INT(1); break;
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case 0x04: case 0x0C: case 0x14: case 0x1C:
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THROW_INT(2); break;
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case 0x08: case 0x18:
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THROW_INT(3); break;
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case 0x10:
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THROW_INT(4); break;
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}
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}
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IME = IMA;
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/* if (debug_trace) debug_disassemble(PC, 1); */
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#ifdef DYNAREC
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if(PC&0x8000) {
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#endif
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op = FETCH;
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clen = cycles_table[op];
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switch(op)
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{
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case 0x00: /* NOP */
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case 0x40: /* LD B,B */
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case 0x49: /* LD C,C */
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case 0x52: /* LD D,D */
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case 0x5B: /* LD E,E */
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case 0x64: /* LD H,H */
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case 0x6D: /* LD L,L */
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case 0x7F: /* LD A,A */
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break;
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case 0x41: /* LD B,C */
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B = C; break;
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case 0x42: /* LD B,D */
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B = D; break;
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case 0x43: /* LD B,E */
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B = E; break;
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case 0x44: /* LD B,H */
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B = H; break;
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case 0x45: /* LD B,L */
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B = L; break;
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case 0x46: /* LD B,(HL) */
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B = readb(xHL); break;
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case 0x47: /* LD B,A */
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B = A; break;
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case 0x48: /* LD C,B */
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C = B; break;
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case 0x4A: /* LD C,D */
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C = D; break;
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case 0x4B: /* LD C,E */
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C = E; break;
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case 0x4C: /* LD C,H */
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C = H; break;
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case 0x4D: /* LD C,L */
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C = L; break;
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case 0x4E: /* LD C,(HL) */
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C = readb(xHL); break;
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case 0x4F: /* LD C,A */
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C = A; break;
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case 0x50: /* LD D,B */
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D = B; break;
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case 0x51: /* LD D,C */
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D = C; break;
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case 0x53: /* LD D,E */
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D = E; break;
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case 0x54: /* LD D,H */
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D = H; break;
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case 0x55: /* LD D,L */
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D = L; break;
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case 0x56: /* LD D,(HL) */
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D = readb(xHL); break;
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case 0x57: /* LD D,A */
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D = A; break;
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case 0x58: /* LD E,B */
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E = B; break;
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case 0x59: /* LD E,C */
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E = C; break;
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case 0x5A: /* LD E,D */
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E = D; break;
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case 0x5C: /* LD E,H */
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E = H; break;
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case 0x5D: /* LD E,L */
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E = L; break;
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case 0x5E: /* LD E,(HL) */
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E = readb(xHL); break;
|
|
case 0x5F: /* LD E,A */
|
|
E = A; break;
|
|
|
|
case 0x60: /* LD H,B */
|
|
H = B; break;
|
|
case 0x61: /* LD H,C */
|
|
H = C; break;
|
|
case 0x62: /* LD H,D */
|
|
H = D; break;
|
|
case 0x63: /* LD H,E */
|
|
H = E; break;
|
|
case 0x65: /* LD H,L */
|
|
H = L; break;
|
|
case 0x66: /* LD H,(HL) */
|
|
H = readb(xHL); break;
|
|
case 0x67: /* LD H,A */
|
|
H = A; break;
|
|
|
|
case 0x68: /* LD L,B */
|
|
L = B; break;
|
|
case 0x69: /* LD L,C */
|
|
L = C; break;
|
|
case 0x6A: /* LD L,D */
|
|
L = D; break;
|
|
case 0x6B: /* LD L,E */
|
|
L = E; break;
|
|
case 0x6C: /* LD L,H */
|
|
L = H; break;
|
|
case 0x6E: /* LD L,(HL) */
|
|
L = readb(xHL); break;
|
|
case 0x6F: /* LD L,A */
|
|
L = A; break;
|
|
|
|
case 0x70: /* LD (HL),B */
|
|
b = B; goto __LD_HL;
|
|
case 0x71: /* LD (HL),C */
|
|
b = C; goto __LD_HL;
|
|
case 0x72: /* LD (HL),D */
|
|
b = D; goto __LD_HL;
|
|
case 0x73: /* LD (HL),E */
|
|
b = E; goto __LD_HL;
|
|
case 0x74: /* LD (HL),H */
|
|
b = H; goto __LD_HL;
|
|
case 0x75: /* LD (HL),L */
|
|
b = L; goto __LD_HL;
|
|
case 0x77: /* LD (HL),A */
|
|
b = A;
|
|
__LD_HL:
|
|
writeb(xHL,b);
|
|
break;
|
|
|
|
case 0x78: /* LD A,B */
|
|
A = B; break;
|
|
case 0x79: /* LD A,C */
|
|
A = C; break;
|
|
case 0x7A: /* LD A,D */
|
|
A = D; break;
|
|
case 0x7B: /* LD A,E */
|
|
A = E; break;
|
|
case 0x7C: /* LD A,H */
|
|
A = H; break;
|
|
case 0x7D: /* LD A,L */
|
|
A = L; break;
|
|
case 0x7E: /* LD A,(HL) */
|
|
A = readb(xHL); break;
|
|
|
|
case 0x01: /* LD BC,imm */
|
|
#ifdef DYNAREC
|
|
W(acc) = readw(xPC);
|
|
B=HB(acc);
|
|
C=LB(acc);
|
|
#else
|
|
BC = readw(xPC);
|
|
#endif
|
|
PC += 2;
|
|
break;
|
|
case 0x11: /* LD DE,imm */
|
|
#ifdef DYNAREC
|
|
W(acc) = readw(xPC);
|
|
D=HB(acc);
|
|
E=LB(acc);
|
|
#else
|
|
DE = readw(xPC);
|
|
#endif
|
|
PC += 2;
|
|
break;
|
|
case 0x21: /* LD HL,imm */
|
|
HL = readw(xPC); PC += 2; break;
|
|
case 0x31: /* LD SP,imm */
|
|
SP = readw(xPC); PC += 2; break;
|
|
|
|
case 0x02: /* LD (BC),A */
|
|
writeb(xBC, A); break;
|
|
case 0x0A: /* LD A,(BC) */
|
|
A = readb(xBC); break;
|
|
case 0x12: /* LD (DE),A */
|
|
writeb(xDE, A); break;
|
|
case 0x1A: /* LD A,(DE) */
|
|
A = readb(xDE); break;
|
|
|
|
case 0x22: /* LDI (HL),A */
|
|
writeb(xHL, A); HL++; break;
|
|
case 0x2A: /* LDI A,(HL) */
|
|
A = readb(xHL); HL++; break;
|
|
case 0x32: /* LDD (HL),A */
|
|
writeb(xHL, A); HL--; break;
|
|
case 0x3A: /* LDD A,(HL) */
|
|
A = readb(xHL); HL--; break;
|
|
|
|
case 0x06: /* LD B,imm */
|
|
B = FETCH; break;
|
|
case 0x0E: /* LD C,imm */
|
|
C = FETCH; break;
|
|
case 0x16: /* LD D,imm */
|
|
D = FETCH; break;
|
|
case 0x1E: /* LD E,imm */
|
|
E = FETCH; break;
|
|
case 0x26: /* LD H,imm */
|
|
H = FETCH; break;
|
|
case 0x2E: /* LD L,imm */
|
|
L = FETCH; break;
|
|
case 0x36: /* LD (HL),imm */
|
|
b = FETCH; writeb(xHL, b); break;
|
|
case 0x3E: /* LD A,imm */
|
|
A = FETCH; break;
|
|
|
|
case 0x08: /* LD (imm),SP */
|
|
writew(readw(xPC), SP); PC += 2; break;
|
|
case 0xEA: /* LD (imm),A */
|
|
writeb(readw(xPC), A); PC += 2; break;
|
|
|
|
case 0xE0: /* LDH (imm),A */
|
|
writehi(FETCH, A); break;
|
|
case 0xE2: /* LDH (C),A */
|
|
writehi(C, A); break;
|
|
case 0xF0: /* LDH A,(imm) */
|
|
A = readhi(FETCH); break;
|
|
case 0xF2: /* LDH A,(C) (undocumented) */
|
|
A = readhi(C); break;
|
|
|
|
|
|
case 0xF8: /* LD HL,SP+imm */
|
|
b = FETCH; LDHLSP(b); break;
|
|
case 0xF9: /* LD SP,HL */
|
|
SP = HL; break;
|
|
case 0xFA: /* LD A,(imm) */
|
|
A = readb(readw(xPC)); PC += 2; break;
|
|
|
|
ALU_CASES(0x80, 0xC6, ADD, __ADD)
|
|
ALU_CASES(0x88, 0xCE, ADC, __ADC)
|
|
ALU_CASES(0x90, 0xD6, SUB, __SUB)
|
|
ALU_CASES(0x98, 0xDE, SBC, __SBC)
|
|
ALU_CASES(0xA0, 0xE6, AND, __AND)
|
|
ALU_CASES(0xA8, 0xEE, XOR, __XOR)
|
|
ALU_CASES(0xB0, 0xF6, OR, __OR)
|
|
ALU_CASES(0xB8, 0xFE, CP, __CP)
|
|
|
|
case 0x09: /* ADD HL,BC */
|
|
w = BC; goto __ADDW;
|
|
case 0x19: /* ADD HL,DE */
|
|
w = DE; goto __ADDW;
|
|
case 0x39: /* ADD HL,SP */
|
|
w = SP; goto __ADDW;
|
|
case 0x29: /* ADD HL,HL */
|
|
w = HL;
|
|
__ADDW:
|
|
ADDW(w);
|
|
break;
|
|
|
|
case 0x04: /* INC B */
|
|
INC(B); break;
|
|
case 0x0C: /* INC C */
|
|
INC(C); break;
|
|
case 0x14: /* INC D */
|
|
INC(D); break;
|
|
case 0x1C: /* INC E */
|
|
INC(E); break;
|
|
case 0x24: /* INC H */
|
|
INC(H); break;
|
|
case 0x2C: /* INC L */
|
|
INC(L); break;
|
|
case 0x34: /* INC (HL) */
|
|
b = readb(xHL);
|
|
INC(b);
|
|
writeb(xHL, b);
|
|
break;
|
|
case 0x3C: /* INC A */
|
|
INC(A); break;
|
|
|
|
case 0x03: /* INC BC */
|
|
#ifdef DYNAREC
|
|
W(acc)=((B<<8)|C)+1;
|
|
B=HB(acc);
|
|
C=LB(acc);
|
|
#else
|
|
INCW(BC);
|
|
#endif
|
|
break;
|
|
case 0x13: /* INC DE */
|
|
#ifdef DYNAREC
|
|
W(acc)=((D<<8)|E)+1;
|
|
D=HB(acc);
|
|
E=LB(acc);
|
|
#else
|
|
INCW(DE);
|
|
#endif
|
|
break;
|
|
case 0x23: /* INC HL */
|
|
INCW(HL); break;
|
|
case 0x33: /* INC SP */
|
|
INCW(SP); break;
|
|
|
|
case 0x05: /* DEC B */
|
|
DEC(B); break;
|
|
case 0x0D: /* DEC C */
|
|
DEC(C); break;
|
|
case 0x15: /* DEC D */
|
|
DEC(D); break;
|
|
case 0x1D: /* DEC E */
|
|
DEC(E); break;
|
|
case 0x25: /* DEC H */
|
|
DEC(H); break;
|
|
case 0x2D: /* DEC L */
|
|
DEC(L); break;
|
|
case 0x35: /* DEC (HL) */
|
|
b = readb(xHL);
|
|
DEC(b);
|
|
writeb(xHL, b);
|
|
break;
|
|
case 0x3D: /* DEC A */
|
|
DEC(A); break;
|
|
|
|
case 0x0B: /* DEC BC */
|
|
#ifdef DYNAREC
|
|
W(acc)=((B<<8)|C)-1;
|
|
B=HB(acc);
|
|
C=LB(acc);
|
|
#else
|
|
DECW(BC);
|
|
#endif
|
|
break;
|
|
case 0x1B: /* DEC DE */
|
|
#ifdef DYNAREC
|
|
W(acc)=((D<<8)|E)-1;
|
|
D=HB(acc);
|
|
E=LB(acc);
|
|
#else
|
|
DECW(DE);
|
|
#endif
|
|
break;
|
|
case 0x2B: /* DEC HL */
|
|
DECW(HL); break;
|
|
case 0x3B: /* DEC SP */
|
|
DECW(SP); break;
|
|
|
|
case 0x07: /* RLCA */
|
|
RLCA(A); break;
|
|
case 0x0F: /* RRCA */
|
|
RRCA(A); break;
|
|
case 0x17: /* RLA */
|
|
RLA(A); break;
|
|
case 0x1F: /* RRA */
|
|
RRA(A); break;
|
|
|
|
case 0x27: /* DAA */
|
|
DAA; break;
|
|
case 0x2F: /* CPL */
|
|
CPL(A); break;
|
|
|
|
case 0x18: /* JR */
|
|
__JR:
|
|
JR; break;
|
|
case 0x20: /* JR NZ */
|
|
if (!(F&FZ)) goto __JR; NOJR; break;
|
|
case 0x28: /* JR Z */
|
|
if (F&FZ) goto __JR; NOJR; break;
|
|
case 0x30: /* JR NC */
|
|
if (!(F&FC)) goto __JR; NOJR; break;
|
|
case 0x38: /* JR C */
|
|
if (F&FC) goto __JR; NOJR; break;
|
|
|
|
case 0xC3: /* JP */
|
|
__JP:
|
|
JP; break;
|
|
case 0xC2: /* JP NZ */
|
|
if (!(F&FZ)) goto __JP; NOJP; break;
|
|
case 0xCA: /* JP Z */
|
|
if (F&FZ) goto __JP; NOJP; break;
|
|
case 0xD2: /* JP NC */
|
|
if (!(F&FC)) goto __JP; NOJP; break;
|
|
case 0xDA: /* JP C */
|
|
if (F&FC) goto __JP; NOJP; break;
|
|
case 0xE9: /* JP HL */
|
|
PC = HL; break;
|
|
|
|
case 0xC9: /* RET */
|
|
__RET:
|
|
RET; break;
|
|
case 0xC0: /* RET NZ */
|
|
if (!(F&FZ)) goto __RET; NORET; break;
|
|
case 0xC8: /* RET Z */
|
|
if (F&FZ) goto __RET; NORET; break;
|
|
case 0xD0: /* RET NC */
|
|
if (!(F&FC)) goto __RET; NORET; break;
|
|
case 0xD8: /* RET C */
|
|
if (F&FC) goto __RET; NORET; break;
|
|
case 0xD9: /* RETI */
|
|
IME = IMA = 1; goto __RET;
|
|
|
|
case 0xCD: /* CALL */
|
|
__CALL:
|
|
CALL; break;
|
|
case 0xC4: /* CALL NZ */
|
|
if (!(F&FZ)) goto __CALL; NOCALL; break;
|
|
case 0xCC: /* CALL Z */
|
|
if (F&FZ) goto __CALL; NOCALL; break;
|
|
case 0xD4: /* CALL NC */
|
|
if (!(F&FC)) goto __CALL; NOCALL; break;
|
|
case 0xDC: /* CALL C */
|
|
if (F&FC) goto __CALL; NOCALL; break;
|
|
|
|
case 0xC7: /* RST 0 */
|
|
b = 0x00; goto __RST;
|
|
case 0xCF: /* RST 8 */
|
|
b = 0x08; goto __RST;
|
|
case 0xD7: /* RST 10 */
|
|
b = 0x10; goto __RST;
|
|
case 0xDF: /* RST 18 */
|
|
b = 0x18; goto __RST;
|
|
case 0xE7: /* RST 20 */
|
|
b = 0x20; goto __RST;
|
|
case 0xEF: /* RST 28 */
|
|
b = 0x28; goto __RST;
|
|
case 0xF7: /* RST 30 */
|
|
b = 0x30; goto __RST;
|
|
case 0xFF: /* RST 38 */
|
|
b = 0x38;
|
|
__RST:
|
|
RST(b); break;
|
|
|
|
case 0xC1: /* POP BC */
|
|
#ifdef DYNAREC
|
|
POP(W(acc));
|
|
B=HB(acc);
|
|
C=LB(acc);
|
|
#else
|
|
POP(BC);
|
|
#endif
|
|
break;
|
|
case 0xC5: /* PUSH BC */
|
|
PUSH(BC); break;
|
|
case 0xD1: /* POP DE */
|
|
#ifdef DYNAREC
|
|
POP(W(acc));
|
|
D=HB(acc);
|
|
E=LB(acc);
|
|
#else
|
|
POP(DE);
|
|
#endif
|
|
break;
|
|
case 0xD5: /* PUSH DE */
|
|
PUSH(DE); break;
|
|
case 0xE1: /* POP HL */
|
|
POP(HL); break;
|
|
case 0xE5: /* PUSH HL */
|
|
PUSH(HL); break;
|
|
case 0xF1: /* POP AF */
|
|
#ifdef DYNAREC
|
|
POP(W(acc));
|
|
A=HB(acc);
|
|
F=LB(acc);
|
|
#else
|
|
POP(AF);
|
|
break;
|
|
#endif
|
|
case 0xF5: /* PUSH AF */
|
|
PUSH(AF); break;
|
|
|
|
case 0xE8: /* ADD SP,imm */
|
|
b = FETCH; ADDSP(b); break;
|
|
|
|
case 0xF3: /* DI */
|
|
DI; break;
|
|
case 0xFB: /* EI */
|
|
EI; break;
|
|
|
|
case 0x37: /* SCF */
|
|
SCF; break;
|
|
case 0x3F: /* CCF */
|
|
CCF; break;
|
|
|
|
case 0x10: /* STOP */
|
|
PC++;
|
|
if (R_KEY1 & 1)
|
|
{
|
|
cpu.speed ^= 1;
|
|
R_KEY1 = (R_KEY1 & 0x7E) | (cpu.speed << 7);
|
|
break;
|
|
}
|
|
/* NOTE - we do not implement dmg STOP whatsoever */
|
|
break;
|
|
|
|
case 0x76: /* HALT */
|
|
cpu.halt = 1;
|
|
break;
|
|
|
|
case 0xCB: /* CB prefix */
|
|
cbop = FETCH;
|
|
clen = cb_cycles_table[cbop];
|
|
switch (cbop)
|
|
{
|
|
CB_REG_CASES(B, 0);
|
|
CB_REG_CASES(C, 1);
|
|
CB_REG_CASES(D, 2);
|
|
CB_REG_CASES(E, 3);
|
|
CB_REG_CASES(H, 4);
|
|
CB_REG_CASES(L, 5);
|
|
CB_REG_CASES(A, 7);
|
|
default:
|
|
b = readb(xHL);
|
|
switch(cbop)
|
|
{
|
|
CB_REG_CASES(b, 6);
|
|
}
|
|
if ((cbop & 0xC0) != 0x40) /* exclude BIT */
|
|
writeb(xHL, b);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
die(
|
|
"invalid opcode 0x%02X at address 0x%04X, rombank = %d\n",
|
|
op, (PC-1) & 0xffff, mbc.rombank);
|
|
break;
|
|
}
|
|
#ifdef DYNAREC
|
|
}
|
|
else
|
|
{ /* ROM, dynarec. */
|
|
struct dynarec_block *p=0,*b=address_map[PC&HASH_BITMASK];
|
|
char meow[500];
|
|
byte *ptr=mbc.rmap[PC>>12];
|
|
snprintf(meow,499,"PC: 0x%x 0x%x a: 0x%x\n",
|
|
ptr,PC, b ? b->address.d : 0);
|
|
rb->splash(HZ*2,meow);
|
|
while(b&&b->address.d!=((unsigned int)(ptr)+PC))
|
|
{
|
|
p=b;
|
|
b=b->next;
|
|
}
|
|
if(b)
|
|
{ /* call block */
|
|
int fd;
|
|
blockcount++;
|
|
snprintf(meow,499,"/dyna_0x%x_run.rb",PC);
|
|
fd=open(meow,O_WRONLY|O_CREAT|O_TRUNC, 0666);
|
|
if(fd>=0)
|
|
{
|
|
fdprintf(fd,"Block 0x%x Blockcount: %d\n",PC,blockcount);
|
|
fdprintf(fd,"before: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
|
|
cpu.a,cpu.b,cpu.c,cpu.d,cpu.e,cpu.hl,cpu.f,cpu.sp,cpu.pc,
|
|
cpu.ime);
|
|
if(blockcount<MAXBLOCK)
|
|
{
|
|
asm volatile ("movem.l (%0),%%d1-%%d7/%%a0-%%a1\n\t"
|
|
"jsr (%1)\n\t"
|
|
"movem.l %%d1-%%d7/%%a0-%%a1,(%0)\n\t"
|
|
:
|
|
: "a" (&cpu.a), "a" (b->block)
|
|
: "d0", "d1", "d2", "d3", "d4", "d5", "d6",
|
|
"d7", "a0","a1", "a2","a3","a4");
|
|
clen=blockclen;
|
|
fdprintf(fd,"after: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
|
|
cpu.a,cpu.b,cpu.c,cpu.d,cpu.e,cpu.hl,cpu.f,cpu.sp,
|
|
cpu.pc,cpu.ime);
|
|
}
|
|
else
|
|
die("end");
|
|
close(fd);
|
|
}
|
|
}
|
|
else
|
|
{ /* Hash miss -> not found -> recompile block and add it */
|
|
struct dynarec_block *newblock;
|
|
newblock=malloc(sizeof(struct dynarec_block));
|
|
memset(newblock,0,sizeof(struct dynarec_block));
|
|
newblock->address.d=(unsigned int)(ptr)+PC;
|
|
dynamic_recompile(newblock);
|
|
if(p)
|
|
p->next=newblock;
|
|
else
|
|
address_map[PC&HASH_BITMASK]=newblock;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
|
|
clen <<= 1;
|
|
div_advance(clen);
|
|
timer_advance(clen);
|
|
clen >>= cpu.speed;
|
|
lcdc_advance(clen);
|
|
if(options.sound)
|
|
sound_advance(clen);
|
|
|
|
i -= clen;
|
|
if (i > 0) goto next;
|
|
return cycles-i;
|
|
}
|
|
|
|
#endif /* ASM_CPU_EMULATE */
|