21f0c9a282
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19971 a1c6a512-1295-4272-9138-f99709370657
177 lines
5 KiB
C
177 lines
5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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* Copyright (C) 2007 by Michael Sevakis
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_TARGET_H
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#define SYSTEM_TARGET_H
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#include "system-arm.h"
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#ifdef CPU_PP
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/* TODO: This header is actually portalplayer specific, and should be
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* moved into an appropriate subdir (or even split in 2). */
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#if CONFIG_CPU == PP5002
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#define CPUFREQ_SLEEP 32768
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#define CPUFREQ_DEFAULT 24000000
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#define CPUFREQ_NORMAL 30000000
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#define CPUFREQ_MAX 80000000
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#else /* PP5022, PP5024 */
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#define CPUFREQ_SLEEP 32768
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#define CPUFREQ_DEFAULT 24000000
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#define CPUFREQ_NORMAL 30000000
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#define CPUFREQ_MAX 80000000
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#endif
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#define inl(a) (*(volatile unsigned long *) (a))
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#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
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#define inb(a) (*(volatile unsigned char *) (a))
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#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
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#define inw(a) (*(volatile unsigned short *) (a))
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#define outw(a,b) (*(volatile unsigned short *) (b) = (a))
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && NUM_CORES > 1
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extern struct spinlock boostctrl_spin;
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#endif
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static inline void udelay(unsigned usecs)
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{
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unsigned stop = USEC_TIMER + usecs;
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while (TIME_BEFORE(USEC_TIMER, stop));
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}
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static inline unsigned int current_core(void)
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{
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/*
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* PROCESSOR_ID seems to be 32-bits:
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* CPU = 0x55555555 = |01010101|01010101|01010101|01010101|
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* COP = 0xaaaaaaaa = |10101010|10101010|10101010|10101010|
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* ^
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*/
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unsigned int core;
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asm volatile (
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"ldrb %0, [%1] \n" /* Just load the LSB */
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"mov %0, %0, lsr #7 \n" /* Bit 7 => index */
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: "=r"(core) /* CPU=0, COP=1 */
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: "r"(&PROCESSOR_ID)
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);
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return core;
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}
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/* Return the actual ID instead of core index */
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static inline unsigned int processor_id(void)
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{
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unsigned int id;
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asm volatile (
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"ldrb %0, [%1] \n"
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: "=r"(id)
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: "r"(&PROCESSOR_ID)
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);
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return id;
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}
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#if CONFIG_CPU == PP5002
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static inline void sleep_core(int core)
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{
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asm volatile (
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/* Sleep: PP5002 crashes if the instruction that puts it to sleep is
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* located at 0xNNNNNNN0. 4/8/C works. This sequence makes sure
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* that the correct alternative is executed. Don't change the order
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* of the next 4 instructions! */
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"tst pc, #0x0c \n"
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"mov r0, #0xca \n"
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"strne r0, [%[ctl]] \n"
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"streq r0, [%[ctl]] \n"
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"nop \n" /* nop's needed because of pipeline */
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"nop \n"
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"nop \n"
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:
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: [ctl]"r"(&PROC_CTL(core))
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: "r0"
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);
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}
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static inline void wake_core(int core)
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{
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asm volatile (
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"mov r0, #0xce \n"
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"str r0, [%[ctl]] \n"
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:
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: [ctl]"r"(&PROC_CTL(core))
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: "r0"
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);
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}
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#else /* PP502x */
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static inline void sleep_core(int core)
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{
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asm volatile (
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"mov r0, #0x80000000 \n"
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"str r0, [%[ctl]] \n"
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"nop \n"
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:
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: [ctl]"r"(&PROC_CTL(core))
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: "r0"
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);
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}
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static inline void wake_core(int core)
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{
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asm volatile (
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"mov r0, #0 \n"
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"str r0, [%[ctl]] \n"
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:
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: [ctl]"r"(&PROC_CTL(core))
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: "r0"
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);
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}
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#endif
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#ifdef BOOTLOADER
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/* All addresses within rockbox are in IRAM in the bootloader so
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are therefore uncached */
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#define UNCACHED_ADDR(a) (a)
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#else /* !BOOTLOADER */
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#if CONFIG_CPU == PP5002
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#define UNCACHED_BASE_ADDR 0x28000000
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#else /* PP502x */
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#define UNCACHED_BASE_ADDR 0x10000000
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#endif
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#define UNCACHED_ADDR(a) \
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((typeof (a))((uintptr_t)(a) | UNCACHED_BASE_ADDR))
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#endif /* BOOTLOADER */
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/* Certain data needs to be out of the way of cache line interference
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* such as data for COP use or for use with UNCACHED_ADDR */
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#define PROC_NEEDS_CACHEALIGN
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#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
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/** cache functions **/
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#ifndef BOOTLOADER
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#define HAVE_CPUCACHE_INVALIDATE
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#define HAVE_CPUCACHE_FLUSH
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#endif
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#endif /* CPU_PP */
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#endif /* SYSTEM_TARGET_H */
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