b01da58c55
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12065 a1c6a512-1295-4272-9138-f99709370657
374 lines
8.9 KiB
C
374 lines
8.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Michael Sevakis
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "kernel.h"
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#include "logf.h"
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#include "audio.h"
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#include "wm8975.h"
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#include "file.h"
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#include "mmu-meg-fx.h"
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static int pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */
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#define GIGABEAT_8000HZ 0x4d
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#define GIGABEAT_11025HZ 0x32
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#define GIGABEAT_12000HZ 0x61
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#define GIGABEAT_16000HZ 0x55
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#define GIGABEAT_22050HZ 0x36
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#define GIGABEAT_24000HZ 0x79
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#define GIGABEAT_32000HZ 0x59
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#define GIGABEAT_44100HZ 0x22
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#define GIGABEAT_48000HZ 0x41
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#define GIGABEAT_88200HZ 0x3e
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#define GIGABEAT_96000HZ 0x5d
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#define FIFO_COUNT ((IISFCON >> 6) & 0x01F)
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/* number of bytes in FIFO */
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#define IIS_FIFO_SIZE 64
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/* Setup for the DMA controller */
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#define DMA_CONTROL_SETUP ((1<<31) | (1<<29) | (1<<23) | (1<<22) | (1<<20))
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unsigned short * p;
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size_t p_size;
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/* DMA count has hit zero - no more data */
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/* Get more data from the callback and top off the FIFO */
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//void fiq(void) __attribute__ ((interrupt ("naked")));
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void fiq(void) ICODE_ATTR __attribute__ ((interrupt ("FIQ")));
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void fiq(void)
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{
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/* clear any pending interrupt */
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SRCPND = (1<<19);
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/* Buffer empty. Try to get more. */
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if (pcm_callback_for_more)
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{
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pcm_callback_for_more((unsigned char**)&p, &p_size);
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}
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else
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{
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/* callback func is missing? */
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pcm_play_dma_stop();
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return;
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}
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if (p_size)
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{
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/* Flush any pending cache writes */
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clean_dcache_range(p, p_size);
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/* set the new DMA values */
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DCON2 = DMA_CONTROL_SETUP | (p_size >> 1);
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DISRC2 = (int)p + 0x30000000;
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/* Re-Activate the channel */
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DMASKTRIG2 = 0x2;
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}
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else
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{
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/* No more DMA to do */
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pcm_play_dma_stop();
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}
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}
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void pcm_init(void)
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{
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pcm_playing = false;
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pcm_paused = false;
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pcm_callback_for_more = NULL;
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audiohw_init();
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audiohw_enable_output(true);
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/* cannot use the WM8975 defaults since our clock is not the same */
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/* the input master clock is 16.9344MHz - we can divide exact for that */
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pcm_set_frequency(SAMPR_44);
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/* init GPIO */
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GPCCON = (GPCCON & ~(3<<14)) | (1<<14);
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GPCDAT |= 1<<7;
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GPECON |= 0x2aa;
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/* Do not service DMA requests, yet */
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/* clear any pending int and mask it */
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INTMSK |= (1<<19); /* mask the interrupt */
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SRCPND = (1<<19); /* clear any pending interrupts */
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INTMOD |= (1<<19); /* connect to FIQ */
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}
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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/* sanity check: bad pointer or too small file */
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if (NULL == addr || size <= IIS_FIFO_SIZE) return;
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p = (unsigned short *)addr;
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p_size = size;
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/* Enable the IIS clock */
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CLKCON |= (1<<17);
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/* IIS interface setup and set to idle */
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IISCON = (1<<5) | (1<<3);
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/* slave, transmit mode, 16 bit samples - 384fs - use 16.9344Mhz */
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IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2);
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/* connect DMA to the FIFO and enable the FIFO */
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IISFCON = (1<<15) | (1<<13);
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/* set DMA dest */
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DIDST2 = (int)&IISFIFO;
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/* IIS is on the APB bus, INT when TC reaches 0, fixed dest addr */
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DIDSTC2 = 0x03;
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/* How many transfers to make - we transfer half-word at a time = 2 bytes */
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/* DMA control: CURR_TC int, single service mode, I2SSDO int, HW trig */
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/* no auto-reload, half-word (16bit) */
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DCON2 = DMA_CONTROL_SETUP | (p_size / 2);
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/* set DMA source and options */
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DISRC2 = (int)p + 0x30000000;
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DISRCC2 = 0x00; /* memory is on AHB bus, increment addresses */
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/* clear pending DMA interrupt */
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SRCPND = 1<<19;
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set_fiq_handler(fiq);
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enable_fiq();
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/* unmask the DMA interrupt */
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INTMSK &= ~(1<<19);
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/* Flush any pending writes */
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clean_dcache_range(addr, size);
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/* Activate the channel */
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DMASKTRIG2 = 0x2;
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/* turn off the idle */
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IISCON &= ~(1<<3);
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pcm_playing = true;
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/* start the IIS */
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IISCON |= (1<<0);
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}
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/* Disconnect the DMA and wait for the FIFO to clear */
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void pcm_play_dma_stop(void)
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{
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/* mask the DMA interrupt */
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INTMSK |= (1<<19);
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/* are we playing? wait for the chunk to finish */
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if (pcm_playing)
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{
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/* wait for the FIFO to empty before turning things off */
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while (IISCON & (1<<7)) ;
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pcm_playing = false;
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}
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/* De-Activate the DMA channel */
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DMASKTRIG2 = 0x4;
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/* Disconnect the IIS clock */
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CLKCON &= ~(1<<17);
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disable_fiq();
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}
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void pcm_play_pause_pause(void)
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{
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/* stop servicing refills */
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INTMSK |= (1<<19);
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}
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void pcm_play_pause_unpause(void)
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{
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/* refill buffer and keep going */
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INTMSK &= ~(1<<19);
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}
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void pcm_set_frequency(unsigned int frequency)
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{
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int sr_ctrl;
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switch(frequency)
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{
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case SAMPR_8:
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sr_ctrl = GIGABEAT_8000HZ;
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break;
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case SAMPR_11:
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sr_ctrl = GIGABEAT_11025HZ;
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break;
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case SAMPR_12:
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sr_ctrl = GIGABEAT_12000HZ;
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break;
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case SAMPR_16:
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sr_ctrl = GIGABEAT_16000HZ;
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break;
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case SAMPR_22:
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sr_ctrl = GIGABEAT_22050HZ;
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break;
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case SAMPR_24:
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sr_ctrl = GIGABEAT_24000HZ;
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break;
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case SAMPR_32:
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sr_ctrl = GIGABEAT_32000HZ;
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break;
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default:
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frequency = SAMPR_44;
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case SAMPR_44:
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sr_ctrl = GIGABEAT_44100HZ;
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break;
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case SAMPR_48:
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sr_ctrl = GIGABEAT_48000HZ;
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break;
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case SAMPR_88:
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sr_ctrl = GIGABEAT_88200HZ;
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break;
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case SAMPR_96:
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sr_ctrl = GIGABEAT_96000HZ;
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break;
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}
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audiohw_set_sample_rate(sr_ctrl);
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pcm_freq = frequency;
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}
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size_t pcm_get_bytes_waiting(void)
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{
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return (DSTAT2 & 0xFFFFF) * 2;
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}
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/* dummy functions for those not actually supporting all this yet */
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void pcm_apply_settings(bool reset)
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{
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(void)reset;
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}
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void pcm_set_monitor(int monitor)
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{
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(void)monitor;
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}
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/** **/
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void pcm_mute(bool mute)
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{
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audiohw_mute(mute);
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if (mute)
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sleep(HZ/16);
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}
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/*
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* This function goes directly into the DMA buffer to calculate the left and
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* right peak values. To avoid missing peaks it tries to look forward two full
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* peek periods (2/HZ sec, 100% overlap), although it's always possible that
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* the entire period will not be visible. To reduce CPU load it only looks at
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* every third sample, and this can be reduced even further if needed (even
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* every tenth sample would still be pretty accurate).
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*/
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/* Check for a peak every PEAK_STRIDE samples */
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#define PEAK_STRIDE 3
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/* Up to 1/50th of a second of audio for peak calculation */
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/* This should use NATIVE_FREQUENCY, or eventually an adjustable freq. value */
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#define PEAK_SAMPLES (44100/50)
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void pcm_calculate_peaks(int *left, int *right)
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{
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short *addr;
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short *end;
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{
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size_t samples = p_size / 4;
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addr = p;
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if (samples > PEAK_SAMPLES)
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samples = PEAK_SAMPLES - (PEAK_STRIDE - 1);
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else
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samples -= MIN(PEAK_STRIDE - 1, samples);
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end = &addr[samples * 2];
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}
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if (left && right) {
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int left_peak = 0, right_peak = 0;
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while (addr < end) {
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int value;
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if ((value = addr [0]) > left_peak)
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left_peak = value;
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else if (-value > left_peak)
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left_peak = -value;
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if ((value = addr [PEAK_STRIDE | 1]) > right_peak)
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right_peak = value;
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else if (-value > right_peak)
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right_peak = -value;
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addr = &addr[PEAK_STRIDE * 2];
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}
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*left = left_peak;
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*right = right_peak;
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}
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else if (left || right) {
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int peak_value = 0, value;
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if (right)
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addr += (PEAK_STRIDE | 1);
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while (addr < end) {
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if ((value = addr [0]) > peak_value)
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peak_value = value;
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else if (-value > peak_value)
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peak_value = -value;
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addr += PEAK_STRIDE * 2;
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}
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if (left)
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*left = peak_value;
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else
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*right = peak_value;
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}
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}
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