6a67707b5e
Wouldn't surprise me a bit to get some non-green. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31339 a1c6a512-1295-4272-9138-f99709370657
248 lines
6.1 KiB
C
248 lines
6.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Barry Wardell
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* ATA stuff was taken from the iPod code */
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#include <stdbool.h>
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#include "system.h"
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#include "ata-driver.h"
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void ata_reset()
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{
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}
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void ata_enable(bool on)
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{
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/* TODO: Implement ata_enable() */
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(void)on;
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}
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bool ata_is_coldstart()
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{
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return false;
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/* TODO: Implement coldstart variable */
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}
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void ata_device_init()
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{
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#ifdef SAMSUNG_YH920
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CPU_INT_DIS = (1<<IDE_IRQ);
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#endif
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#ifdef HAVE_ATA_DMA
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IDE_DMA_CONTROL |= 2;
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IDE_DMA_CONTROL &= ~1;
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IDE0_CFG &= ~0x8010;
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IDE0_CFG |= 0x20;
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#else
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/* From ipod-ide.c:ipod_ide_register() */
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IDE0_CFG |= (1<<5);
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#ifdef IPOD_NANO
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IDE0_CFG |= (0x10000000); /* cpu > 65MHz */
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#else
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IDE0_CFG &=~(0x10000000); /* cpu < 65MHz */
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#endif
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#endif
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IDE0_PRI_TIMING0 = 0x10;
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IDE0_PRI_TIMING1 = 0x80002150;
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}
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/* These are PIO timings for 80 Mhz. At 24 Mhz,
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the first value is 0 but the rest are the same.
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They go in IDE0_PRI_TIMING0.
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Rockbox used 0x10, and test_disk shows that leads to faster PIO.
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If 0x10 is incorrect, these timings may be needed with some devices.
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static const unsigned long pio80mhz[] = {
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0xC293, 0x43A2, 0x11A1, 0x7232, 0x3131
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};
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*/
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#ifdef HAVE_ATA_DMA
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/* Timings for multi-word and ultra DMA modes.
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These go in IDE0_PRI_TIMING1
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*/
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static const unsigned long tm_mwdma[] = {
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0xF9F92, 0x56562, 0x45451
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};
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static const unsigned long tm_udma[] = {
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0x800037C1, 0x80003491, 0x80003371,
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#if ATA_MAX_UDMA > 2
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0x80003271, 0x80003071
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#endif
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};
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#if ATA_MAX_UDMA > 2
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static bool dma_boosted = false;
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static bool dma_needs_boost;
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#endif
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/* This function sets up registers for 80 Mhz.
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Ultra DMA mode 2 works at 30 Mhz.
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*/
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void ata_dma_set_mode(unsigned char mode) {
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int modeidx;
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(*(volatile unsigned long *)(0x600060C4)) = 0xC0000000; /* 80 Mhz */
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#if !defined(IPOD_NANO)
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IDE0_CFG &= ~0x10000000;
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#endif
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modeidx = mode & 7;
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mode &= 0xF8;
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if (mode == 0x40 && modeidx <= ATA_MAX_UDMA) {
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IDE0_PRI_TIMING1 = tm_udma[modeidx];
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#if ATA_MAX_UDMA > 2
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if (modeidx > 2)
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dma_needs_boost = true;
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else
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dma_needs_boost = false;
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#endif
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} else if (mode == 0x20 && modeidx <= ATA_MAX_MWDMA)
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IDE0_PRI_TIMING1 = tm_mwdma[modeidx];
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#if !defined(IPOD_NANO)
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IDE0_CFG |= 0x20000000; /* >= 50 Mhz */
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#endif
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}
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#define IDE_CFG_INTRQ 8
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#define IDE_DMA_CONTROL_READ 8
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/* This waits for an ATA interrupt using polling.
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In ATA_CONTROL, CONTROL_nIEN must be cleared.
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*/
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STATICIRAM ICODE_ATTR int ata_wait_intrq(void)
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{
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long timeout = current_tick + HZ*10;
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do
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{
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if (IDE0_CFG & IDE_CFG_INTRQ)
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return 1;
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ata_keep_active();
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yield();
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} while (TIME_BEFORE(current_tick, timeout));
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return 0; /* timeout */
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}
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/* This function checks if parameters are appropriate for DMA,
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and if they are, it sets up for DMA.
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If return value is false, caller may use PIO for this transfer.
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If return value is true, caller must issue a DMA ATA command
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and then call ata_dma_finish().
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*/
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bool ata_dma_setup(void *addr, unsigned long bytes, bool write) {
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/* Require cacheline alignment for reads to prevent interference. */
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if (!write && ((unsigned long)addr & 15))
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return false;
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/* Writes only need to be word-aligned, but by default DMA
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* is not used for writing as it appears to be slower.
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*/
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#ifdef ATA_DMA_WRITES
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if (write && ((unsigned long)addr & 3))
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return false;
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#else
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if (write)
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return false;
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#endif
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#if ATA_MAX_UDMA > 2
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if (dma_needs_boost && !dma_boosted) {
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cpu_boost(true);
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dma_boosted = true;
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}
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#endif
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if (write) {
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/* If unflushed, old data may be written to disk */
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commit_dcache();
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}
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else {
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/* Invalidate cache because new data may be present in RAM */
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commit_discard_dcache();
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}
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/* Clear pending interrupts so ata_dma_finish() can wait for an
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interrupt from this transfer
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*/
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IDE0_CFG |= IDE_CFG_INTRQ;
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IDE_DMA_CONTROL |= 2;
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IDE_DMA_LENGTH = bytes - 4;
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#if !defined(BOOTLOADER) || defined (HAVE_BOOTLOADER_USB_MODE)
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if ((unsigned long)addr < DRAM_START)
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/* Rockbox remaps DRAM to start at 0 */
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IDE_DMA_ADDR = (unsigned long)addr + DRAM_START;
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else
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#endif
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IDE_DMA_ADDR = (unsigned long)addr;
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if (write)
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IDE_DMA_CONTROL &= ~IDE_DMA_CONTROL_READ;
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else
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IDE_DMA_CONTROL |= IDE_DMA_CONTROL_READ;
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IDE0_CFG |= 0x8000;
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return true;
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}
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/* This function waits for a DMA transfer to end.
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It must be called to finish what ata_dma_setup started.
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Return value is true if DMA completed before the timeout, and false
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if a timeout happened.
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*/
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bool ata_dma_finish(void) {
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bool res;
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/* It may be okay to put this at the end of setup */
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IDE_DMA_CONTROL |= 1;
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/* Wait for end of transfer.
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Reading standard ATA status while DMA is in progress causes
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failures and hangs. Because of that, another wait is used.
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*/
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res = ata_wait_intrq();
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IDE0_CFG &= ~0x8000;
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IDE_DMA_CONTROL &= ~0x80000001;
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#if ATA_MAX_UDMA > 2
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if (dma_boosted) {
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cpu_boost(false);
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dma_boosted = false;
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}
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#endif
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return res;
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}
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#endif /* HAVE_ATA_DMA */
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