66827f3a18
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16358 a1c6a512-1295-4272-9138-f99709370657
561 lines
26 KiB
C
561 lines
26 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2004 by Thom Johansen
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __PP5020_H__
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#define __PP5020_H__
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/* All info gleaned and/or copied from the iPodLinux project. */
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/* DRAM starts at 0x10000000, but in Rockbox we remap it to 0x00000000 */
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#define DRAM_START 0x10000000
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/* Processor ID */
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#define PROCESSOR_ID (*(volatile unsigned long *)(0x60000000))
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#define PROC_ID_CPU 0x55
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#define PROC_ID_COP 0xaa
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/* Mailboxes */
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#define MBX_BASE (0x60001000)
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/* Read bits in the mailbox */
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#define MBX_MSG_STAT (*(volatile unsigned long *)(0x60001000))
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/* Set bits in the mailbox */
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#define MBX_MSG_SET (*(volatile unsigned long *)(0x60001004))
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/* Clear bits in the mailbox */
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#define MBX_MSG_CLR (*(volatile unsigned long *)(0x60001008))
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/* Doesn't seem to be COP_REPLY at all :) */
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#define MBX_UNKNOWN1 (*(volatile unsigned long *)(0x6000100c))
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/* COP can set bit 29 - only CPU read clears it */
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#define CPU_QUEUE (*(volatile unsigned long *)(0x60001010))
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/* CPU can set bit 29 - only COP read clears it */
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#define COP_QUEUE (*(volatile unsigned long *)(0x60001020))
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#define PROC_QUEUE(core) ((&CPU_QUEUE)[(core)*4])
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/* Interrupts */
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#define CPU_INT_STAT (*(volatile unsigned long*)(0x60004000))
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#define COP_INT_STAT (*(volatile unsigned long*)(0x60004004))
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#define CPU_FIQ_STAT (*(volatile unsigned long*)(0x60004008))
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#define COP_FIQ_STAT (*(volatile unsigned long*)(0x6000400c))
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#define INT_STAT (*(volatile unsigned long*)(0x60004010))
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#define INT_FORCED_STAT (*(volatile unsigned long*)(0x60004014))
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#define INT_FORCED_SET (*(volatile unsigned long*)(0x60004018))
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#define INT_FORCED_CLR (*(volatile unsigned long*)(0x6000401c))
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#define CPU_INT_EN_STAT (*(volatile unsigned long*)(0x60004020))
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#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
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#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028))
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#define CPU_INT_PRIORITY (*(volatile unsigned long*)(0x6000402c))
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#define COP_INT_EN_STAT (*(volatile unsigned long*)(0x60004030))
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#define COP_INT_EN (*(volatile unsigned long*)(0x60004034))
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#define COP_INT_CLR (*(volatile unsigned long*)(0x60004038))
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#define COP_INT_PRIORITY (*(volatile unsigned long*)(0x6000403c))
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#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x60004100))
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#define COP_HI_INT_STAT (*(volatile unsigned long*)(0x60004104))
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#define CPU_HI_FIQ_STAT (*(volatile unsigned long*)(0x60004108))
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#define COP_HI_FIQ_STAT (*(volatile unsigned long*)(0x6000410c))
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#define HI_INT_STAT (*(volatile unsigned long*)(0x60004110))
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#define HI_INT_FORCED_STAT (*(volatile unsigned long*)(0x60004114))
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#define HI_INT_FORCED_SET (*(volatile unsigned long*)(0x60004118))
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#define HI_INT_FORCED_CLR (*(volatile unsigned long*)(0x6000411c))
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#define CPU_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004120))
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#define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124))
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#define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128))
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#define CPU_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000412c))
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#define COP_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004130))
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#define COP_HI_INT_EN (*(volatile unsigned long*)(0x60004134))
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#define COP_HI_INT_CLR (*(volatile unsigned long*)(0x60004138))
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#define COP_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000413c))
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#define TIMER1_IRQ 0
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#define TIMER2_IRQ 1
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#define MAILBOX_IRQ 4
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#define IIS_IRQ 10
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#define USB_IRQ 20
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#define IDE_IRQ 23
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#define FIREWIRE_IRQ 25
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#define HI_IRQ 30
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#define GPIO0_IRQ (32+0) /* Ports A..D */
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#define GPIO1_IRQ (32+1) /* Ports E..H */
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#define GPIO2_IRQ (32+2) /* Ports I..L */
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#define SER0_IRQ (32+4)
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#define SER1_IRQ (32+5)
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#define I2C_IRQ (32+8)
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#define TIMER1_MASK (1 << TIMER1_IRQ)
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#define TIMER2_MASK (1 << TIMER2_IRQ)
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#define MAILBOX_MASK (1 << MAILBOX_IRQ)
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#define IIS_MASK (1 << IIS_IRQ)
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#define IDE_MASK (1 << IDE_IRQ)
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#define USB_MASK (1 << USB_IRQ)
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#define FIREWIRE_MASK (1 << FIREWIRE_IRQ)
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#define HI_MASK (1 << HI_IRQ)
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#define GPIO0_MASK (1 << (GPIO0_IRQ-32))
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#define GPIO1_MASK (1 << (GPIO1_IRQ-32))
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#define GPIO2_MASK (1 << (GPIO2_IRQ-32))
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#define SER0_MASK (1 << (SER0_IRQ-32))
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#define SER1_MASK (1 << (SER1_IRQ-32))
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#define I2C_MASK (1 << (I2C_IRQ-32))
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/* Timers */
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#define TIMER1_CFG (*(volatile unsigned long *)(0x60005000))
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#define TIMER1_VAL (*(volatile unsigned long *)(0x60005004))
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#define TIMER2_CFG (*(volatile unsigned long *)(0x60005008))
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#define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c))
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#define USEC_TIMER (*(volatile unsigned long *)(0x60005010))
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#define RTC (*(volatile unsigned long *)(0x60005014))
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/* Device Controller */
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#define DEV_RS (*(volatile unsigned long *)(0x60006004))
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#define DEV_RS2 (*(volatile unsigned long *)(0x60006008))
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#define DEV_EN (*(volatile unsigned long *)(0x6000600c))
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#define DEV_EN2 (*(volatile unsigned long *)(0x60006010))
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#define DEV_EXTCLOCKS 0x00000002
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#define DEV_SYSTEM 0x00000004
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#define DEV_USB0 0x00000008
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#define DEV_SER0 0x00000040
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#define DEV_SER1 0x00000080
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#define DEV_I2S 0x00000800
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#define DEV_I2C 0x00001000
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#define DEV_ATA 0x00004000
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#define DEV_OPTO 0x00010000
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#define DEV_PIEZO 0x00010000
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#define DEV_PWM 0x00020000
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#define DEV_USB1 0x00400000
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#define DEV_FIREWIRE 0x00800000
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#define DEV_IDE0 0x02000000
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#define DEV_LCD 0x04000000
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/* clock control */
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#define CLOCK_SOURCE (*(volatile unsigned long *)(0x60006020))
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#define MLCD_SCLK_DIV (*(volatile unsigned long *)(0x6000602c))
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/* bits 0..1: Mono LCD bridge serial clock divider: 1 / (n+1) */
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#define PLL_CONTROL (*(volatile unsigned long *)(0x60006034))
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#define PLL_STATUS (*(volatile unsigned long *)(0x6000603c))
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#define ADC_CLOCK_SRC (*(volatile unsigned long *)(0x60006094))
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#define CLCD_CLOCK_SRC (*(volatile unsigned long *)(0x600060a0))
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/* Processors Control */
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#define CPU_CTL (*(volatile unsigned long *)(0x60007000))
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#define COP_CTL (*(volatile unsigned long *)(0x60007004))
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#define PROC_CTL(core) ((&CPU_CTL)[core])
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#define PROC_SLEEP 0x80000000
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#define PROC_WAIT 0x40000000
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#define PROC_WAIT_CLR 0x20000000
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#define PROC_CNT_START 0x08000000
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#define PROC_WAKE 0x00000000
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/**
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* This is based on some quick but sound experiments on PP5022C.
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* CPU/COP_CTL bitmap:
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* [31] - sleep until an interrupt occurs
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* [30] - wait for cycle countdown to 0
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* [29] - wait for cycle countdown to 0
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* behaves identically to bit 30 unless bit 30 is set as well
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* in which case this bit is cleared at the end of the count
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* [28] - unknown - no execution effect observed yet
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* [27] - begin cycle countdown
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* [26:8] - semaphore flags for core communication ?
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* no execution effect observed yet
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* [11:8] seem to often be set to the core's own ID
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* nybble when sleeping - 0x5 or 0xa.
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* [7:0] - W: number of cycles to skip on next instruction
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* R: cycles remaining
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* Executing on CPU
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* CPU_CTL = 0x68000080
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* nop
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* stalls the nop for 128 cycles
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* Reading CPU_CTL after the nop will return 0x48000000
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*/
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/* Cache Control */
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#define CACHE_PRIORITY (*(volatile unsigned long *)(0x60006044))
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#define CACHE_CTL (*(volatile unsigned long *)(0x6000c000))
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#define CACHE_MASK (*(volatile unsigned long *)(0xf000f040))
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#define CACHE_OPERATION (*(volatile unsigned long *)(0xf000f044))
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#define CACHE_FLUSH_MASK (*(volatile unsigned long *)(0xf000f048))
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/* CACHE_CTL bits */
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#define CACHE_CTL_DISABLE 0x0000
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#define CACHE_CTL_ENABLE 0x0001
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#define CACHE_CTL_RUN 0x0002
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#define CACHE_CTL_INIT 0x0004
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#define CACHE_CTL_VECT_REMAP 0x0010
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#define CACHE_CTL_READY 0x4000
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#define CACHE_CTL_BUSY 0x8000
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/* CACHE_OPERATION bits */
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#define CACHE_OP_FLUSH 0x0002
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#define CACHE_OP_INVALIDATE 0x0004
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/* GPIO Ports */
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#define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000))
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#define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004))
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#define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008))
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#define GPIOD_ENABLE (*(volatile unsigned long *)(0x6000d00c))
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#define GPIOA_OUTPUT_EN (*(volatile unsigned long *)(0x6000d010))
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#define GPIOB_OUTPUT_EN (*(volatile unsigned long *)(0x6000d014))
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#define GPIOC_OUTPUT_EN (*(volatile unsigned long *)(0x6000d018))
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#define GPIOD_OUTPUT_EN (*(volatile unsigned long *)(0x6000d01c))
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#define GPIOA_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d020))
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#define GPIOB_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d024))
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#define GPIOC_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d028))
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#define GPIOD_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d02c))
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#define GPIOA_INPUT_VAL (*(volatile unsigned long *)(0x6000d030))
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#define GPIOB_INPUT_VAL (*(volatile unsigned long *)(0x6000d034))
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#define GPIOC_INPUT_VAL (*(volatile unsigned long *)(0x6000d038))
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#define GPIOD_INPUT_VAL (*(volatile unsigned long *)(0x6000d03c))
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#define GPIOA_INT_STAT (*(volatile unsigned long *)(0x6000d040))
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#define GPIOB_INT_STAT (*(volatile unsigned long *)(0x6000d044))
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#define GPIOC_INT_STAT (*(volatile unsigned long *)(0x6000d048))
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#define GPIOD_INT_STAT (*(volatile unsigned long *)(0x6000d04c))
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#define GPIOA_INT_EN (*(volatile unsigned long *)(0x6000d050))
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#define GPIOB_INT_EN (*(volatile unsigned long *)(0x6000d054))
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#define GPIOC_INT_EN (*(volatile unsigned long *)(0x6000d058))
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#define GPIOD_INT_EN (*(volatile unsigned long *)(0x6000d05c))
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#define GPIOA_INT_LEV (*(volatile unsigned long *)(0x6000d060))
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#define GPIOB_INT_LEV (*(volatile unsigned long *)(0x6000d064))
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#define GPIOC_INT_LEV (*(volatile unsigned long *)(0x6000d068))
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#define GPIOD_INT_LEV (*(volatile unsigned long *)(0x6000d06c))
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#define GPIOA_INT_CLR (*(volatile unsigned long *)(0x6000d070))
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#define GPIOB_INT_CLR (*(volatile unsigned long *)(0x6000d074))
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#define GPIOC_INT_CLR (*(volatile unsigned long *)(0x6000d078))
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#define GPIOD_INT_CLR (*(volatile unsigned long *)(0x6000d07c))
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#define GPIOE_ENABLE (*(volatile unsigned long *)(0x6000d080))
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#define GPIOF_ENABLE (*(volatile unsigned long *)(0x6000d084))
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#define GPIOG_ENABLE (*(volatile unsigned long *)(0x6000d088))
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#define GPIOH_ENABLE (*(volatile unsigned long *)(0x6000d08c))
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#define GPIOE_OUTPUT_EN (*(volatile unsigned long *)(0x6000d090))
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#define GPIOF_OUTPUT_EN (*(volatile unsigned long *)(0x6000d094))
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#define GPIOG_OUTPUT_EN (*(volatile unsigned long *)(0x6000d098))
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#define GPIOH_OUTPUT_EN (*(volatile unsigned long *)(0x6000d09c))
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#define GPIOE_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a0))
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#define GPIOF_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a4))
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#define GPIOG_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a8))
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#define GPIOH_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0ac))
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#define GPIOE_INPUT_VAL (*(volatile unsigned long *)(0x6000d0b0))
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#define GPIOF_INPUT_VAL (*(volatile unsigned long *)(0x6000d0b4))
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#define GPIOG_INPUT_VAL (*(volatile unsigned long *)(0x6000d0b8))
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#define GPIOH_INPUT_VAL (*(volatile unsigned long *)(0x6000d0bc))
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#define GPIOE_INT_STAT (*(volatile unsigned long *)(0x6000d0c0))
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#define GPIOF_INT_STAT (*(volatile unsigned long *)(0x6000d0c4))
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#define GPIOG_INT_STAT (*(volatile unsigned long *)(0x6000d0c8))
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#define GPIOH_INT_STAT (*(volatile unsigned long *)(0x6000d0cc))
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#define GPIOE_INT_EN (*(volatile unsigned long *)(0x6000d0d0))
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#define GPIOF_INT_EN (*(volatile unsigned long *)(0x6000d0d4))
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#define GPIOG_INT_EN (*(volatile unsigned long *)(0x6000d0d8))
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#define GPIOH_INT_EN (*(volatile unsigned long *)(0x6000d0dc))
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#define GPIOE_INT_LEV (*(volatile unsigned long *)(0x6000d0e0))
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#define GPIOF_INT_LEV (*(volatile unsigned long *)(0x6000d0e4))
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#define GPIOG_INT_LEV (*(volatile unsigned long *)(0x6000d0e8))
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#define GPIOH_INT_LEV (*(volatile unsigned long *)(0x6000d0ec))
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#define GPIOE_INT_CLR (*(volatile unsigned long *)(0x6000d0f0))
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#define GPIOF_INT_CLR (*(volatile unsigned long *)(0x6000d0f4))
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#define GPIOG_INT_CLR (*(volatile unsigned long *)(0x6000d0f8))
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#define GPIOH_INT_CLR (*(volatile unsigned long *)(0x6000d0fc))
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#define GPIOI_ENABLE (*(volatile unsigned long *)(0x6000d100))
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#define GPIOJ_ENABLE (*(volatile unsigned long *)(0x6000d104))
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#define GPIOK_ENABLE (*(volatile unsigned long *)(0x6000d108))
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#define GPIOL_ENABLE (*(volatile unsigned long *)(0x6000d10c))
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#define GPIOI_OUTPUT_EN (*(volatile unsigned long *)(0x6000d110))
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#define GPIOJ_OUTPUT_EN (*(volatile unsigned long *)(0x6000d114))
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#define GPIOK_OUTPUT_EN (*(volatile unsigned long *)(0x6000d118))
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#define GPIOL_OUTPUT_EN (*(volatile unsigned long *)(0x6000d11c))
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#define GPIOI_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d120))
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#define GPIOJ_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d124))
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#define GPIOK_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d128))
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#define GPIOL_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d12c))
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#define GPIOI_INPUT_VAL (*(volatile unsigned long *)(0x6000d130))
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#define GPIOJ_INPUT_VAL (*(volatile unsigned long *)(0x6000d134))
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#define GPIOK_INPUT_VAL (*(volatile unsigned long *)(0x6000d138))
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#define GPIOL_INPUT_VAL (*(volatile unsigned long *)(0x6000d13c))
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#define GPIOI_INT_STAT (*(volatile unsigned long *)(0x6000d140))
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#define GPIOJ_INT_STAT (*(volatile unsigned long *)(0x6000d144))
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#define GPIOK_INT_STAT (*(volatile unsigned long *)(0x6000d148))
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#define GPIOL_INT_STAT (*(volatile unsigned long *)(0x6000d14c))
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#define GPIOI_INT_EN (*(volatile unsigned long *)(0x6000d150))
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#define GPIOJ_INT_EN (*(volatile unsigned long *)(0x6000d154))
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#define GPIOK_INT_EN (*(volatile unsigned long *)(0x6000d158))
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#define GPIOL_INT_EN (*(volatile unsigned long *)(0x6000d15c))
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#define GPIOI_INT_LEV (*(volatile unsigned long *)(0x6000d160))
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#define GPIOJ_INT_LEV (*(volatile unsigned long *)(0x6000d164))
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#define GPIOK_INT_LEV (*(volatile unsigned long *)(0x6000d168))
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#define GPIOL_INT_LEV (*(volatile unsigned long *)(0x6000d16c))
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#define GPIOI_INT_CLR (*(volatile unsigned long *)(0x6000d170))
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#define GPIOJ_INT_CLR (*(volatile unsigned long *)(0x6000d174))
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#define GPIOK_INT_CLR (*(volatile unsigned long *)(0x6000d178))
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#define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c))
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/* Standard GPIO addresses + 0x800 allow atomic port manipulation on PP502x.
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* Bits 8..15 of the written word define which bits are changed, bits 0..7
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* define the value of those bits. */
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#define GPIO_SET_BITWISE(port, mask) \
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do { *(&port + (0x800/sizeof(long))) = (mask << 8) | mask; } while(0)
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#define GPIO_CLEAR_BITWISE(port, mask) \
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do { *(&port + (0x800/sizeof(long))) = mask << 8; } while(0)
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/* Device initialization */
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#define PP_VER1 (*(volatile unsigned long *)(0x70000000))
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#define PP_VER2 (*(volatile unsigned long *)(0x70000004))
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#define STRAP_OPT_A (*(volatile unsigned long *)(0x70000008))
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#define STRAP_OPT_B (*(volatile unsigned long *)(0x7000000c))
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#define BUS_WIDTH_MASK 0x00000010
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#define RAM_TYPE_MASK 0x000000c0
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#define ROM_TYPE_MASK 0x00000008
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#define DEV_INIT1 (*(volatile unsigned long *)(0x70000010))
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#define DEV_INIT2 (*(volatile unsigned long *)(0x70000020))
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/* some timing that needs to be handled during clock setup */
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#define DEV_TIMING1 (*(volatile unsigned long *)(0x70000034))
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#define XMB_NOR_CFG (*(volatile unsigned long *)(0x70000038))
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#define XMB_RAM_CFG (*(volatile unsigned long *)(0x7000003c))
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#define INIT_BUTTONS 0x00040000
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#define INIT_PLL 0x40000000
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#define INIT_USB 0x80000000
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/* 32 bit GPO port */
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#define GPO32_VAL (*(volatile unsigned long *)(0x70000080))
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#define GPO32_ENABLE (*(volatile unsigned long *)(0x70000084))
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/* IIS */
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#define IISDIV (*(volatile unsigned long*)(0x60006080))
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#define IISCONFIG (*(volatile unsigned long*)(0x70002800))
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#define IISCLK (*(volatile unsigned long*)(0x70002808))
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#define IISFIFO_CFG (*(volatile unsigned long*)(0x7000280c))
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#define IISFIFO_WR (*(volatile unsigned long*)(0x70002840))
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#define IISFIFO_WRH (*(volatile unsigned short*)(0x70002840))
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#define IISFIFO_RD (*(volatile unsigned long*)(0x70002880))
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#define IISFIFO_RDH (*(volatile unsigned short*)(0x70002880))
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/**
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* IISCONFIG bits:
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* | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
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* | RESET | |TXFIFOEN|RXFIFOEN| | ???? | MS | ???? |
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* | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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* | | | | | | | | |
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* | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
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* | | | | | Bus Format[1:0] | Size[1:0] |
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* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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* | | Size Format[2:0] | ???? | ???? | IRQTX | IRQRX |
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*/
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/* All IIS formats send MSB first */
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#define IIS_RESET (1 << 31)
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#define IIS_TXFIFOEN (1 << 29)
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#define IIS_RXFIFOEN (1 << 28)
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#define IIS_MASTER (1 << 25)
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#define IIS_IRQTX (1 << 1)
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#define IIS_IRQRX (1 << 0)
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#define IIS_IRQTX_REG IISCONFIG
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#define IIS_IRQRX_REG IISCONFIG
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/* Data format on the IIS bus */
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#define IIS_FORMAT_MASK (0x3 << 10)
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#define IIS_FORMAT_IIS (0x0 << 10) /* Standard IIS - leading dummy bit */
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#define IIS_FORMAT_1 (0x1 << 10)
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#define IIS_FORMAT_LJUST (0x2 << 10) /* Left justified - no dummy bit */
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#define IIS_FORMAT_3 (0x3 << 10)
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/* Other formats not yet known */
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/* Data size on IIS bus */
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#define IIS_SIZE_MASK (0x3 << 8)
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#define IIS_SIZE_16BIT (0x0 << 8)
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/* Other sizes not yet known */
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/* Data size/format on IIS FIFO */
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#define IIS_FIFO_FORMAT_MASK (0x7 << 4)
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#define IIS_FIFO_FORMAT_LE_HALFWORD (0x0 << 4)
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/* Big-endian formats - data sent to the FIFO must be big endian.
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* I forgot which is which size but did test them. */
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#define IIS_FIFO_FORMAT_1 (0x1 << 4)
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#define IIS_FIFO_FORMAT_2 (0x2 << 4)
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/* 32bit-MSB-little endian */
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#define IIS_FIFO_FORMAT_LE32 (0x3 << 4)
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/* 16bit-MSB-little endian */
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#define IIS_FIFO_FORMAT_LE16 (0x4 << 4)
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#define IIS_FIFO_FORMAT_5 (0x5 << 4)
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#define IIS_FIFO_FORMAT_6 (0x6 << 4)
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/* A second one like IIS_FIFO_FORMAT_LE16? PP5020 only? */
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#define IIS_FIFO_FORMAT_LE16_2 (0x7 << 4)
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/* FIFO formats 0x5 and above seem equivalent to 0x4 ?? */
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/**
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* IISFIFO_CFG bits:
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* | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
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* | | | RXFull[5:0] |
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* | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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* | | | TXFree[5:0] |
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* | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
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* | | | | RXCLR | | | | TXCLR |
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* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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* | | | RX_FULL_LVL | | | TX_EMPTY_LVL |
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*/
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/* handy macros to extract the FIFO counts */
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#define IIS_RX_FULL_MASK (0x3f << 24)
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#define IIS_RX_FULL_COUNT \
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((IISFIFO_CFG & IIS_RX_FULL_MASK) >> 24)
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#define IIS_TX_FREE_MASK (0x3f << 16)
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#define IIS_TX_FREE_COUNT \
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((IISFIFO_CFG & IIS_TX_FREE_MASK) >> 16)
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#define IIS_RXCLR (1 << 12)
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#define IIS_TXCLR (1 << 8)
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/* Number of slots */
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#define IIS_RX_FULL_LVL_4 (0x1 << 4)
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#define IIS_RX_FULL_LVL_8 (0x2 << 4)
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#define IIS_RX_FULL_LVL_12 (0x3 << 4)
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#define IIS_TX_EMPTY_LVL_4 (0x1 << 0)
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#define IIS_TX_EMPTY_LVL_8 (0x2 << 0)
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#define IIS_TX_EMPTY_LVL_12 (0x3 << 0)
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/* Note: didn't bother to see of levels 0 and 16 actually work */
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/* First ("mono") LCD bridge */
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#define LCD1_BASE 0x70003000
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#define LCD1_CONTROL (*(volatile unsigned long *)(0x70003000))
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#define LCD1_CMD (*(volatile unsigned long *)(0x70003008))
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#define LCD1_DATA (*(volatile unsigned long *)(0x70003010))
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#define LCD1_BUSY_MASK 0x8000
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/* Serial Controller */
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#define SER0_BASE (*(volatile unsigned long*)(0x70006000))
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#define SER0_RBR (*(volatile unsigned long*)(0x70006000))
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#define SER0_THR (*(volatile unsigned long*)(0x70006000))
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#define SER0_IER (*(volatile unsigned long*)(0x70006004))
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#define SER0_FCR (*(volatile unsigned long*)(0x70006008))
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#define SER0_IIR (*(volatile unsigned long*)(0x70006008))
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#define SER0_LCR (*(volatile unsigned long*)(0x7000600c))
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#define SER0_MCR (*(volatile unsigned long*)(0x70006010))
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#define SER0_LSR (*(volatile unsigned long*)(0x70006014))
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#define SER0_MSR (*(volatile unsigned long*)(0x70006018))
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#define SER0_SPR (*(volatile unsigned long*)(0x7000601c))
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#define SER0_DLL (*(volatile unsigned long*)(0x70006000))
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#define SER0_DLM (*(volatile unsigned long*)(0x70006004))
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#define SER1_BASE (*(volatile unsigned long*)(0x70006040))
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#define SER1_RBR (*(volatile unsigned long*)(0x70006040))
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#define SER1_THR (*(volatile unsigned long*)(0x70006040))
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#define SER1_IER (*(volatile unsigned long*)(0x70006044))
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#define SER1_FCR (*(volatile unsigned long*)(0x70006048))
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#define SER1_IIR (*(volatile unsigned long*)(0x70006048))
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#define SER1_LCR (*(volatile unsigned long*)(0x7000604c))
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#define SER1_MCR (*(volatile unsigned long*)(0x70006050))
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#define SER1_LSR (*(volatile unsigned long*)(0x70006054))
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#define SER1_MSR (*(volatile unsigned long*)(0x70006058))
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#define SER1_SPR (*(volatile unsigned long*)(0x7000605c))
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#define SER1_DLL (*(volatile unsigned long*)(0x70006040))
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#define SER1_DLM (*(volatile unsigned long*)(0x70006044))
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/* Second ("color") LCD bridge */
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#define LCD2_BASE 0x70008a00
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#define LCD2_PORT (*(volatile unsigned long*)(0x70008a0c))
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#define LCD2_BLOCK_CTRL (*(volatile unsigned long*)(0x70008a20))
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#define LCD2_BLOCK_CONFIG (*(volatile unsigned long*)(0x70008a24))
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#define LCD2_BLOCK_DATA (*(volatile unsigned long*)(0x70008b00))
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#define LCD2_BUSY_MASK 0x80000000
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#define LCD2_CMD_MASK 0x80000000
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#define LCD2_DATA_MASK 0x81000000
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#define LCD2_BLOCK_READY 0x04000000
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#define LCD2_BLOCK_TXOK 0x01000000
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/* I2C */
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#define I2C_BASE 0x7000c000
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/* EIDE Controller */
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#define IDE_BASE 0xc3000000
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#define IDE0_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000000))
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#define IDE0_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000004))
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#define IDE0_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000008))
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#define IDE0_SEC_TIMING1 (*(volatile unsigned long*)(0xc300000c))
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#define IDE1_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000010))
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#define IDE1_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000014))
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#define IDE1_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000018))
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#define IDE1_SEC_TIMING1 (*(volatile unsigned long*)(0xc300001c))
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#define IDE0_CFG (*(volatile unsigned long*)(0xc3000028))
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#define IDE1_CFG (*(volatile unsigned long*)(0xc300002c))
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#define IDE0_CNTRLR_STAT (*(volatile unsigned long*)(0xc30001e0))
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/* USB controller */
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#define USB_BASE 0xc5000000
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/* Firewire Controller */
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#define FIREWIRE_BASE 0xc6000000
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/* Memory controller */
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#define CACHE_BASE (*(volatile unsigned long*)(0xf0000000))
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/* 0xf0000000-0xf0001fff */
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#define CACHE_DATA_BASE (*(volatile unsigned long*)(0xf0000000))
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/* 0xf0002000-0xf0003fff */
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#define CACHE_DATA_MIRROR_BASE (*(volatile unsigned long*)(0xf0002000))
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/* 0xf0004000-0xf0007fff */
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#define CACHE_STATUS_BASE (*(volatile unsigned long*)(0xf0004000))
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#define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000))
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#define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000))
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#define MMAP_PHYS_READ_MASK 0x0100
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#define MMAP_PHYS_WRITE_MASK 0x0200
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#define MMAP_PHYS_DATA_MASK 0x0400
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#define MMAP_PHYS_CODE_MASK 0x0800
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#define MMAP_FIRST (*(volatile unsigned long*)(0xf000f000))
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#define MMAP_LAST (*(volatile unsigned long*)(0xf000f03c))
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#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
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#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
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#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))
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#define MMAP1_PHYSICAL (*(volatile unsigned long*)(0xf000f00c))
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#define MMAP2_LOGICAL (*(volatile unsigned long*)(0xf000f010))
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#define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014))
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#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018))
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#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c))
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#define MMAP4_LOGICAL (*(volatile unsigned long*)(0xf000f020))
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#define MMAP4_PHYSICAL (*(volatile unsigned long*)(0xf000f024))
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#define MMAP5_LOGICAL (*(volatile unsigned long*)(0xf000f028))
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#define MMAP5_PHYSICAL (*(volatile unsigned long*)(0xf000f02c))
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#define MMAP6_LOGICAL (*(volatile unsigned long*)(0xf000f030))
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#define MMAP6_PHYSICAL (*(volatile unsigned long*)(0xf000f034))
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#define MMAP7_LOGICAL (*(volatile unsigned long*)(0xf000f038))
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#define MMAP7_PHYSICAL (*(volatile unsigned long*)(0xf000f03c))
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#endif /* __PP5020_H__ */
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