4ed78f5c72
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19716 a1c6a512-1295-4272-9138-f99709370657
317 lines
8.3 KiB
C
317 lines
8.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: $
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*
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* Copyright (C) 2007 by Tomasz Malesinski
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdlib.h>
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#include "pnx0101.h"
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#include "system.h"
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static struct
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{
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unsigned char freq;
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unsigned char sys_mult;
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unsigned char sys_div;
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}
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perf_modes[3] ICONST_ATTR =
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{
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{12, 4, 4},
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{48, 4, 1},
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{60, 5, 1}
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};
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static int performance_mode, bus_divider;
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static void cgu_set_sel_stage_input(int clock, int input)
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{
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int s = CGU.base_ssr[clock];
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if (s & 1)
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CGU.base_fs2[clock] = input;
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else
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CGU.base_fs1[clock] = input;
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CGU.base_scr[clock] = (s & 3) ^ 3;
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}
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static void cgu_reset_sel_stage_clocks(int first_esr, int n_esr,
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int first_div, int n_div)
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{
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int i;
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for (i = 0; i < n_esr; i++)
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CGU.clk_esr[first_esr + i] = 0;
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for (i = 0; i < n_div; i++)
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CGU.base_fdc[first_div + i] = 0;
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}
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static void cgu_configure_div(int div, int n, int m)
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{
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int msub, madd, div_size, max_n;
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unsigned long cfg;
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if (n == m)
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{
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CGU.base_fdc[div] = CGU.base_fdc[div] & ~1;
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return;
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}
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msub = -n;
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madd = m - n;
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div_size = (div == PNX0101_HIPREC_FDC) ? 10 : 8;
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max_n = 1 << div_size;
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while ((madd << 1) < max_n && (msub << 1) >= -max_n)
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{
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madd <<= 1;
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msub <<= 1;
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}
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cfg = (((msub << div_size) | madd) << 3) | 4;
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CGU.base_fdc[div] = CGU.base_fdc[div] & ~1;
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CGU.base_fdc[div] = cfg | 2;
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CGU.base_fdc[div] = cfg;
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CGU.base_fdc[div] = cfg | 1;
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}
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static void cgu_connect_div_to_clock(int rel_div, int esr)
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{
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CGU.clk_esr[esr] = (rel_div << 1) | 1;
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}
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static void cgu_enable_clock(int clock)
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{
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CGU.clk_pcr[clock] |= 1;
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}
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static void cgu_start_sel_stage_dividers(int bcr)
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{
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CGU.base_bcr[bcr] = 1;
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}
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/* Convert a pointer that points to IRAM (0x4xxxx) to a pointer that
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points to the uncached page (0x0xxxx) that is also mapped to IRAM. */
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static inline void *noncached(void *p)
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{
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return (void *)(((unsigned long)p) & 0xffff);
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}
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/* To avoid SRAM accesses while changing memory controller settings we
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run this routine from uncached copy of IRAM. All times are in CPU
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cycles. At CPU frequencies lower than 60 MHz we could use faster
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settings, but since DMA may access SRAM at any time, changing
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memory timings together with CPU frequency would be tricky. */
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static void do_set_mem_timings(void) ICODE_ATTR;
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static void do_set_mem_timings(void)
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{
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int old_irq = disable_irq_save();
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while ((EMC.status & 3) != 0);
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EMC.control = 5;
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EMCSTATIC0.waitrd = 6;
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EMCSTATIC0.waitwr = 5;
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EMCSTATIC1.waitrd = 5;
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EMCSTATIC1.waitwr = 4; /* OF uses 5 here */
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EMCSTATIC2.waitrd = 4;
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EMCSTATIC2.waitwr = 3;
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EMCSTATIC0.waitoen = 1;
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EMCSTATIC1.waitoen = 1;
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EMCSTATIC2.waitoen = 1;
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/* Enable write buffers for SRAM. */
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#ifndef DEBUG
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EMCSTATIC1.config = 0x80081;
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#endif
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EMC.control = 1;
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restore_irq(old_irq);
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}
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static void emc_set_mem_timings(void)
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{
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void (*f)(void) = noncached(do_set_mem_timings);
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(*f)();
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}
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static void cgu_set_sys_mult(int i)
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{
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cgu_set_sel_stage_input(PNX0101_SEL_STAGE_SYS, PNX0101_MAIN_CLOCK_FAST);
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cgu_set_sel_stage_input(PNX0101_SEL_STAGE_APB3, PNX0101_MAIN_CLOCK_FAST);
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PLL.lppdn = 1;
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PLL.lpfin = 1;
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PLL.lpmbyp = 0;
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PLL.lpdbyp = 0;
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PLL.lppsel = 1;
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PLL.lpmsel = i - 1;
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PLL.lppdn = 0;
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while (!PLL.lplock);
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cgu_configure_div(PNX0101_FIRST_DIV_SYS + 1, 1, (i == 5) ? 15 : 12);
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cgu_connect_div_to_clock(1, 0x11);
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cgu_enable_clock(0x11);
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cgu_start_sel_stage_dividers(PNX0101_BCR_SYS);
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cgu_set_sel_stage_input(PNX0101_SEL_STAGE_SYS,
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PNX0101_MAIN_CLOCK_MAIN_PLL);
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cgu_set_sel_stage_input(PNX0101_SEL_STAGE_APB3,
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PNX0101_MAIN_CLOCK_MAIN_PLL);
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}
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static void pnx0101_set_performance_mode(int mode)
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{
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int old = performance_mode;
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if (perf_modes[old].sys_mult != perf_modes[mode].sys_mult)
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cgu_set_sys_mult(perf_modes[mode].sys_mult);
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if (perf_modes[old].sys_div != perf_modes[mode].sys_div)
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cgu_configure_div(bus_divider, 1, perf_modes[mode].sys_div);
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performance_mode = mode;
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}
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static void pnx0101_init_clocks(void)
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{
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bus_divider = PNX0101_FIRST_DIV_SYS + (CGU.clk_esr[0] >> 1);
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performance_mode = 0;
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emc_set_mem_timings();
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pnx0101_set_performance_mode(2);
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cgu_set_sel_stage_input(PNX0101_SEL_STAGE_APB1,
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PNX0101_MAIN_CLOCK_FAST);
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cgu_reset_sel_stage_clocks(PNX0101_FIRST_ESR_APB1, PNX0101_N_ESR_APB1,
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PNX0101_FIRST_DIV_APB1, PNX0101_N_DIV_APB1);
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cgu_configure_div(PNX0101_FIRST_DIV_APB1, 1, 4);
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cgu_connect_div_to_clock(0, PNX0101_ESR_APB1);
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cgu_connect_div_to_clock(0, PNX0101_ESR_T0);
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cgu_connect_div_to_clock(0, PNX0101_ESR_T1);
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cgu_connect_div_to_clock(0, PNX0101_ESR_I2C);
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cgu_enable_clock(PNX0101_CLOCK_APB1);
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cgu_enable_clock(PNX0101_CLOCK_T0);
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cgu_enable_clock(PNX0101_CLOCK_T1);
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cgu_enable_clock(PNX0101_CLOCK_I2C);
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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switch (frequency)
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{
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case CPUFREQ_MAX:
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pnx0101_set_performance_mode(2);
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cpu_frequency = CPUFREQ_MAX;
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break;
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case CPUFREQ_NORMAL:
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pnx0101_set_performance_mode(1);
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cpu_frequency = CPUFREQ_NORMAL;
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break;
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case CPUFREQ_DEFAULT:
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default:
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pnx0101_set_performance_mode(0);
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cpu_frequency = CPUFREQ_DEFAULT;
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break;
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}
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}
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#endif
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interrupt_handler_t interrupt_vector[0x1d] __attribute__ ((section(".idata")));
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#define IRQ_READ(reg, dest) \
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do { unsigned long v2; \
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do { \
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dest = (reg); \
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v2 = (reg); \
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} while ((dest != v2)); \
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} while (0);
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#define IRQ_WRITE_WAIT(reg, val, cond) \
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do { unsigned long v, v2; \
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do { \
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(reg) = (val); \
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v = (reg); \
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v2 = (reg); \
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} while ((v != v2) || !(cond)); \
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} while (0);
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static void undefined_int(void)
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{
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}
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void irq(void)
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{
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unsigned long n;
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IRQ_READ(INTVECTOR[0], n)
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(*(interrupt_vector[n >> 3]))();
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}
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void fiq(void)
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{
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}
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void irq_enable_int(int n)
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{
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IRQ_WRITE_WAIT(INTREQ[n], INTREQ_WEENABLE | INTREQ_ENABLE, v & 0x10000);
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}
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void irq_disable_int(int n)
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{
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IRQ_WRITE_WAIT(INTREQ[n], INTREQ_WEENABLE, (v & 0x10000) == 0);
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}
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void irq_set_int_handler(int n, interrupt_handler_t handler)
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{
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interrupt_vector[n] = handler;
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}
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void system_init(void)
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{
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int i;
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/* turn off watchdog */
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(*(volatile unsigned long *)0x80002804) = 0;
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/*
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IRQ_WRITE_WAIT(INTVECTOR[0], 0, v == 0);
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IRQ_WRITE_WAIT(INTVECTOR[1], 0, v == 0);
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IRQ_WRITE_WAIT(INTPRIOMASK[0], 0, v == 0);
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IRQ_WRITE_WAIT(INTPRIOMASK[1], 0, v == 0);
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*/
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for (i = 1; i <= 0x1c; i++)
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{
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IRQ_WRITE_WAIT(INTREQ[i],
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INTREQ_WEPRIO | INTREQ_WETARGET |
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INTREQ_WEENABLE | INTREQ_WEACTVLO | 1,
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(v & 0x3010f) == 1);
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IRQ_WRITE_WAIT(INTREQ[i], INTREQ_WEENABLE, (v & 0x10000) == 0);
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IRQ_WRITE_WAIT(INTREQ[i], INTREQ_WEPRIO | 1, (v & 0xf) == 1);
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interrupt_vector[i] = undefined_int;
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}
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interrupt_vector[0] = undefined_int;
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pnx0101_init_clocks();
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}
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void system_reboot(void)
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{
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(*(volatile unsigned long *)0x80002804) = 1;
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while (1);
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}
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void system_exception_wait(void)
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{
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while (1);
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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