250 lines
No EOL
9.5 KiB
C
250 lines
No EOL
9.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "dcp-imx233.h"
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#include "string.h"
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#include "kernel-imx233.h"
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/* The hardware uses 160 bytes of storage to enable context switching */
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static uint8_t dcp_context[160] NOCACHEBSS_ATTR;
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/* Channel arbiter */
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static struct channel_arbiter_t channel_arbiter;
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/* Channel packets */
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static struct imx233_dcp_packet_t channel_packet[HW_DCP_NUM_CHANNELS];
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/* completion semaphore */
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static struct semaphore channel_sema[HW_DCP_NUM_CHANNELS];
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void INT_DCP(void)
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{
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/* clear interrupt and wakeup completion handler */
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for(int i = 0; i < HW_DCP_NUM_CHANNELS; i++)
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{
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if(HW_DCP_STAT & HW_DCP_STAT__IRQ(i))
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{
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__REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(i);
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semaphore_release(&channel_sema[i]);
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}
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}
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}
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void imx233_dcp_init(void)
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{
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/* Reset block */
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imx233_reset_block(&HW_DCP_CTRL);
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/* Setup contexte pointer */
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HW_DCP_CONTEXT = (uint32_t)PHYSICAL_ADDR(&dcp_context);
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/* Enable context switching and caching */
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__REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__ENABLE_CONTEXT_CACHING |
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HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING;
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/* Check that there are sufficiently many channels */
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if(__XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS) != HW_DCP_NUM_CHANNELS)
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panicf("DCP has %lu channels but was configured to use %d !",
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__XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS), HW_DCP_NUM_CHANNELS);
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/* Setup channel arbiter to use */
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arbiter_init(&channel_arbiter, HW_DCP_NUM_CHANNELS);
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/* Merge channel0 interrupt */
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__REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED;
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/* setup semaphores */
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for(int i = 0; i< HW_DCP_NUM_CHANNELS; i++)
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semaphore_init(&channel_sema[i], 1, 0);
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}
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// return OBJ_WAIT_TIMEOUT on failure
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int imx233_dcp_acquire_channel(int timeout)
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{
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return arbiter_acquire(&channel_arbiter, timeout);
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}
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void imx233_dcp_release_channel(int chan)
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{
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arbiter_release(&channel_arbiter, chan);
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}
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// doesn't check that channel is in use!
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void imx233_dcp_reserve_channel(int channel)
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{
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arbiter_reserve(&channel_arbiter, channel);
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}
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static enum imx233_dcp_error_t get_error_status(int ch)
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{
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uint32_t stat = channel_packet[ch].status;
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if(stat & HW_DCP_STATUS__ERROR_SETUP)
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return DCP_ERROR_SETUP;
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if(stat & HW_DCP_STATUS__ERROR_PACKET)
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return DCP_ERROR_PACKET;
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if(stat & HW_DCP_STATUS__ERROR_SRC)
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return DCP_ERROR_SRC;
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if(stat & HW_DCP_STATUS__ERROR_DST)
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return DCP_ERROR_DST;
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switch(__XTRACT_EX(stat, HW_DCP_STATUS__ERROR_CODE))
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{
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case 0: return DCP_SUCCESS;
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case 1: return DCP_ERROR_CHAIN_IS_0;
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case 2: return DCP_ERROR_NO_CHAIN;
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case 3: return DCP_ERROR_CONTEXT;
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case 4: return DCP_ERROR_PAYLOAD;
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case 5: return DCP_ERROR_MODE;
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default: return DCP_ERROR;
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}
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}
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static enum imx233_dcp_error_t imx233_dcp_job(int ch)
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{
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/* if IRQs are not enabled, don't enable channel interrupt and do some polling */
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bool irq_enabled = irq_enabled();
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/* enable channel, clear interrupt, enable interrupt */
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imx233_icoll_enable_interrupt(INT_SRC_DCP, true);
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if(irq_enabled)
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__REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(ch);
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__REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(ch);
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__REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(ch);
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/* write back packet */
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commit_discard_dcache_range(&channel_packet[ch], sizeof(struct imx233_dcp_packet_t));
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/* write 1 to semaphore to run job */
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HW_DCP_CHxCMDPTR(ch) = (uint32_t)PHYSICAL_ADDR(&channel_packet[ch]);
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HW_DCP_CHxSEMA(ch) = 1;
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/* wait completion */
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if(irq_enabled)
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semaphore_wait(&channel_sema[ch], TIMEOUT_BLOCK);
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else
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while(__XTRACT_EX(HW_DCP_CHxSEMA(ch), HW_DCP_CHxSEMA__VALUE))
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udelay(10);
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/* disable channel and interrupt */
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__REG_CLR(HW_DCP_CTRL) = HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(ch);
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__REG_CLR(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(ch);
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/* read status */
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return get_error_status(ch);
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}
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enum imx233_dcp_error_t imx233_dcp_memcpy_ex(int ch, bool fill, const void *src, void *dst, size_t len)
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{
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/* prepare packet */
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channel_packet[ch].next = 0;
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channel_packet[ch].ctrl0 = HW_DCP_CTRL0__INTERRUPT_ENABLE |
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HW_DCP_CTRL0__ENABLE_MEMCOPY | HW_DCP_CTRL0__DECR_SEMAPHORE |
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(fill ? HW_DCP_CTRL0__CONSTANT_FILL : 0);
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channel_packet[ch].ctrl1 = 0;
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channel_packet[ch].src = (uint32_t)(fill ? src : PHYSICAL_ADDR(src));
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channel_packet[ch].dst = (uint32_t)PHYSICAL_ADDR(dst);
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channel_packet[ch].size = len;
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channel_packet[ch].payload = 0;
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channel_packet[ch].status = 0;
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/* write-back src if not filling, discard dst */
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if(!fill)
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commit_discard_dcache_range(src, len);
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discard_dcache_range(dst, len);
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/* do the job */
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return imx233_dcp_job(ch);
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}
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enum imx233_dcp_error_t imx233_dcp_memcpy(bool fill, const void *src, void *dst, size_t len, int tmo)
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{
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int chan = imx233_dcp_acquire_channel(tmo);
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if(chan == OBJ_WAIT_TIMEDOUT)
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return DCP_TIMEOUT;
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enum imx233_dcp_error_t err = imx233_dcp_memcpy_ex(chan, fill, src, dst, len);
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imx233_dcp_release_channel(chan);
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return err;
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}
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enum imx233_dcp_error_t imx233_dcp_blit_ex(int ch, bool fill, const void *src, size_t w, size_t h, void *dst, size_t out_w)
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{
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/* prepare packet */
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channel_packet[ch].next = 0;
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channel_packet[ch].ctrl0 = HW_DCP_CTRL0__INTERRUPT_ENABLE |
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HW_DCP_CTRL0__ENABLE_MEMCOPY | HW_DCP_CTRL0__DECR_SEMAPHORE |
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HW_DCP_CTRL0__ENABLE_BLIT |
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(fill ? HW_DCP_CTRL0__CONSTANT_FILL : 0);
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channel_packet[ch].ctrl1 = out_w;
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channel_packet[ch].src = (uint32_t)(fill ? src : PHYSICAL_ADDR(src));
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channel_packet[ch].dst = (uint32_t)PHYSICAL_ADDR(dst);
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channel_packet[ch].size = w | h << HW_DCP_SIZE__NUMBER_LINES_BP;
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channel_packet[ch].payload = 0;
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channel_packet[ch].status = 0;
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/* we have a problem here to discard the output buffer since it's not contiguous
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* so only commit the source */
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if(!fill)
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commit_discard_dcache_range(src, w * h);
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/* do the job */
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return imx233_dcp_job(ch);
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}
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enum imx233_dcp_error_t imx233_dcp_blit(bool fill, const void *src, size_t w, size_t h, void *dst, size_t out_w, int tmo)
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{
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int chan = imx233_dcp_acquire_channel(tmo);
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if(chan == OBJ_WAIT_TIMEDOUT)
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return DCP_TIMEOUT;
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enum imx233_dcp_error_t err = imx233_dcp_blit_ex(chan, fill, src, w, h, dst, out_w);
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imx233_dcp_release_channel(chan);
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return err;
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}
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struct imx233_dcp_info_t imx233_dcp_get_info(unsigned flags)
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{
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struct imx233_dcp_info_t info;
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memset(&info, 0, sizeof(info));
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if(flags & DCP_INFO_CAPABILITIES)
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{
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info.has_crypto = HW_DCP_CTRL & HW_DCP_CTRL__PRESENT_CRYPTO;
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info.has_csc = HW_DCP_CTRL & HW_DCP_CTRL__PRESENT_CSC;
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info.num_keys = __XTRACT(HW_DCP_CAPABILITY0, NUM_KEYS);
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info.num_channels = __XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS);
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info.ciphers = __XTRACT(HW_DCP_CAPABILITY1, CIPHER_ALGORITHMS);
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info.hashs = __XTRACT(HW_DCP_CAPABILITY1, HASH_ALGORITHMS);
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}
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if(flags & DCP_INFO_GLOBAL_STATE)
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{
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info.otp_key_ready = HW_DCP_STAT & HW_DCP_STAT__OTP_KEY_READY;
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info.context_switching = HW_DCP_CTRL & HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING;
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info.context_caching = HW_DCP_CTRL & HW_DCP_CTRL__ENABLE_CONTEXT_CACHING;
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info.gather_writes = HW_DCP_CTRL & HW_DCP_CTRL__GATHER_RESIDUAL_WRITES;
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info.ch0_merged = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED;
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}
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if(flags & DCP_INFO_CHANNELS)
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{
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for(int i = 0; i < HW_DCP_NUM_CHANNELS; i++)
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{
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info.channel[i].irq_en = HW_DCP_CTRL & HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(i);
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info.channel[i].irq = HW_DCP_STAT & HW_DCP_STAT__IRQ(i);
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info.channel[i].ready = HW_DCP_STAT & HW_DCP_STAT__READY_CHANNELS(i);
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info.channel[i].high_priority = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL(i);
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info.channel[i].enable = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(i);
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info.channel[i].sema = __XTRACT_EX(HW_DCP_CHxSEMA(i), HW_DCP_CHxSEMA__VALUE);
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info.channel[i].cmdptr = HW_DCP_CHxCMDPTR(i);
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info.channel[i].acquired = arbiter_acquired(&channel_arbiter, i);
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}
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}
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if(flags & DCP_INFO_CSC)
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{
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info.csc.irq_en = HW_DCP_CTRL & HW_DCP_CTRL__CSC_INTERRUPT_ENABLE;
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info.csc.irq = HW_DCP_STAT & HW_DCP_STAT__CSCIRQ;
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info.csc.priority = __XTRACT(HW_DCP_CHANNELCTRL, CSC_PRIORITY);
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info.csc.enable = HW_DCP_CSCCTRL0 & HW_DCP_CSCCTRL0__ENABLE;
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}
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return info;
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} |