2f16d4f1b3
Changes made: Combine bootloader/h10.c and bootloader/e200.c into a common bootloader file (bootloader/main-pp.c) to be used by all mi4 based PortalPlayer targets. The file bootloader/main-pp.c is based off the old bootloader/h10.c with some minor changes to allow it to work on the Sansa too. This effectively adds a Sansa bootloader. Define MODEL_NAME string in config-*.h for use in bootloader. Split crt0-pp.S into separate files for bootloader and normal builds. Bootloader code is now in crt0-pp-bl.S while normal build code stays in crt0-pp.S. Improvements to crt0-pp.S and crt0-pp-bl.S (mostly to make it more multiprocessor safe): * Leave space in bootloader at 0xe0-0xeb since scramble writes over there when it creates the mi4 file (don't leave space for iPods since it's not needed and all code in crt0-pp-bl.S needs to fit before the boot_table at 0x100). * Remove unused DEBUG and STUB code from crt0-pp.S. * Make CPU wait for COP to be sleeping when we put the COP to sleep. * Invalidate COP cache when COP wakes * Flush CPU cache before waking COP * Make sure only the CPU clears the BSS (not the COP) * Make sure only the CPU sets up its own stack (not the COP) Rolo works on H10, so enable it. Make Sansa e200 use rockbox.e200 rather than PP5022.mi4 for 'Normal' builds. This makes updating rockbox simpler as we don't need to go through the firmware update procedure, but rather just put a new rockbox.e200 on the device. rockbox.e200 uses a simple 'add' checksum. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11815 a1c6a512-1295-4272-9138-f99709370657
222 lines
4.1 KiB
Text
222 lines
4.1 KiB
Text
#include "config.h"
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ENTRY(start)
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#ifdef CPU_COLDFIRE
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OUTPUT_FORMAT(elf32-m68k)
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INPUT(target/coldfire/crt0.o)
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#elif defined (CPU_ARM)
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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#ifdef CPU_PP
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INPUT(target/arm/crt0-pp-bl.o)
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#else
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INPUT(target/arm/crt0.o)
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#endif
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#else
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OUTPUT_FORMAT(elf32-sh)
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INPUT(target/sh/crt0.o)
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#endif
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#define DRAMSIZE (MEMORYSIZE * 0x100000)
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#ifdef IRIVER_H100_SERIES
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#define DRAMORIG 0x31000000
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#define IRAMORIG 0x10000000
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#define IRAMSIZE 0x18000
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#define FLASHORIG 0x001f0000
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#define FLASHSIZE 2M
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#elif defined(IRIVER_H300_SERIES)
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#define DRAMORIG 0x31000000
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#define IRAMORIG 0x10000000
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#define IRAMSIZE 0x18000
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#define FLASHORIG 0x003f0000
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#define FLASHSIZE 4M
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#elif defined(IAUDIO_X5)
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#define DRAMORIG 0x31000000
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#define IRAMORIG 0x10000000
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#define IRAMSIZE 0x20000
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#define FLASHORIG 0x00010000
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#define FLASHSIZE 4M
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#elif CONFIG_CPU == PP5020
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#define DRAMORIG 0x10000000
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 0x18000
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#define FLASHORIG 0x001f0000
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#define FLASHSIZE 2M
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#elif CONFIG_CPU == PP5024
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#define DRAMORIG 0x10000000
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 0x18000
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#define FLASHORIG 0x001f0000
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#define FLASHSIZE 2M
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#elif CONFIG_CPU == S3C2440
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#define DRAMORIG 0x30000000
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 4K
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#define FLASHORIG 0x0000000
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#define FLASHSIZE 1M
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#elif CONFIG_CPU == PP5002
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#define DRAMORIG 0x28000000
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 0x18000
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#define FLASHORIG 0x001f0000
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#define FLASHSIZE 2M
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#else
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#define DRAMORIG 0x09000000
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#define IRAMORIG 0x0f000000
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#define IRAMSIZE 0x1000
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#define FLASHORIG 0x02000000 + ROM_START
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#define FLASHSIZE 256K - ROM_START
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#endif
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#if !defined(CPU_PP) && (CONFIG_CPU!=S3C2440)
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MEMORY
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{
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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FLASH : ORIGIN = FLASHORIG, LENGTH = FLASHSIZE
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}
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#endif
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SECTIONS
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#ifdef CPU_PP
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{
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. = IRAMORIG;
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.text : {
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*(.init.text)
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*(.text)
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}
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.data : {
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*(.icode)
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*(.irodata)
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*(.idata)
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*(.data)
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_dataend = . ;
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}
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.stack :
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{
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*(.stack)
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_stackbegin = .;
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stackbegin = .;
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. += 0x2000;
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_stackend = .;
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stackend = .;
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}
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/* The bss section is too large for IRAM - we just move it 16MB into the
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DRAM */
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. = (DRAMORIG+16*1024*1024);
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.bss : {
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_edata = .;
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*(.bss);
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*(.ibss);
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_end = .;
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}
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}
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#elif (CONFIG_CPU==S3C2440)
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{
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. = DRAMORIG + 0x8000;
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.text : {
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*(.init.text)
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*(.text)
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}
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.data : {
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*(.icode)
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*(.irodata)
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*(.idata)
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*(.data)
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_dataend = . ;
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}
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.stack :
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{
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*(.stack)
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_stackbegin = .;
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stackbegin = .;
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. += 0x2000;
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_stackend = .;
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stackend = .;
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}
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.bss : {
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_edata = .;
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*(.bss);
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*(.ibss);
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_end = .;
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}
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}
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#else
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{
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.vectors :
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{
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#ifdef IAUDIO_X5
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*(.init.text)
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#endif
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_datacopy = .;
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} > FLASH
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.data : AT ( _datacopy )
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{
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_datastart = .;
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*(.resetvectors);
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*(.vectors);
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. = ALIGN(0x200);
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*(.icode)
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*(.irodata)
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*(.idata)
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*(.data)
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. = ALIGN(0x4);
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_dataend = .;
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. = ALIGN(0x10); /* Maintain proper alignment for .text section */
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} > IRAM
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/* TRICK ALERT! Newer versions of the linker don't allow output sections
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to overlap even if one of them is empty, so advance the location pointer
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"by hand" */
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.text LOADADDR(.data) + SIZEOF(.data) :
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{
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*(.init.text)
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*(.text)
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. = ALIGN(0x4);
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} > FLASH
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.rodata :
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{
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*(.rodata)
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*(.rodata.str1.1)
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*(.rodata.str1.4)
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. = ALIGN(0x4);
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_iramcopy = .;
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} > FLASH
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.stack :
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{
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*(.stack)
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_stackbegin = .;
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stackbegin = .;
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. += 0x2000;
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_stackend = .;
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stackend = .;
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} > IRAM
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#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES) || defined(IAUDIO_X5)
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.bss DRAMORIG+0x800000:
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#else
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.bss :
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#endif
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{
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_edata = .;
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*(.ibss)
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*(.bss)
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*(COMMON)
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_end = .;
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#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES) || defined(IAUDIO_X5)
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} > DRAM
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#else
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} > IRAM
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#endif
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}
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#endif
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