481 lines
24 KiB
C
481 lines
24 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* x1000 version: 1.0
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* x1000 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_SFC_H__
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#define __HEADERGEN_SFC_H__
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#include "macro.h"
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#define REG_SFC_GLB jz_reg(SFC_GLB)
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#define JA_SFC_GLB (0xb3440000 + 0x0)
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#define JT_SFC_GLB JIO_32_RW
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#define JN_SFC_GLB SFC_GLB
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#define JI_SFC_GLB
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#define BP_SFC_GLB_THRESHOLD 7
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#define BM_SFC_GLB_THRESHOLD 0x1f80
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#define BF_SFC_GLB_THRESHOLD(v) (((v) & 0x3f) << 7)
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#define BFM_SFC_GLB_THRESHOLD(v) BM_SFC_GLB_THRESHOLD
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#define BF_SFC_GLB_THRESHOLD_V(e) BF_SFC_GLB_THRESHOLD(BV_SFC_GLB_THRESHOLD__##e)
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#define BFM_SFC_GLB_THRESHOLD_V(v) BM_SFC_GLB_THRESHOLD
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#define BP_SFC_GLB_PHASE_NUM 3
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#define BM_SFC_GLB_PHASE_NUM 0x38
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#define BF_SFC_GLB_PHASE_NUM(v) (((v) & 0x7) << 3)
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#define BFM_SFC_GLB_PHASE_NUM(v) BM_SFC_GLB_PHASE_NUM
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#define BF_SFC_GLB_PHASE_NUM_V(e) BF_SFC_GLB_PHASE_NUM(BV_SFC_GLB_PHASE_NUM__##e)
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#define BFM_SFC_GLB_PHASE_NUM_V(v) BM_SFC_GLB_PHASE_NUM
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#define BP_SFC_GLB_TRAN_DIR 13
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#define BM_SFC_GLB_TRAN_DIR 0x2000
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#define BV_SFC_GLB_TRAN_DIR__READ 0x0
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#define BV_SFC_GLB_TRAN_DIR__WRITE 0x1
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#define BF_SFC_GLB_TRAN_DIR(v) (((v) & 0x1) << 13)
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#define BFM_SFC_GLB_TRAN_DIR(v) BM_SFC_GLB_TRAN_DIR
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#define BF_SFC_GLB_TRAN_DIR_V(e) BF_SFC_GLB_TRAN_DIR(BV_SFC_GLB_TRAN_DIR__##e)
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#define BFM_SFC_GLB_TRAN_DIR_V(v) BM_SFC_GLB_TRAN_DIR
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#define BP_SFC_GLB_OP_MODE 6
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#define BM_SFC_GLB_OP_MODE 0x40
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#define BV_SFC_GLB_OP_MODE__SLAVE 0x0
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#define BV_SFC_GLB_OP_MODE__DMA 0x1
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#define BF_SFC_GLB_OP_MODE(v) (((v) & 0x1) << 6)
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#define BFM_SFC_GLB_OP_MODE(v) BM_SFC_GLB_OP_MODE
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#define BF_SFC_GLB_OP_MODE_V(e) BF_SFC_GLB_OP_MODE(BV_SFC_GLB_OP_MODE__##e)
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#define BFM_SFC_GLB_OP_MODE_V(v) BM_SFC_GLB_OP_MODE
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#define BP_SFC_GLB_WP_EN 2
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#define BM_SFC_GLB_WP_EN 0x4
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#define BF_SFC_GLB_WP_EN(v) (((v) & 0x1) << 2)
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#define BFM_SFC_GLB_WP_EN(v) BM_SFC_GLB_WP_EN
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#define BF_SFC_GLB_WP_EN_V(e) BF_SFC_GLB_WP_EN(BV_SFC_GLB_WP_EN__##e)
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#define BFM_SFC_GLB_WP_EN_V(v) BM_SFC_GLB_WP_EN
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#define BP_SFC_GLB_BURST_MD 0
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#define BM_SFC_GLB_BURST_MD 0x3
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#define BV_SFC_GLB_BURST_MD__INCR4 0x0
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#define BV_SFC_GLB_BURST_MD__INCR8 0x1
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#define BV_SFC_GLB_BURST_MD__INCR16 0x2
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#define BV_SFC_GLB_BURST_MD__INCR32 0x3
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#define BF_SFC_GLB_BURST_MD(v) (((v) & 0x3) << 0)
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#define BFM_SFC_GLB_BURST_MD(v) BM_SFC_GLB_BURST_MD
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#define BF_SFC_GLB_BURST_MD_V(e) BF_SFC_GLB_BURST_MD(BV_SFC_GLB_BURST_MD__##e)
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#define BFM_SFC_GLB_BURST_MD_V(v) BM_SFC_GLB_BURST_MD
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#define REG_SFC_DEV_CONF jz_reg(SFC_DEV_CONF)
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#define JA_SFC_DEV_CONF (0xb3440000 + 0x4)
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#define JT_SFC_DEV_CONF JIO_32_RW
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#define JN_SFC_DEV_CONF SFC_DEV_CONF
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#define JI_SFC_DEV_CONF
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#define BP_SFC_DEV_CONF_SMP_DELAY 16
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#define BM_SFC_DEV_CONF_SMP_DELAY 0x30000
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#define BF_SFC_DEV_CONF_SMP_DELAY(v) (((v) & 0x3) << 16)
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#define BFM_SFC_DEV_CONF_SMP_DELAY(v) BM_SFC_DEV_CONF_SMP_DELAY
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#define BF_SFC_DEV_CONF_SMP_DELAY_V(e) BF_SFC_DEV_CONF_SMP_DELAY(BV_SFC_DEV_CONF_SMP_DELAY__##e)
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#define BFM_SFC_DEV_CONF_SMP_DELAY_V(v) BM_SFC_DEV_CONF_SMP_DELAY
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#define BP_SFC_DEV_CONF_STA_TYPE 13
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#define BM_SFC_DEV_CONF_STA_TYPE 0x6000
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#define BV_SFC_DEV_CONF_STA_TYPE__1BYTE 0x0
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#define BV_SFC_DEV_CONF_STA_TYPE__2BYTE 0x1
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#define BV_SFC_DEV_CONF_STA_TYPE__3BYTE 0x2
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#define BV_SFC_DEV_CONF_STA_TYPE__4BYTE 0x3
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#define BF_SFC_DEV_CONF_STA_TYPE(v) (((v) & 0x3) << 13)
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#define BFM_SFC_DEV_CONF_STA_TYPE(v) BM_SFC_DEV_CONF_STA_TYPE
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#define BF_SFC_DEV_CONF_STA_TYPE_V(e) BF_SFC_DEV_CONF_STA_TYPE(BV_SFC_DEV_CONF_STA_TYPE__##e)
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#define BFM_SFC_DEV_CONF_STA_TYPE_V(v) BM_SFC_DEV_CONF_STA_TYPE
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#define BP_SFC_DEV_CONF_THOLD 11
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#define BM_SFC_DEV_CONF_THOLD 0x1800
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#define BF_SFC_DEV_CONF_THOLD(v) (((v) & 0x3) << 11)
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#define BFM_SFC_DEV_CONF_THOLD(v) BM_SFC_DEV_CONF_THOLD
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#define BF_SFC_DEV_CONF_THOLD_V(e) BF_SFC_DEV_CONF_THOLD(BV_SFC_DEV_CONF_THOLD__##e)
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#define BFM_SFC_DEV_CONF_THOLD_V(v) BM_SFC_DEV_CONF_THOLD
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#define BP_SFC_DEV_CONF_TSETUP 9
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#define BM_SFC_DEV_CONF_TSETUP 0x600
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#define BF_SFC_DEV_CONF_TSETUP(v) (((v) & 0x3) << 9)
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#define BFM_SFC_DEV_CONF_TSETUP(v) BM_SFC_DEV_CONF_TSETUP
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#define BF_SFC_DEV_CONF_TSETUP_V(e) BF_SFC_DEV_CONF_TSETUP(BV_SFC_DEV_CONF_TSETUP__##e)
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#define BFM_SFC_DEV_CONF_TSETUP_V(v) BM_SFC_DEV_CONF_TSETUP
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#define BP_SFC_DEV_CONF_TSH 5
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#define BM_SFC_DEV_CONF_TSH 0x1e0
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#define BF_SFC_DEV_CONF_TSH(v) (((v) & 0xf) << 5)
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#define BFM_SFC_DEV_CONF_TSH(v) BM_SFC_DEV_CONF_TSH
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#define BF_SFC_DEV_CONF_TSH_V(e) BF_SFC_DEV_CONF_TSH(BV_SFC_DEV_CONF_TSH__##e)
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#define BFM_SFC_DEV_CONF_TSH_V(v) BM_SFC_DEV_CONF_TSH
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#define BP_SFC_DEV_CONF_CMD_TYPE 15
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#define BM_SFC_DEV_CONF_CMD_TYPE 0x8000
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#define BV_SFC_DEV_CONF_CMD_TYPE__8BITS 0x0
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#define BV_SFC_DEV_CONF_CMD_TYPE__16BITS 0x1
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#define BF_SFC_DEV_CONF_CMD_TYPE(v) (((v) & 0x1) << 15)
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#define BFM_SFC_DEV_CONF_CMD_TYPE(v) BM_SFC_DEV_CONF_CMD_TYPE
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#define BF_SFC_DEV_CONF_CMD_TYPE_V(e) BF_SFC_DEV_CONF_CMD_TYPE(BV_SFC_DEV_CONF_CMD_TYPE__##e)
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#define BFM_SFC_DEV_CONF_CMD_TYPE_V(v) BM_SFC_DEV_CONF_CMD_TYPE
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#define BP_SFC_DEV_CONF_CPHA 4
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#define BM_SFC_DEV_CONF_CPHA 0x10
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#define BF_SFC_DEV_CONF_CPHA(v) (((v) & 0x1) << 4)
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#define BFM_SFC_DEV_CONF_CPHA(v) BM_SFC_DEV_CONF_CPHA
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#define BF_SFC_DEV_CONF_CPHA_V(e) BF_SFC_DEV_CONF_CPHA(BV_SFC_DEV_CONF_CPHA__##e)
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#define BFM_SFC_DEV_CONF_CPHA_V(v) BM_SFC_DEV_CONF_CPHA
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#define BP_SFC_DEV_CONF_CPOL 3
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#define BM_SFC_DEV_CONF_CPOL 0x8
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#define BF_SFC_DEV_CONF_CPOL(v) (((v) & 0x1) << 3)
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#define BFM_SFC_DEV_CONF_CPOL(v) BM_SFC_DEV_CONF_CPOL
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#define BF_SFC_DEV_CONF_CPOL_V(e) BF_SFC_DEV_CONF_CPOL(BV_SFC_DEV_CONF_CPOL__##e)
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#define BFM_SFC_DEV_CONF_CPOL_V(v) BM_SFC_DEV_CONF_CPOL
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#define BP_SFC_DEV_CONF_CE_DL 2
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#define BM_SFC_DEV_CONF_CE_DL 0x4
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#define BF_SFC_DEV_CONF_CE_DL(v) (((v) & 0x1) << 2)
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#define BFM_SFC_DEV_CONF_CE_DL(v) BM_SFC_DEV_CONF_CE_DL
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#define BF_SFC_DEV_CONF_CE_DL_V(e) BF_SFC_DEV_CONF_CE_DL(BV_SFC_DEV_CONF_CE_DL__##e)
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#define BFM_SFC_DEV_CONF_CE_DL_V(v) BM_SFC_DEV_CONF_CE_DL
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#define BP_SFC_DEV_CONF_HOLD_DL 1
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#define BM_SFC_DEV_CONF_HOLD_DL 0x2
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#define BF_SFC_DEV_CONF_HOLD_DL(v) (((v) & 0x1) << 1)
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#define BFM_SFC_DEV_CONF_HOLD_DL(v) BM_SFC_DEV_CONF_HOLD_DL
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#define BF_SFC_DEV_CONF_HOLD_DL_V(e) BF_SFC_DEV_CONF_HOLD_DL(BV_SFC_DEV_CONF_HOLD_DL__##e)
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#define BFM_SFC_DEV_CONF_HOLD_DL_V(v) BM_SFC_DEV_CONF_HOLD_DL
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#define BP_SFC_DEV_CONF_WP_DL 0
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#define BM_SFC_DEV_CONF_WP_DL 0x1
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#define BF_SFC_DEV_CONF_WP_DL(v) (((v) & 0x1) << 0)
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#define BFM_SFC_DEV_CONF_WP_DL(v) BM_SFC_DEV_CONF_WP_DL
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#define BF_SFC_DEV_CONF_WP_DL_V(e) BF_SFC_DEV_CONF_WP_DL(BV_SFC_DEV_CONF_WP_DL__##e)
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#define BFM_SFC_DEV_CONF_WP_DL_V(v) BM_SFC_DEV_CONF_WP_DL
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#define REG_SFC_DEV_STA_EXP jz_reg(SFC_DEV_STA_EXP)
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#define JA_SFC_DEV_STA_EXP (0xb3440000 + 0x8)
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#define JT_SFC_DEV_STA_EXP JIO_32_RW
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#define JN_SFC_DEV_STA_EXP SFC_DEV_STA_EXP
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#define JI_SFC_DEV_STA_EXP
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#define REG_SFC_DEV_STA_RT jz_reg(SFC_DEV_STA_RT)
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#define JA_SFC_DEV_STA_RT (0xb3440000 + 0xc)
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#define JT_SFC_DEV_STA_RT JIO_32_RW
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#define JN_SFC_DEV_STA_RT SFC_DEV_STA_RT
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#define JI_SFC_DEV_STA_RT
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#define REG_SFC_DEV_STA_MSK jz_reg(SFC_DEV_STA_MSK)
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#define JA_SFC_DEV_STA_MSK (0xb3440000 + 0x10)
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#define JT_SFC_DEV_STA_MSK JIO_32_RW
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#define JN_SFC_DEV_STA_MSK SFC_DEV_STA_MSK
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#define JI_SFC_DEV_STA_MSK
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#define REG_SFC_TRAN_CONF(_n1) jz_reg(SFC_TRAN_CONF(_n1))
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#define JA_SFC_TRAN_CONF(_n1) (0xb3440000 + 0x14 + (_n1) * 0x4)
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#define JT_SFC_TRAN_CONF(_n1) JIO_32_RW
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#define JN_SFC_TRAN_CONF(_n1) SFC_TRAN_CONF
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#define JI_SFC_TRAN_CONF(_n1) (_n1)
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#define BP_SFC_TRAN_CONF_MODE 29
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#define BM_SFC_TRAN_CONF_MODE 0xe0000000
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#define BF_SFC_TRAN_CONF_MODE(v) (((v) & 0x7) << 29)
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#define BFM_SFC_TRAN_CONF_MODE(v) BM_SFC_TRAN_CONF_MODE
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#define BF_SFC_TRAN_CONF_MODE_V(e) BF_SFC_TRAN_CONF_MODE(BV_SFC_TRAN_CONF_MODE__##e)
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#define BFM_SFC_TRAN_CONF_MODE_V(v) BM_SFC_TRAN_CONF_MODE
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#define BP_SFC_TRAN_CONF_ADDR_WIDTH 26
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#define BM_SFC_TRAN_CONF_ADDR_WIDTH 0x1c000000
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#define BF_SFC_TRAN_CONF_ADDR_WIDTH(v) (((v) & 0x7) << 26)
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#define BFM_SFC_TRAN_CONF_ADDR_WIDTH(v) BM_SFC_TRAN_CONF_ADDR_WIDTH
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#define BF_SFC_TRAN_CONF_ADDR_WIDTH_V(e) BF_SFC_TRAN_CONF_ADDR_WIDTH(BV_SFC_TRAN_CONF_ADDR_WIDTH__##e)
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#define BFM_SFC_TRAN_CONF_ADDR_WIDTH_V(v) BM_SFC_TRAN_CONF_ADDR_WIDTH
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#define BP_SFC_TRAN_CONF_DUMMY_BITS 17
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#define BM_SFC_TRAN_CONF_DUMMY_BITS 0x7e0000
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#define BF_SFC_TRAN_CONF_DUMMY_BITS(v) (((v) & 0x3f) << 17)
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#define BFM_SFC_TRAN_CONF_DUMMY_BITS(v) BM_SFC_TRAN_CONF_DUMMY_BITS
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#define BF_SFC_TRAN_CONF_DUMMY_BITS_V(e) BF_SFC_TRAN_CONF_DUMMY_BITS(BV_SFC_TRAN_CONF_DUMMY_BITS__##e)
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#define BFM_SFC_TRAN_CONF_DUMMY_BITS_V(v) BM_SFC_TRAN_CONF_DUMMY_BITS
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#define BP_SFC_TRAN_CONF_COMMAND 0
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#define BM_SFC_TRAN_CONF_COMMAND 0xffff
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#define BF_SFC_TRAN_CONF_COMMAND(v) (((v) & 0xffff) << 0)
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#define BFM_SFC_TRAN_CONF_COMMAND(v) BM_SFC_TRAN_CONF_COMMAND
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#define BF_SFC_TRAN_CONF_COMMAND_V(e) BF_SFC_TRAN_CONF_COMMAND(BV_SFC_TRAN_CONF_COMMAND__##e)
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#define BFM_SFC_TRAN_CONF_COMMAND_V(v) BM_SFC_TRAN_CONF_COMMAND
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#define BP_SFC_TRAN_CONF_POLL_EN 25
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#define BM_SFC_TRAN_CONF_POLL_EN 0x2000000
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#define BF_SFC_TRAN_CONF_POLL_EN(v) (((v) & 0x1) << 25)
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#define BFM_SFC_TRAN_CONF_POLL_EN(v) BM_SFC_TRAN_CONF_POLL_EN
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#define BF_SFC_TRAN_CONF_POLL_EN_V(e) BF_SFC_TRAN_CONF_POLL_EN(BV_SFC_TRAN_CONF_POLL_EN__##e)
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#define BFM_SFC_TRAN_CONF_POLL_EN_V(v) BM_SFC_TRAN_CONF_POLL_EN
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#define BP_SFC_TRAN_CONF_CMD_EN 24
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#define BM_SFC_TRAN_CONF_CMD_EN 0x1000000
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#define BF_SFC_TRAN_CONF_CMD_EN(v) (((v) & 0x1) << 24)
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#define BFM_SFC_TRAN_CONF_CMD_EN(v) BM_SFC_TRAN_CONF_CMD_EN
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#define BF_SFC_TRAN_CONF_CMD_EN_V(e) BF_SFC_TRAN_CONF_CMD_EN(BV_SFC_TRAN_CONF_CMD_EN__##e)
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#define BFM_SFC_TRAN_CONF_CMD_EN_V(v) BM_SFC_TRAN_CONF_CMD_EN
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#define BP_SFC_TRAN_CONF_PHASE_FMT 23
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#define BM_SFC_TRAN_CONF_PHASE_FMT 0x800000
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#define BF_SFC_TRAN_CONF_PHASE_FMT(v) (((v) & 0x1) << 23)
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#define BFM_SFC_TRAN_CONF_PHASE_FMT(v) BM_SFC_TRAN_CONF_PHASE_FMT
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#define BF_SFC_TRAN_CONF_PHASE_FMT_V(e) BF_SFC_TRAN_CONF_PHASE_FMT(BV_SFC_TRAN_CONF_PHASE_FMT__##e)
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#define BFM_SFC_TRAN_CONF_PHASE_FMT_V(v) BM_SFC_TRAN_CONF_PHASE_FMT
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#define BP_SFC_TRAN_CONF_DATA_EN 16
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#define BM_SFC_TRAN_CONF_DATA_EN 0x10000
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#define BF_SFC_TRAN_CONF_DATA_EN(v) (((v) & 0x1) << 16)
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#define BFM_SFC_TRAN_CONF_DATA_EN(v) BM_SFC_TRAN_CONF_DATA_EN
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#define BF_SFC_TRAN_CONF_DATA_EN_V(e) BF_SFC_TRAN_CONF_DATA_EN(BV_SFC_TRAN_CONF_DATA_EN__##e)
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#define BFM_SFC_TRAN_CONF_DATA_EN_V(v) BM_SFC_TRAN_CONF_DATA_EN
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#define REG_SFC_TRAN_LENGTH jz_reg(SFC_TRAN_LENGTH)
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#define JA_SFC_TRAN_LENGTH (0xb3440000 + 0x2c)
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#define JT_SFC_TRAN_LENGTH JIO_32_RW
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#define JN_SFC_TRAN_LENGTH SFC_TRAN_LENGTH
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#define JI_SFC_TRAN_LENGTH
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#define REG_SFC_DEV_ADDR(_n1) jz_reg(SFC_DEV_ADDR(_n1))
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#define JA_SFC_DEV_ADDR(_n1) (0xb3440000 + 0x30 + (_n1) * 0x4)
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#define JT_SFC_DEV_ADDR(_n1) JIO_32_RW
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#define JN_SFC_DEV_ADDR(_n1) SFC_DEV_ADDR
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#define JI_SFC_DEV_ADDR(_n1) (_n1)
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#define REG_SFC_DEV_PLUS(_n1) jz_reg(SFC_DEV_PLUS(_n1))
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#define JA_SFC_DEV_PLUS(_n1) (0xb3440000 + 0x48 + (_n1) * 0x40)
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#define JT_SFC_DEV_PLUS(_n1) JIO_32_RW
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#define JN_SFC_DEV_PLUS(_n1) SFC_DEV_PLUS
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#define JI_SFC_DEV_PLUS(_n1) (_n1)
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#define REG_SFC_MEM_ADDR jz_reg(SFC_MEM_ADDR)
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#define JA_SFC_MEM_ADDR (0xb3440000 + 0x60)
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#define JT_SFC_MEM_ADDR JIO_32_RW
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#define JN_SFC_MEM_ADDR SFC_MEM_ADDR
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#define JI_SFC_MEM_ADDR
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#define REG_SFC_TRIG jz_reg(SFC_TRIG)
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#define JA_SFC_TRIG (0xb3440000 + 0x64)
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#define JT_SFC_TRIG JIO_32_RW
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#define JN_SFC_TRIG SFC_TRIG
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#define JI_SFC_TRIG
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#define BP_SFC_TRIG_FLUSH 2
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#define BM_SFC_TRIG_FLUSH 0x4
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#define BF_SFC_TRIG_FLUSH(v) (((v) & 0x1) << 2)
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#define BFM_SFC_TRIG_FLUSH(v) BM_SFC_TRIG_FLUSH
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#define BF_SFC_TRIG_FLUSH_V(e) BF_SFC_TRIG_FLUSH(BV_SFC_TRIG_FLUSH__##e)
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#define BFM_SFC_TRIG_FLUSH_V(v) BM_SFC_TRIG_FLUSH
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#define BP_SFC_TRIG_STOP 1
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#define BM_SFC_TRIG_STOP 0x2
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#define BF_SFC_TRIG_STOP(v) (((v) & 0x1) << 1)
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#define BFM_SFC_TRIG_STOP(v) BM_SFC_TRIG_STOP
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#define BF_SFC_TRIG_STOP_V(e) BF_SFC_TRIG_STOP(BV_SFC_TRIG_STOP__##e)
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#define BFM_SFC_TRIG_STOP_V(v) BM_SFC_TRIG_STOP
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#define BP_SFC_TRIG_START 0
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#define BM_SFC_TRIG_START 0x1
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#define BF_SFC_TRIG_START(v) (((v) & 0x1) << 0)
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#define BFM_SFC_TRIG_START(v) BM_SFC_TRIG_START
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#define BF_SFC_TRIG_START_V(e) BF_SFC_TRIG_START(BV_SFC_TRIG_START__##e)
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#define BFM_SFC_TRIG_START_V(v) BM_SFC_TRIG_START
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#define REG_SFC_SR jz_reg(SFC_SR)
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#define JA_SFC_SR (0xb3440000 + 0x68)
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#define JT_SFC_SR JIO_32_RW
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#define JN_SFC_SR SFC_SR
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#define JI_SFC_SR
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#define BP_SFC_SR_FIFO_NUM 16
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#define BM_SFC_SR_FIFO_NUM 0x7f0000
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#define BF_SFC_SR_FIFO_NUM(v) (((v) & 0x7f) << 16)
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#define BFM_SFC_SR_FIFO_NUM(v) BM_SFC_SR_FIFO_NUM
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#define BF_SFC_SR_FIFO_NUM_V(e) BF_SFC_SR_FIFO_NUM(BV_SFC_SR_FIFO_NUM__##e)
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#define BFM_SFC_SR_FIFO_NUM_V(v) BM_SFC_SR_FIFO_NUM
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#define BP_SFC_SR_BUSY 5
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#define BM_SFC_SR_BUSY 0x60
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#define BF_SFC_SR_BUSY(v) (((v) & 0x3) << 5)
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#define BFM_SFC_SR_BUSY(v) BM_SFC_SR_BUSY
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#define BF_SFC_SR_BUSY_V(e) BF_SFC_SR_BUSY(BV_SFC_SR_BUSY__##e)
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#define BFM_SFC_SR_BUSY_V(v) BM_SFC_SR_BUSY
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#define BP_SFC_SR_END 4
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#define BM_SFC_SR_END 0x10
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#define BF_SFC_SR_END(v) (((v) & 0x1) << 4)
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#define BFM_SFC_SR_END(v) BM_SFC_SR_END
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#define BF_SFC_SR_END_V(e) BF_SFC_SR_END(BV_SFC_SR_END__##e)
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#define BFM_SFC_SR_END_V(v) BM_SFC_SR_END
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#define BP_SFC_SR_TREQ 3
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#define BM_SFC_SR_TREQ 0x8
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#define BF_SFC_SR_TREQ(v) (((v) & 0x1) << 3)
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#define BFM_SFC_SR_TREQ(v) BM_SFC_SR_TREQ
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#define BF_SFC_SR_TREQ_V(e) BF_SFC_SR_TREQ(BV_SFC_SR_TREQ__##e)
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#define BFM_SFC_SR_TREQ_V(v) BM_SFC_SR_TREQ
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#define BP_SFC_SR_RREQ 2
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#define BM_SFC_SR_RREQ 0x4
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#define BF_SFC_SR_RREQ(v) (((v) & 0x1) << 2)
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#define BFM_SFC_SR_RREQ(v) BM_SFC_SR_RREQ
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#define BF_SFC_SR_RREQ_V(e) BF_SFC_SR_RREQ(BV_SFC_SR_RREQ__##e)
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#define BFM_SFC_SR_RREQ_V(v) BM_SFC_SR_RREQ
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#define BP_SFC_SR_OVER 1
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#define BM_SFC_SR_OVER 0x2
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#define BF_SFC_SR_OVER(v) (((v) & 0x1) << 1)
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#define BFM_SFC_SR_OVER(v) BM_SFC_SR_OVER
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#define BF_SFC_SR_OVER_V(e) BF_SFC_SR_OVER(BV_SFC_SR_OVER__##e)
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#define BFM_SFC_SR_OVER_V(v) BM_SFC_SR_OVER
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#define BP_SFC_SR_UNDER 0
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#define BM_SFC_SR_UNDER 0x1
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#define BF_SFC_SR_UNDER(v) (((v) & 0x1) << 0)
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#define BFM_SFC_SR_UNDER(v) BM_SFC_SR_UNDER
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#define BF_SFC_SR_UNDER_V(e) BF_SFC_SR_UNDER(BV_SFC_SR_UNDER__##e)
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#define BFM_SFC_SR_UNDER_V(v) BM_SFC_SR_UNDER
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#define REG_SFC_SCR jz_reg(SFC_SCR)
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#define JA_SFC_SCR (0xb3440000 + 0x6c)
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#define JT_SFC_SCR JIO_32_RW
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#define JN_SFC_SCR SFC_SCR
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#define JI_SFC_SCR
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#define BP_SFC_SCR_CLR_END 4
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#define BM_SFC_SCR_CLR_END 0x10
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#define BF_SFC_SCR_CLR_END(v) (((v) & 0x1) << 4)
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#define BFM_SFC_SCR_CLR_END(v) BM_SFC_SCR_CLR_END
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#define BF_SFC_SCR_CLR_END_V(e) BF_SFC_SCR_CLR_END(BV_SFC_SCR_CLR_END__##e)
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#define BFM_SFC_SCR_CLR_END_V(v) BM_SFC_SCR_CLR_END
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#define BP_SFC_SCR_CLR_TREQ 3
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#define BM_SFC_SCR_CLR_TREQ 0x8
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#define BF_SFC_SCR_CLR_TREQ(v) (((v) & 0x1) << 3)
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#define BFM_SFC_SCR_CLR_TREQ(v) BM_SFC_SCR_CLR_TREQ
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#define BF_SFC_SCR_CLR_TREQ_V(e) BF_SFC_SCR_CLR_TREQ(BV_SFC_SCR_CLR_TREQ__##e)
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#define BFM_SFC_SCR_CLR_TREQ_V(v) BM_SFC_SCR_CLR_TREQ
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#define BP_SFC_SCR_CLR_RREQ 2
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#define BM_SFC_SCR_CLR_RREQ 0x4
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#define BF_SFC_SCR_CLR_RREQ(v) (((v) & 0x1) << 2)
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#define BFM_SFC_SCR_CLR_RREQ(v) BM_SFC_SCR_CLR_RREQ
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#define BF_SFC_SCR_CLR_RREQ_V(e) BF_SFC_SCR_CLR_RREQ(BV_SFC_SCR_CLR_RREQ__##e)
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#define BFM_SFC_SCR_CLR_RREQ_V(v) BM_SFC_SCR_CLR_RREQ
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#define BP_SFC_SCR_CLR_OVER 1
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#define BM_SFC_SCR_CLR_OVER 0x2
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#define BF_SFC_SCR_CLR_OVER(v) (((v) & 0x1) << 1)
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#define BFM_SFC_SCR_CLR_OVER(v) BM_SFC_SCR_CLR_OVER
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#define BF_SFC_SCR_CLR_OVER_V(e) BF_SFC_SCR_CLR_OVER(BV_SFC_SCR_CLR_OVER__##e)
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#define BFM_SFC_SCR_CLR_OVER_V(v) BM_SFC_SCR_CLR_OVER
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#define BP_SFC_SCR_CLR_UNDER 0
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#define BM_SFC_SCR_CLR_UNDER 0x1
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#define BF_SFC_SCR_CLR_UNDER(v) (((v) & 0x1) << 0)
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#define BFM_SFC_SCR_CLR_UNDER(v) BM_SFC_SCR_CLR_UNDER
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#define BF_SFC_SCR_CLR_UNDER_V(e) BF_SFC_SCR_CLR_UNDER(BV_SFC_SCR_CLR_UNDER__##e)
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#define BFM_SFC_SCR_CLR_UNDER_V(v) BM_SFC_SCR_CLR_UNDER
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#define REG_SFC_INTC jz_reg(SFC_INTC)
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#define JA_SFC_INTC (0xb3440000 + 0x70)
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#define JT_SFC_INTC JIO_32_RW
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#define JN_SFC_INTC SFC_INTC
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#define JI_SFC_INTC
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#define BP_SFC_INTC_MSK_END 4
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#define BM_SFC_INTC_MSK_END 0x10
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#define BF_SFC_INTC_MSK_END(v) (((v) & 0x1) << 4)
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#define BFM_SFC_INTC_MSK_END(v) BM_SFC_INTC_MSK_END
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#define BF_SFC_INTC_MSK_END_V(e) BF_SFC_INTC_MSK_END(BV_SFC_INTC_MSK_END__##e)
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#define BFM_SFC_INTC_MSK_END_V(v) BM_SFC_INTC_MSK_END
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#define BP_SFC_INTC_MSK_TREQ 3
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#define BM_SFC_INTC_MSK_TREQ 0x8
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#define BF_SFC_INTC_MSK_TREQ(v) (((v) & 0x1) << 3)
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#define BFM_SFC_INTC_MSK_TREQ(v) BM_SFC_INTC_MSK_TREQ
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#define BF_SFC_INTC_MSK_TREQ_V(e) BF_SFC_INTC_MSK_TREQ(BV_SFC_INTC_MSK_TREQ__##e)
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#define BFM_SFC_INTC_MSK_TREQ_V(v) BM_SFC_INTC_MSK_TREQ
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#define BP_SFC_INTC_MSK_RREQ 2
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#define BM_SFC_INTC_MSK_RREQ 0x4
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#define BF_SFC_INTC_MSK_RREQ(v) (((v) & 0x1) << 2)
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#define BFM_SFC_INTC_MSK_RREQ(v) BM_SFC_INTC_MSK_RREQ
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#define BF_SFC_INTC_MSK_RREQ_V(e) BF_SFC_INTC_MSK_RREQ(BV_SFC_INTC_MSK_RREQ__##e)
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#define BFM_SFC_INTC_MSK_RREQ_V(v) BM_SFC_INTC_MSK_RREQ
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#define BP_SFC_INTC_MSK_OVER 1
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#define BM_SFC_INTC_MSK_OVER 0x2
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#define BF_SFC_INTC_MSK_OVER(v) (((v) & 0x1) << 1)
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#define BFM_SFC_INTC_MSK_OVER(v) BM_SFC_INTC_MSK_OVER
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#define BF_SFC_INTC_MSK_OVER_V(e) BF_SFC_INTC_MSK_OVER(BV_SFC_INTC_MSK_OVER__##e)
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#define BFM_SFC_INTC_MSK_OVER_V(v) BM_SFC_INTC_MSK_OVER
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#define BP_SFC_INTC_MSK_UNDER 0
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#define BM_SFC_INTC_MSK_UNDER 0x1
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#define BF_SFC_INTC_MSK_UNDER(v) (((v) & 0x1) << 0)
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#define BFM_SFC_INTC_MSK_UNDER(v) BM_SFC_INTC_MSK_UNDER
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#define BF_SFC_INTC_MSK_UNDER_V(e) BF_SFC_INTC_MSK_UNDER(BV_SFC_INTC_MSK_UNDER__##e)
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#define BFM_SFC_INTC_MSK_UNDER_V(v) BM_SFC_INTC_MSK_UNDER
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#define REG_SFC_FSM jz_reg(SFC_FSM)
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#define JA_SFC_FSM (0xb3440000 + 0x74)
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#define JT_SFC_FSM JIO_32_RW
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#define JN_SFC_FSM SFC_FSM
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#define JI_SFC_FSM
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#define BP_SFC_FSM_STATE_AHB 16
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#define BM_SFC_FSM_STATE_AHB 0xf0000
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#define BF_SFC_FSM_STATE_AHB(v) (((v) & 0xf) << 16)
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#define BFM_SFC_FSM_STATE_AHB(v) BM_SFC_FSM_STATE_AHB
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#define BF_SFC_FSM_STATE_AHB_V(e) BF_SFC_FSM_STATE_AHB(BV_SFC_FSM_STATE_AHB__##e)
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#define BFM_SFC_FSM_STATE_AHB_V(v) BM_SFC_FSM_STATE_AHB
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#define BP_SFC_FSM_STATE_SPI 11
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#define BM_SFC_FSM_STATE_SPI 0xf800
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#define BF_SFC_FSM_STATE_SPI(v) (((v) & 0x1f) << 11)
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#define BFM_SFC_FSM_STATE_SPI(v) BM_SFC_FSM_STATE_SPI
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#define BF_SFC_FSM_STATE_SPI_V(e) BF_SFC_FSM_STATE_SPI(BV_SFC_FSM_STATE_SPI__##e)
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#define BFM_SFC_FSM_STATE_SPI_V(v) BM_SFC_FSM_STATE_SPI
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#define BP_SFC_FSM_STATE_CLK 6
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#define BM_SFC_FSM_STATE_CLK 0x3c0
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#define BF_SFC_FSM_STATE_CLK(v) (((v) & 0xf) << 6)
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#define BFM_SFC_FSM_STATE_CLK(v) BM_SFC_FSM_STATE_CLK
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#define BF_SFC_FSM_STATE_CLK_V(e) BF_SFC_FSM_STATE_CLK(BV_SFC_FSM_STATE_CLK__##e)
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#define BFM_SFC_FSM_STATE_CLK_V(v) BM_SFC_FSM_STATE_CLK
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#define BP_SFC_FSM_STATE_DMAC 3
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#define BM_SFC_FSM_STATE_DMAC 0x38
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#define BF_SFC_FSM_STATE_DMAC(v) (((v) & 0x7) << 3)
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#define BFM_SFC_FSM_STATE_DMAC(v) BM_SFC_FSM_STATE_DMAC
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#define BF_SFC_FSM_STATE_DMAC_V(e) BF_SFC_FSM_STATE_DMAC(BV_SFC_FSM_STATE_DMAC__##e)
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#define BFM_SFC_FSM_STATE_DMAC_V(v) BM_SFC_FSM_STATE_DMAC
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#define BP_SFC_FSM_STATE_RMC 0
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#define BM_SFC_FSM_STATE_RMC 0x7
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#define BF_SFC_FSM_STATE_RMC(v) (((v) & 0x7) << 0)
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#define BFM_SFC_FSM_STATE_RMC(v) BM_SFC_FSM_STATE_RMC
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#define BF_SFC_FSM_STATE_RMC_V(e) BF_SFC_FSM_STATE_RMC(BV_SFC_FSM_STATE_RMC__##e)
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#define BFM_SFC_FSM_STATE_RMC_V(v) BM_SFC_FSM_STATE_RMC
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#define REG_SFC_CGE jz_reg(SFC_CGE)
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#define JA_SFC_CGE (0xb3440000 + 0x78)
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#define JT_SFC_CGE JIO_32_RW
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#define JN_SFC_CGE SFC_CGE
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#define JI_SFC_CGE
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#define BP_SFC_CGE_SFC 5
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#define BM_SFC_CGE_SFC 0x20
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#define BF_SFC_CGE_SFC(v) (((v) & 0x1) << 5)
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#define BFM_SFC_CGE_SFC(v) BM_SFC_CGE_SFC
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#define BF_SFC_CGE_SFC_V(e) BF_SFC_CGE_SFC(BV_SFC_CGE_SFC__##e)
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#define BFM_SFC_CGE_SFC_V(v) BM_SFC_CGE_SFC
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#define BP_SFC_CGE_FIFO 4
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#define BM_SFC_CGE_FIFO 0x10
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#define BF_SFC_CGE_FIFO(v) (((v) & 0x1) << 4)
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#define BFM_SFC_CGE_FIFO(v) BM_SFC_CGE_FIFO
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#define BF_SFC_CGE_FIFO_V(e) BF_SFC_CGE_FIFO(BV_SFC_CGE_FIFO__##e)
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#define BFM_SFC_CGE_FIFO_V(v) BM_SFC_CGE_FIFO
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#define BP_SFC_CGE_DMA 3
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#define BM_SFC_CGE_DMA 0x8
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#define BF_SFC_CGE_DMA(v) (((v) & 0x1) << 3)
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#define BFM_SFC_CGE_DMA(v) BM_SFC_CGE_DMA
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#define BF_SFC_CGE_DMA_V(e) BF_SFC_CGE_DMA(BV_SFC_CGE_DMA__##e)
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#define BFM_SFC_CGE_DMA_V(v) BM_SFC_CGE_DMA
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#define BP_SFC_CGE_RMC 2
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#define BM_SFC_CGE_RMC 0x4
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#define BF_SFC_CGE_RMC(v) (((v) & 0x1) << 2)
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#define BFM_SFC_CGE_RMC(v) BM_SFC_CGE_RMC
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#define BF_SFC_CGE_RMC_V(e) BF_SFC_CGE_RMC(BV_SFC_CGE_RMC__##e)
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#define BFM_SFC_CGE_RMC_V(v) BM_SFC_CGE_RMC
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#define BP_SFC_CGE_SPI 1
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#define BM_SFC_CGE_SPI 0x2
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#define BF_SFC_CGE_SPI(v) (((v) & 0x1) << 1)
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#define BFM_SFC_CGE_SPI(v) BM_SFC_CGE_SPI
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#define BF_SFC_CGE_SPI_V(e) BF_SFC_CGE_SPI(BV_SFC_CGE_SPI__##e)
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#define BFM_SFC_CGE_SPI_V(v) BM_SFC_CGE_SPI
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#define BP_SFC_CGE_REG 0
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#define BM_SFC_CGE_REG 0x1
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#define BF_SFC_CGE_REG(v) (((v) & 0x1) << 0)
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#define BFM_SFC_CGE_REG(v) BM_SFC_CGE_REG
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#define BF_SFC_CGE_REG_V(e) BF_SFC_CGE_REG(BV_SFC_CGE_REG__##e)
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#define BFM_SFC_CGE_REG_V(v) BM_SFC_CGE_REG
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#define REG_SFC_DATA jz_reg(SFC_DATA)
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#define JA_SFC_DATA (0xb3440000 + 0x1000)
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#define JT_SFC_DATA JIO_32_RW
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#define JN_SFC_DATA SFC_DATA
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#define JI_SFC_DATA
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#endif /* __HEADERGEN_SFC_H__*/
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