f7f1f7023f
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31424 a1c6a512-1295-4272-9138-f99709370657
95 lines
3.5 KiB
C
95 lines
3.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __IMX233_H__
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#define __IMX233_H__
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/*
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* Chip Memory Map:
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* 0x00000000 - 0x00007fff: on chip ram
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* 0x40000000 - 0x5fffffff: dram (512Mb max)
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* 0x80000000 - 0x80100000: memory mapped registers
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* We use the following map:
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* 0x60000000 - 0x7fffffff: dram (cached)
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* 0x90000000 - 0xafffffff: dram (buffered)
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* everything else : identity mapped (uncached)
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*
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* As a side note it's important to notice that uncached dram is identity mapped
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*/
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#define IRAM_ORIG 0
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#define IRAM_SIZE 0x8000
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#define DRAM_ORIG 0x40000000
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#define DRAM_SIZE (MEMORYSIZE * 0x100000)
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#define UNCACHED_DRAM_ADDR 0x40000000
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#define CACHED_DRAM_ADDR 0x60000000
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#define BUFFERED_DRAM_ADDR 0x90000000
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#define CACHEALIGN_SIZE 32
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#define NOCACHE_BASE (UNCACHED_DRAM_ADDR - CACHED_DRAM_ADDR)
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#define PHYSICAL_ADDR(a) \
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((typeof(a))((uintptr_t)(a) >= CACHED_DRAM_ADDR ? \
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((uintptr_t)(a) - CACHED_DRAM_ADDR + UNCACHED_DRAM_ADDR) \
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:(uintptr_t)(a)))
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#define UNCACHED_ADDR(a) PHYSICAL_ADDR(a)
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#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
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#define TTB_SIZE 0x4000
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#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
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#define FRAME_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_DEPTH / 8)
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#define FRAME_PHYS_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE - FRAME_SIZE)
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#define FRAME ((void *)(FRAME_PHYS_ADDR - UNCACHED_DRAM_ADDR + BUFFERED_DRAM_ADDR))
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/* Timer runs at APBX speed which is derived from ref_xtal@24MHz */
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#define TIMER_FREQ 24000000
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#ifdef SANSA_FUZEPLUS
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#define TICK_TIMER_NR 0
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#define USER_TIMER_NR 1
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#else
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#error Select timers !
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#endif
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/* USBOTG */
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#define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048)))
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#define USB_NUM_ENDPOINTS 5
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#define USB_DEVBSS_ATTR NOCACHEBSS_ATTR
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#define USB_BASE 0x80080000
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/*
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#define QHARRAY_SIZE ((64*USB_NUM_ENDPOINTS*2 + 2047) & (0xffffffff - 2047))
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#define QHARRAY_PHYS_ADDR ((FRAME_PHYS_ADDR - QHARRAY_SIZE) & (0xffffffff - 2047))
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*/
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#define __REG_SET(reg) (*((volatile uint32_t *)(® + 1)))
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#define __REG_CLR(reg) (*((volatile uint32_t *)(® + 2)))
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#define __REG_TOG(reg) (*((volatile uint32_t *)(® + 3)))
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#define __BLOCK_SFTRST (1 << 31)
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#define __BLOCK_CLKGATE (1 << 30)
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#define CACHEALIGN_BITS 4
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#define __XTRACT(reg, field) ((reg & reg##__##field##_BM) >> reg##__##field##_BP)
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#define __XTRACT_EX(val, field) (((val) & field##_BM) >> field##_BP)
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#define __FIELD_SET(reg, field, val) reg = (reg & ~reg##__##field##_BM) | (val << reg##__##field##_BP)
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#endif /* __IMX233_H__ */
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