rockbox/firmware/target/arm/imx31
2011-01-05 19:35:51 +00:00
..
gigabeat-s Gigabeat S: Make it a removable mass-storage device. Windows will assign a drive to only the main data partition by default. To access the bootloader partition instead, press 'Vol -' while it connects (in bootloader and firmware). Hopefully doesn't break anything for anyone. 2011-01-05 19:35:51 +00:00
app.lds */app.lds: remove STUBOFFSET 2010-09-20 17:09:55 +00:00
ata-imx31.c Gigabeat S: Use statically initialized channel descriptors. Also, there's no need for them to be in non-cached memory since they're only used on the AP side. 2010-06-24 08:40:05 +00:00
ata-target.h Rework ATA driver to get rid of lots of target-specific constants and allow for non-memory-mapped task file registers. 2011-01-02 22:51:47 +00:00
avic-imx31.c
avic-imx31.h
boot.lds
ccm-imx31.c Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout. 2010-06-30 02:02:46 +00:00
ccm-imx31.h
crt0.S
debug-imx31.c move dbg_ports() from apps/menu_debug.c to target tree. FS#11712 by me. 2010-11-06 14:24:25 +00:00
debug-target.h move dbg_ports() from apps/menu_debug.c to target tree. FS#11712 by me. 2010-11-06 14:24:25 +00:00
dvfs_dptc-imx31.c Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout. 2010-06-30 02:02:46 +00:00
dvfs_dptc-imx31.h i.MX31/Gigabeat S: This should fix stability problems. One problem was to start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM. 2010-05-06 03:23:51 +00:00
gpio-imx31.c
gpio-imx31.h
i2c-imx31.c
i2c-imx31.h
iomuxc-imx31.c Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout. 2010-06-30 02:02:46 +00:00
iomuxc-imx31.h
mc13783-imx31.c Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout. 2010-06-30 02:02:46 +00:00
mmu-imx31.c
mmu-imx31.h
rolo_restart_firmware.S Introduce NORETURN_ATTR wrapper for __attribute__((noreturn)), using this and a bit further cleanup in main gets rid of a warning when compiling for android. 2010-08-12 13:38:25 +00:00
sdma-imx31.c i.MX31: Make DMA ISR call loop a bit more efficient. 2010-06-30 07:08:10 +00:00
sdma-imx31.h
sdma_script_code.h i.MX31: Only include the SDMA code that will be used on the target. Simplify the script selection. 2010-06-30 05:02:58 +00:00
sdma_struct.h
serial-imx31.h
spi-imx31.c
spi-imx31.h