204 lines
5.4 KiB
ArmAsm
204 lines
5.4 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/*
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* init.S
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*
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* Initialization code for JzRISC.
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*
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* Author: Seeger Chin
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* e-mail: seeger.chin@gmail.com
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*
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* Copyright (C) 2006 Ingenic Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include "config.h"
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#include "mips.h"
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.text
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.extern system_early_init
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.extern main
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.global _start
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.section .startup.text,"ax",%progbits
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.set push
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.set mips32
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.set noreorder
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.set noat
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#ifdef BOOTLOADER
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#ifndef XDUOO_X3
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/* These will get filled in by scramble */
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.word 0 /* Empty */
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.word 0 /* Filesize */
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/* Relocate bootloader */
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la t0, (_loadaddress-0xE00000)
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la t1, _loadaddress
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la t2, _bootend
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_relocate_loop:
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lw t3, 0(t0)
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addiu t1, 4
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addiu t0, 4
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bne t1, t2, _relocate_loop
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sw t3, -4(t1)
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#endif
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#endif
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_start:
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la ra, _start
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/*
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----------------------------------------------------
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Init CP0 registers.
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----------------------------------------------------
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*/
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mtc0 zero, C0_WATCHLO
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mtc0 zero, C0_WATCHHI
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li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \
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| M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \
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| M_StatusIM2 | M_StatusERL)
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/*
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BEV = Enable Boot Exception Vectors
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IMx = Interrupt mask
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ERL = Denotes error level
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*/
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mtc0 t0, C0_STATUS
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li t0, M_CauseIV
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mtc0 t0, C0_CAUSE
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/*
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----------------------------------------------------
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Init caches, assumes a 4way*128set*32byte I/D cache
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----------------------------------------------------
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*/
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li t0, 3 # enable cache for kseg0 accesses
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mtc0 t0, C0_CONFIG # CONFIG reg
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la t0, 0x80000000 # an idx op should use an unmappable address
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ori t1, t0, 0x4000 # 16kB cache
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mtc0 zero, C0_TAGLO # TAGLO reg
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mtc0 zero, C0_TAGHI # TAGHI reg
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_cache_loop:
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cache 0x8, 0(t0) # index store icache tag
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cache 0x9, 0(t0) # index store dcache tag
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addiu t0, t0, 0x20 # 32 bytes per cache line
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bne t0, t1, _cache_loop
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ssnop
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/*
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----------------------------------------------------
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Invalidate BTB
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----------------------------------------------------
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*/
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mfc0 t0, C0_CONFIG
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ssnop
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ori t0, 2
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mtc0 t0, C0_CONFIG
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ssnop
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/*
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----------------------------------------------------
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Copy IRAM section
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* copy IRAM first before BSS gets cleared, as both
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have the same address
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----------------------------------------------------
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*/
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la t0, _iramcopy
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la t1, _iramstart
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la t2, _iramend
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_iram_loop:
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lw t3, 0(t0)
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addiu t1, 4
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addiu t0, 4
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bne t1, t2, _iram_loop
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sw t3, -4(t1)
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#ifdef HAVE_INIT_ATTR
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/* Copy init code */
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la t0, _initcopy
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la t1, _initstart
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la t2, _initend
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_init_loop:
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lw t3, 0(t0)
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addiu t1, 4
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addiu t0, 4
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bne t1, t2, _init_loop
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sw t3, -4(t1)
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#endif
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/*
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----------------------------------------------------
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Clear BSS section
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----------------------------------------------------
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*/
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la t0, _edata
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la t1, _end
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_bss_loop:
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addiu t0, 4
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bne t0, t1, _bss_loop
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sw zero, -4(t0)
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/*
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----------------------------------------------------
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Set up stack
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----------------------------------------------------
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*/
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la sp, stackend
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la t0, stackbegin
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li t2, 0xDEADBEEF
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_stack_loop:
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addiu t0, 4
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bne t0, sp, _stack_loop
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sw t2, -4(t0)
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/*
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----------------------------------------------------
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Set up interrupt stack
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----------------------------------------------------
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*/
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la k0, _irqstackend
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la t0, _irqstackbegin
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_irq_stack_loop:
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addiu t0, 4
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bne t0, k0, _irq_stack_loop
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sw t2, -4(t0)
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/*
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----------------------------------------------------
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Jump to C code
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----------------------------------------------------
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*/
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jal system_early_init /* Init clocks etc first */
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ssnop
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j main
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move ra, zero /* init backtrace root */
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.set pop
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