2ac5153236
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28017 a1c6a512-1295-4272-9138-f99709370657
131 lines
4.5 KiB
C
131 lines
4.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "pl081.h"
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#include "dma-target.h"
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#include "panic.h"
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static int dma_used = 0;
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static void (*dma_callback[2])(void); /* 2 channels */
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void dma_retain(void)
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{
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if(++dma_used == 1)
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{
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bitset32(&CGU_PERI, CGU_DMA_CLOCK_ENABLE);
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DMAC_CONFIGURATION |= (1<<0);
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}
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}
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void dma_release(void)
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{
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if(--dma_used == 0)
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{
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DMAC_CONFIGURATION &= ~(1<<0);
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bitclr32(&CGU_PERI, CGU_DMA_CLOCK_ENABLE);
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}
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if (dma_used < 0)
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panicf("dma_used < 0!");
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}
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void dma_init(void)
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{
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#if CONFIG_CPU == AS3525
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DMAC_SYNC = 0xffff; /* disable synchronisation logic */
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#endif
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VIC_INT_ENABLE = INTERRUPT_DMAC;
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}
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void dma_disable_channel(int channel)
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{
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DMAC_CH_CONFIGURATION(channel) &= ~(1<<0);
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}
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void dma_enable_channel(int channel, void *src, void *dst, int peri,
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int flow_controller, bool src_inc, bool dst_inc,
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size_t size, int nwords, void (*callback)(void))
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{
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dma_callback[channel] = callback;
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/* Clear any pending interrupts leftover from previous operation */
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DMAC_INT_TC_CLEAR = (1<<channel);
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DMAC_INT_ERR_CLEAR = (1<<channel);
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DMAC_CH_SRC_ADDR(channel) = (int)src;
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DMAC_CH_DST_ADDR(channel) = (int)dst;
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/* When LLI is 0 channel is disabled upon transfer completion */
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DMAC_CH_LLI(channel) = 0;
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/* Channel Control Register */
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DMAC_CH_CONTROL(channel) =
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((1<<31) /* LLI triggers terminal count interrupt */
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/* | (1<<30) */ /* cacheable = 1, non = 0 */
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/* | (1<<29) */ /* bufferable = 1, non = 0 */
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/* | (1<<28) */ /* privileged = 1, user = 0 */
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| (dst_inc? (1<<27): 0) /* specify address increment */
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| (src_inc? (1<<26): 0) /* specify address increment */
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/* [25:24] */ /* undefined */
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| (2<<21) /* dst width = word, 32bit */
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| (2<<18) /* src width = word, 32bit */
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/* OF uses transfers of 4 * 32 bits words on memory, i2sin, i2sout */
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/* OF uses transfers of 8 * 32 bits words on SD */
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| (nwords<<15) /* dst size */
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| (nwords<<12) /* src size */
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| ((size & 0x7ff)<<0)); /* transfer size */
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/* Channel Config Register */
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DMAC_CH_CONFIGURATION(channel) =
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/* [31:19] */ /* Read undefined. Write as zero */
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/* (0<<18) */ /* Halt Bit */
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/* (0<<17) */ /* Active Bit */
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/* (0<<16) */ /* Lock Bit */
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(1<<15) /* terminal count interrupt mask */
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| (1<<14) /* interrupt error mask */
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| (flow_controller<<11) /* flow controller is peripheral or SDMAC */
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/* we set the same peripheral as source and destination because we
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* always use memory-to-peripheral or peripheral-to-memory transfers */
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| (peri<<6) /* dst peripheral */
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| (peri<<1) /* src peripheral */
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| (1<<0); /* enable channel */
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}
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/* isr */
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void INT_DMAC(void)
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{
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unsigned int channel;
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/* SD channel is serviced first */
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for(channel = 0; channel < 2; channel++)
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if(DMAC_INT_STATUS & (1<<channel))
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{
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if(DMAC_INT_ERROR_STATUS & (1<<channel))
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panicf("DMA error, channel %d", channel);
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/* clear terminal count interrupt */
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DMAC_INT_TC_CLEAR = (1<<channel);
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if(dma_callback[channel])
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dma_callback[channel]();
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}
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}
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