316 lines
8.9 KiB
C
316 lines
8.9 KiB
C
#include "mips.h"
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#include "atj213x.h"
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extern const unsigned short rockboxlogo[];
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unsigned short framebuffer[320*240] __attribute__((aligned(32))) = {[0 ... 76799] = 0};
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static void backlight_init(void)
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{
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/* backlight clock enable, select backlight clock as 32kHz */
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CMU_FMCLK = (CMU_FMCLK & ~(CMU_FMCLK_BCLK_MASK)) | CMU_FMCLK_BCKE | CMU_FMCLK_BCLK_32K;
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/* baclight enable */
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PMU_CTL |= PMU_CTL_BL_EN;
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/* pwm output, phase high, some initial duty cycle set as 24/32 */
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PMU_CHG = ((PMU_CHG & ~PMU_CHG_PDOUT_MASK)| PMU_CHG_PBLS_PWM | PMU_CHG_PPHS_HIGH | PMU_CHG_PDUT(24));
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}
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static void backlight_set(int level)
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{
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/* set duty cycle in 1/32 units */
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PMU_CHG = ((PMU_CHG & ~PMU_CHG_PDOUT_MASK) | PMU_CHG_PDUT(level));
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}
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static void wdt_feed(void)
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{
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RTC_WDCTL |= RTC_WDCTL_CLR;
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}
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void set_sw_interrupt0(void)
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{
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unsigned int val;
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asm volatile("mfc0 %0,$13" : "=r" (val));
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val |= 0x100;
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asm volatile("mtc0 %0,$13" : "+r" (val));
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}
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int lcm_wait_fifo_empty(void)
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{
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volatile int timeout = 100000;
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while (--timeout)
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if (YUV2RGB_CTL & 0x04)
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return 0;
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return -1;
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}
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static inline void lcm_rs_command(void)
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{
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lcm_wait_fifo_empty();
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YUV2RGB_CTL = 0x802ae;
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}
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static inline void lcm_rs_data(void)
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{
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lcm_wait_fifo_empty();
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YUV2RGB_CTL = 0x902ae;
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}
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static inline void lcm_fb_data(void)
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{
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lcm_rs_command();
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YUV2RGB_FIFODATA = 0x22; /* write GRAM command */
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YUV2RGB_CTL = 0xa02ae; /* AHB bus write fifo */
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}
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static inline lcd_reg_write(int reg, int val)
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{
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lcm_rs_command();
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YUV2RGB_FIFODATA = reg;
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lcm_rs_data();
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YUV2RGB_FIFODATA = val;
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}
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/* strips off MIPS segment coding */
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#define PHYADDR(x) ((x) & 0x1fffffff)
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/* rb compat defines */
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#define LCD_WIDTH 240
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#define LCD_HEIGHT 320
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#define FBADDR(x,y) ((short *)framebuffer + LCD_WIDTH*y + x)
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static void lcd_set_gram_area(int x_start, int y_start,
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int x_end, int y_end)
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{
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/* here we exploit the fact that width fits in LSB only */
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lcd_reg_write(0x02, 0x00); /* column start MSB */
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lcd_reg_write(0x03, x_start); /* column start LSB */
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lcd_reg_write(0x04, 0x00); /* column end MSB */
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lcd_reg_write(0x05, x_end); /* column end LSB */
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lcd_reg_write(0x06, y_start>>8); /* row start MSB */
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lcd_reg_write(0x07, y_start&0xff); /* row start LSB */
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lcd_reg_write(0x08, y_end>>8); /* row end MSB */
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lcd_reg_write(0x09, y_end&0xff); /* row end LSB */
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}
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void lcd_update_rect(int x, int y, int width, int height)
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{
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unsigned int end_x, end_y, row, col, *fbptr;
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x &= ~1; /* we transfer 2px at once */
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width = (width + 1) & ~1; /* adjust the width */
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end_x = x + width - 1;
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end_y = y + height - 1;
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lcd_set_gram_area(x, y, end_x, end_y); /* set GRAM window */
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lcm_fb_data(); /* prepare for AHB write to fifo */
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for (row=y; row<=end_y; row++)
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{
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fbptr = (uint32_t *)FBADDR(x,row);
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for (col=x; col<end_x; col+=2)
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YUV2RGB_FIFODATA = *fbptr++;
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}
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}
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/* for reference
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* When in act213x_fb_data()
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* YUV2RGB_CTL = 0xa02ae; -> DMA0-3 (AHB bus)
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* YUV2RGB_CTL = 0xa00ae; -> DMA4-7 (special bus)
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*/
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static void lcd_update_dma(void)
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{
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lcd_set_gram_area(0, 0, LCD_WIDTH-1, LCD_HEIGHT-1);
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/* AHB bus DMA channels are 0-3 */
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DMA_MODE(0) = (0x00<<29) | /* dst burst length = single */
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(0x00<<28) | /* DMA no reload */
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(0x00<<27) | /* dst DSP mode disable */
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(0x00<<26) | /* dst row mode */
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(0x00<<25) | /* dst address count dir - don't care */
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(0x01<<24) | /* dst fixed address */
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(0x18<<19) | /* dst DRQ trig source LCM */
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(0x02<<17) | /* dst transfer width 32bits */
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(0x01<<16) | /* dst transfer fixed size chunks */
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(0x05<<13) | /* src burst length = incr8 */
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(0x00<<12) | /* reserved */
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(0x00<<11) | /* src DSP mode disable */
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(0x00<<10) | /* src row mode */
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(0x00<<9) | /* src address count dir - increase */
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(0x00<<8) | /* src address not fixed */
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(0x10<<3) | /* src DRQ trig source SDRAM */
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(0x02<<1) | /* src transfer width 32bit */
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(0x00<<0); /* src transfer not in fixed chunks */
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DMA_SRC(0) = PHYADDR((uint32_t)framebuffer);
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DMA_DST(0) = PHYADDR((uint32_t)&YUV2RGB_FIFODATA);
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DMA_CNT(0) = 240*320*2; /* in bytes */
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DMA_CMD(0) = 1; /* start dma operation */
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}
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static lcm_init(void)
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{
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CMU_DEVCLKEN |= (1<<8)|(1<<1); /* dma clk, lcm clk */
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CMU_DMACLK = 1; /* DMA4 clock enable */
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/* reset DMA4 */
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DMAC_CTL |= (1<<20);
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udelay(1);
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DMAC_CTL &= ~(1<<20);
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GPIO_MFCTL1 = (1<<31); // enable multifunction
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GPIO_MFCTL0 = (GPIO_MFCTL0 & ~(0x07<<22 | 0x03<<14 | 0x03<<6 | 0x07<<3 | 0x07)) | // 0xfe3f3f00
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0x02<<22 | 0x02<<14 | 0x02<<6 | 0x02<<3|0x02; // 0x808092
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udelay(1);
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lcm_rs_command(); /* this has side effect of enabling whole block */
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YUV2RGB_CLKCTL = 0x102; /* lcm clock divider */
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}
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/* google says COG-IZT2298 is 2.8" lcd module */
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static lcd_init(void)
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{
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int x,y;
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/* lcd reset pin GPIOA16 */
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GPIO_AOUTEN |= (1<<16);
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GPIO_ADAT |= (1<<16);
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mdelay(10);
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GPIO_ADAT &= ~(1<<16);
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mdelay(10);
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GPIO_ADAT |= (1<<16);
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mdelay(10);
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/* lcd controller init sequence matching HX8347-D */
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lcd_reg_write(0xea, 0x00);
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lcd_reg_write(0xeb, 0x20);
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lcd_reg_write(0xec, 0x0f);
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lcd_reg_write(0xed, 0xc4);
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lcd_reg_write(0xe8, 0xc4);
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lcd_reg_write(0xe9, 0xc4);
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lcd_reg_write(0xf1, 0xc4);
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lcd_reg_write(0xf2, 0xc4);
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lcd_reg_write(0x27, 0xc4);
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lcd_reg_write(0x40, 0x00); /* gamma block start */
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lcd_reg_write(0x41, 0x00);
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lcd_reg_write(0x42, 0x01);
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lcd_reg_write(0x43, 0x13);
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lcd_reg_write(0x44, 0x10);
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lcd_reg_write(0x45, 0x26);
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lcd_reg_write(0x46, 0x08);
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lcd_reg_write(0x47, 0x51);
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lcd_reg_write(0x48, 0x02);
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lcd_reg_write(0x49, 0x12);
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lcd_reg_write(0x4a, 0x18);
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lcd_reg_write(0x4b, 0x19);
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lcd_reg_write(0x4c, 0x14);
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lcd_reg_write(0x50, 0x19);
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lcd_reg_write(0x51, 0x2f);
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lcd_reg_write(0x52, 0x2c);
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lcd_reg_write(0x53, 0x3e);
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lcd_reg_write(0x54, 0x3f);
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lcd_reg_write(0x55, 0x3f);
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lcd_reg_write(0x56, 0x2e);
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lcd_reg_write(0x57, 0x77);
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lcd_reg_write(0x58, 0x0b);
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lcd_reg_write(0x59, 0x06);
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lcd_reg_write(0x5a, 0x07);
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lcd_reg_write(0x5b, 0x0d);
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lcd_reg_write(0x5c, 0x1d);
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lcd_reg_write(0x5d, 0xcc); /* gamma block end */
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lcd_reg_write(0x1b, 0x1b);
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lcd_reg_write(0x1a, 0x01);
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lcd_reg_write(0x24, 0x2f);
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lcd_reg_write(0x25, 0x57);
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lcd_reg_write(0x23, 0x86);
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lcd_reg_write(0x18, 0x36); /* 70Hz framerate */
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lcd_reg_write(0x19, 0x01); /* osc enable */
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lcd_reg_write(0x01, 0x00);
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lcd_reg_write(0x1f, 0x88);
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mdelay(5);
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lcd_reg_write(0x1f, 0x80);
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mdelay(5);
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lcd_reg_write(0x1f, 0x90);
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mdelay(5);
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lcd_reg_write(0x1f, 0xd0);
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mdelay(5);
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lcd_reg_write(0x17, 0x05); /* 16bpp */
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lcd_reg_write(0x36, 0x00);
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lcd_reg_write(0x28, 0x38);
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mdelay(40);
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lcd_reg_write(0x28, 0x3c);
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lcd_reg_write(0x02, 0x00); /* column start MSB */
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lcd_reg_write(0x03, 0x00); /* column start LSB */
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lcd_reg_write(0x04, 0x00); /* column end MSB */
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lcd_reg_write(0x05, 0xef); /* column end LSB */
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lcd_reg_write(0x06, 0x00); /* row start MSB */
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lcd_reg_write(0x07, 0x00); /* row start LSB */
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lcd_reg_write(0x08, 0x01); /* row end MSB */
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lcd_reg_write(0x09, 0x3f); /* row end LSB */
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lcm_fb_data(); /* prepare for DMA write to fifo */
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/* clear lcd gram */
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for (y=0; y<LCD_HEIGHT; y++)
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for (x=0; x<(LCD_WIDTH>>1); x++)
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YUV2RGB_FIFODATA = 0;
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}
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int main(void)
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{
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int i;
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RTC_WDCTL &= ~(1<<4); /* disable WDT */
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/* Configure T0 interrupt as IP6. IP6 is unmasked in crt0.S */
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INTC_CFG0 = 0;
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INTC_CFG1 = 0;
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INTC_CFG2 = (1<<10);
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/* unmask T0 source in INTC */
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INTC_MSK |= (1<<10);
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backlight_init();
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/* copy rb logo image */
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for (i=0; i<240*74; i++)
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framebuffer[i] = rockboxlogo[i];
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lcm_init();
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lcd_init();
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lcd_update_rect(0,0,240,74);
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/* ADEC_N63.BIN seems to setup P_CLK as 7.5MHz which is timer clk */
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RTC_T0 = (7500000*10/32); /* with this we should see transition every ~0.3125s and 'black' every ~10s */
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RTC_T0CTL = (1<<5) | (1<<2) | (1<<1) | (1<<0); /* timer enable, timer reload, timer irq, clear irq pending bit */
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while(1)
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{
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/* otherwise wdt will trigger reset */
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//wdt_feed();
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}
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return 0;
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}
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/* Timer T0 interrupt service routine */
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INT_T0()
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{
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static int j = 0;
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/* clear pending bit in timer module */
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RTC_T0CTL |= 1;
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/* change backligh */
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backlight_set(++j);
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}
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