164876eaf1
The i2c core has some bugs: it locks up when the slave doesn't NAK and prevent the dma channel from being resetted. Specifically handle this situation by setting CLR_GOT_A_NAK (workaround) and then reset dma and i2c block. Change-Id: I0e09d38d4301a0ad42dfad785cc934b43f2c4485
270 lines
9.2 KiB
C
270 lines
9.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "kernel.h"
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#include "dma-imx233.h"
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#include "i2c-imx233.h"
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#include "pinctrl-imx233.h"
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#include "string.h"
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/**
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* Driver Architecture:
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* The driver has two interfaces: the good'n'old i2c_* api and a more
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* advanced one specific to the imx233 dma architecture. The i2c_* api is
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* implemented with the imx233_i2c_* one.
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* Since each i2c transfer must be split into several dma transfers and we
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* cannot do dynamic allocation, we allow for at most I2C_NR_STAGES stages.
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* A typical read memory transfer will require 3 stages thus 4 is safe:
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* - one with start, device address and memory address
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* - one with repeated start and device address
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* - one with data read and stop
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* To make the interface easier to use and to handle the DMA/cache related
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* issues, all the data transfers are done in a statically allocated buffer
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* which is managed by the driver. The driver will ensure that all transfers
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* are cache aligned and will copy back the data to user buffers at the end.
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* The I2C_BUFFER_SIZE define controls the size of the buffer. All transfers
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* should probably fit within 512 bytes.
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*/
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/* Used for DMA */
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struct i2c_dma_command_t
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{
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struct apb_dma_command_t dma;
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/* PIO words */
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uint32_t ctrl0;
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/* copy buffer copy */
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void *src;
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void *dst;
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/* padded to next multiple of cache line size (32 bytes) */
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uint32_t pad[2];
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} __attribute__((packed)) CACHEALIGN_ATTR;
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__ENSURE_STRUCT_CACHE_FRIENDLY(struct i2c_dma_command_t)
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#define I2C_NR_STAGES 4
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#define I2C_BUFFER_SIZE 512
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/* Current transfer */
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static int i2c_nr_stages;
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static struct i2c_dma_command_t i2c_stage[I2C_NR_STAGES];
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static struct mutex i2c_mutex;
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static struct semaphore i2c_sema;
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static uint8_t i2c_buffer[I2C_BUFFER_SIZE] CACHEALIGN_ATTR;
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static uint32_t i2c_buffer_end; /* current end */
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void INT_I2C_DMA(void)
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{
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/* reset dma channel on error */
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if(imx233_dma_is_channel_error_irq(APB_I2C))
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imx233_dma_reset_channel(APB_I2C);
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/* clear irq flags */
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imx233_dma_clear_channel_interrupt(APB_I2C);
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semaphore_release(&i2c_sema);
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}
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void INT_I2C_ERROR(void)
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{
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/* reset dma channel on error */
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if(imx233_dma_is_channel_error_irq(APB_I2C))
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imx233_dma_reset_channel(APB_I2C);
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/* clear irq flags */
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imx233_dma_clear_channel_interrupt(APB_I2C);
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semaphore_release(&i2c_sema);
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}
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static void imx233_i2c_reset(void)
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{
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/* clear softreset */
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imx233_reset_block(&HW_I2C_CTRL0);
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/* Errata (imx233):
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* When RETAIN_CLOCK is set, the ninth clock pulse (ACK) is not generated. However, the SDA
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* line is read at the proper timing interval. If RETAIN_CLOCK is cleared, the ninth clock pulse is
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* generated.
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* HW_I2C_CTRL1[ACK_MODE] has default value of 0. It should be set to 1 to enable the fix for
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* this issue.
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*/
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#if IMX233_SUBTARGET >= 3780
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BF_SET(I2C_CTRL1, ACK_MODE);
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#endif
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BF_SET(I2C_CTRL0, CLKGATE);
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/* Fast-mode @ 400K */
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HW_I2C_TIMING0 = 0x000F0007; /* tHIGH=0.6us, read at 0.3us */
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HW_I2C_TIMING1 = 0x001F000F; /* tLOW=1.3us, write at 0.6us */
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HW_I2C_TIMING2 = 0x0015000D;
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}
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void imx233_i2c_init(void)
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{
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BF_SET(I2C_CTRL0, SFTRST);
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/* setup pins (must be done when shutdown) */
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imx233_pinctrl_setup_vpin(VPIN_I2C_SCL, "i2c scl", PINCTRL_DRIVE_4mA, true);
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imx233_pinctrl_setup_vpin(VPIN_I2C_SDA, "i2c sda", PINCTRL_DRIVE_4mA, true);
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imx233_i2c_reset();
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mutex_init(&i2c_mutex);
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semaphore_init(&i2c_sema, 1, 0);
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}
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void imx233_i2c_begin(void)
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{
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mutex_lock(&i2c_mutex);
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/* wakeup */
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BF_CLR(I2C_CTRL0, CLKGATE);
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i2c_nr_stages = 0;
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i2c_buffer_end = 0;
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}
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enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer, unsigned size, bool stop)
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{
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if(i2c_nr_stages == I2C_NR_STAGES)
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return I2C_ERROR;
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/* align buffer end on cache boundary */
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uint32_t start_off = CACHEALIGN_UP(i2c_buffer_end);
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uint32_t end_off = start_off + size;
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if(end_off > I2C_BUFFER_SIZE)
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{
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panicf("die");
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return I2C_BUFFER_FULL;
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}
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i2c_buffer_end = end_off;
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if(transmit)
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{
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/* copy data to buffer */
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memcpy(i2c_buffer + start_off, buffer, size);
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}
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else
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{
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/* record pointers for finalization */
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i2c_stage[i2c_nr_stages].src = i2c_buffer + start_off;
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i2c_stage[i2c_nr_stages].dst = buffer;
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}
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if(i2c_nr_stages > 0)
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{
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i2c_stage[i2c_nr_stages - 1].dma.next = &i2c_stage[i2c_nr_stages].dma;
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i2c_stage[i2c_nr_stages - 1].dma.cmd |= BM_APB_CHx_CMD_CHAIN;
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if(!start)
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i2c_stage[i2c_nr_stages - 1].ctrl0 |= BM_I2C_CTRL0_RETAIN_CLOCK;
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}
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i2c_stage[i2c_nr_stages].dma.buffer = i2c_buffer + start_off;
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i2c_stage[i2c_nr_stages].dma.next = NULL;
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i2c_stage[i2c_nr_stages].dma.cmd = BF_OR4(APB_CHx_CMD,
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COMMAND(transmit ? BV_APB_CHx_CMD_COMMAND__READ : BV_APB_CHx_CMD_COMMAND__WRITE),
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WAIT4ENDCMD(1), CMDWORDS(1), XFER_COUNT(size));
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/* assume that any read is final (send nak on last) */
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i2c_stage[i2c_nr_stages].ctrl0 = BF_OR6(I2C_CTRL0,
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XFER_COUNT(size), DIRECTION(transmit), SEND_NAK_ON_LAST(!transmit),
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PRE_SEND_START(start), POST_SEND_STOP(stop), MASTER_MODE(1));
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i2c_nr_stages++;
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return I2C_SUCCESS;
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}
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static enum imx233_i2c_error_t imx233_i2c_finalize(void)
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{
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discard_dcache_range(i2c_buffer, I2C_BUFFER_SIZE);
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for(int i = 0; i < i2c_nr_stages; i++)
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{
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struct i2c_dma_command_t *c = &i2c_stage[i];
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if(BF_RDX(c->dma.cmd, APB_CHx_CMD, COMMAND) == BV_APB_CHx_CMD_COMMAND__WRITE)
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memcpy(c->dst, c->src, BF_RDX(c->dma.cmd, APB_CHx_CMD, XFER_COUNT));
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}
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return I2C_SUCCESS;
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}
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enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
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{
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if(i2c_nr_stages == 0)
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return I2C_ERROR;
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i2c_stage[i2c_nr_stages - 1].dma.cmd |= BM_APB_CHx_CMD_SEMAPHORE | BM_APB_CHx_CMD_IRQONCMPLT;
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BF_CLR(I2C_CTRL1, ALL_IRQ);
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imx233_dma_reset_channel(APB_I2C);
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imx233_icoll_enable_interrupt(INT_SRC_I2C_DMA, true);
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imx233_icoll_enable_interrupt(INT_SRC_I2C_ERROR, true);
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imx233_dma_enable_channel_interrupt(APB_I2C, true);
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imx233_dma_start_command(APB_I2C, &i2c_stage[0].dma);
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enum imx233_i2c_error_t ret;
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if(semaphore_wait(&i2c_sema, timeout) == OBJ_WAIT_TIMEDOUT)
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{
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imx233_dma_reset_channel(APB_I2C);
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ret = I2C_TIMEOUT;
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}
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else if(BF_RD(I2C_CTRL1, MASTER_LOSS_IRQ))
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ret = I2C_MASTER_LOSS;
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else if(BF_RD(I2C_CTRL1, NO_SLAVE_ACK_IRQ))
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{
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/* the core doesn't like this error, this is a workaround to prevent lock up */
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BF_SET(I2C_CTRL1, CLR_GOT_A_NAK);
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imx233_dma_reset_channel(APB_I2C);
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imx233_i2c_reset();
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ret= I2C_NO_SLAVE_ACK;
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}
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else if(BF_RD(I2C_CTRL1, EARLY_TERM_IRQ))
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ret = I2C_SLAVE_NAK;
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else
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ret = imx233_i2c_finalize();
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/* sleep */
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BF_SET(I2C_CTRL0, CLKGATE);
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mutex_unlock(&i2c_mutex);
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return ret;
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}
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void i2c_init(void)
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{
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}
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int i2c_write(int device, const unsigned char* buf, int count)
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{
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uint8_t addr = device;
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imx233_i2c_begin();
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imx233_i2c_add(true, true, &addr, 1, false); /* start + dev addr */
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imx233_i2c_add(false, true, (void *)buf, count, true); /* data + stop */
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return imx233_i2c_end(TIMEOUT_BLOCK);
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}
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int i2c_read(int device, unsigned char* buf, int count)
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{
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uint8_t addr = device | 1;
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imx233_i2c_begin();
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imx233_i2c_add(true, true, &addr, 1, false); /* start + dev addr */
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imx233_i2c_add(false, false, buf, count, true); /* data + stop */
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return imx233_i2c_end(TIMEOUT_BLOCK);
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}
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int i2c_readmem(int device, int address, unsigned char* buf, int count)
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{
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uint8_t start[2] = {device, address};
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uint8_t addr_rd = device | 1;
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imx233_i2c_begin();
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imx233_i2c_add(true, true, start, 2, false); /* start + dev addr + addr */
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imx233_i2c_add(true, true, &addr_rd, 1, false); /* start + dev addr */
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imx233_i2c_add(false, false, buf, count, true); /* data + stop */
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return imx233_i2c_end(TIMEOUT_BLOCK);
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}
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int i2c_writemem(int device, int address, const unsigned char* buf, int count)
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{
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uint8_t start[2] = {device, address};
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imx233_i2c_begin();
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imx233_i2c_add(true, true, start, 2, false); /* start + dev addr + addr */
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imx233_i2c_add(false, true, (void *)buf, count, true); /* data + stop */
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return imx233_i2c_end(TIMEOUT_BLOCK);
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}
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