140783ef66
Completely rewrite the Mafile, properly put the usb driver in its own file and the target specific files in a subdirectory. Change-Id: Iaeee0128e021d5dad76b4d6035a63e33e2d946c1
205 lines
6.5 KiB
C
205 lines
6.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "stddef.h"
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#include "target.h"
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#include "system.h"
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#include "logf.h"
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#define __REG_SET(reg) (*((volatile uint32_t *)(® + 1)))
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#define __REG_CLR(reg) (*((volatile uint32_t *)(® + 2)))
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#define __REG_TOG(reg) (*((volatile uint32_t *)(® + 3)))
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#define __BLOCK_SFTRST (1 << 31)
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#define __BLOCK_CLKGATE (1 << 30)
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#define __XTRACT(reg, field) ((reg & reg##__##field##_BM) >> reg##__##field##_BP)
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#define __XTRACT_EX(val, field) (((val) & field##_BM) >> field##_BP)
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#define __FIELD_SET(reg, field, val) reg = (reg & ~reg##__##field##_BM) | (val << reg##__##field##_BP)
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/**
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*
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* Global
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*
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*/
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enum stmp_family_t
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{
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UNKNOWN,
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STMP3600,
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STMP3700,
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STMP3770,
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STMP3780
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};
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enum stmp_family_t g_stmp_family = UNKNOWN;
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/**
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*
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* Clkctrl
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*
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*/
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#define HW_CLKCTRL_BASE 0x80040000
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#define HW_CLKCTRL_PLLCTRL0 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x0))
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#define HW_CLKCTRL_PLLCTRL0__BYPASS (1 << 17) /* STMP3600 only */
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#define HW_CLKCTRL_PLLCTRL0__POWER (1 << 16)
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#define HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS (1 << 18)
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#define HW_CLKCTRL_PLLCTRL1 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x10))
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#define HW_CLKCTRL_PLLCTRL1__LOCK (1 << 31)
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/* STMP3600 only */
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#define HW_CLKCTRL_CPUCLKCTRL (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x20))
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#define HW_CLKCTRL_CPUCLKCTRL__DIV_BP 0
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#define HW_CLKCTRL_CPUCLKCTRL__DIV_BM 0x3ff
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#define HW_CLKCTRL_CPUCLKCTRL__WAIT_PLL_LOCK (1 << 30)
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/* STMP3600 */
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#define HW_CLKCTRL_HBUSCLKCTRL (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x30))
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/* STMP3600 only */
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#define HW_CLKCTRL_XBUSCLKCTRL (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40))
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#define HW_CLKCTRL_XBUSCLKCTRL__DIV_BP 0
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#define HW_CLKCTRL_XBUSCLKCTRL__DIV_BM 0x3ff
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/* STMP3600 only */
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#define HW_CLKCTRL_UTMICLKCTRL (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70))
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#define HW_CLKCTRL_UTMICLKCTRL__UTMI_CLK30M_GATE (1 << 30)
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#define HW_CLKCTRL_UTMICLKCTRL__UTMI_CLK120M_GATE (1 << 31)
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/**
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*
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* Digctl
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*
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*/
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/* Digital control */
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#define HW_DIGCTL_BASE 0x8001C000
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#define HW_DIGCTL_CTRL (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0))
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#define HW_DIGCTL_CTRL__USB_CLKGATE (1 << 2)
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#define HW_DIGCTL_MICROSECONDS (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0))
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#define HW_DIGCTL_CHIPID (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x310))
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#define HW_DIGCTL_CHIPID__PRODUCT_CODE_BP 16
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#define HW_DIGCTL_CHIPID__PRODUCT_CODE_BM 0xffff0000
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#define HW_DIGCTL_CHIPID__REVISION_BP 0
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#define HW_DIGCTL_CHIPID__REVISION_BM 0xff
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#define HZ 1000000
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/**
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*
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* USB PHY
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*
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*/
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/* USB Phy */
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#define HW_USBPHY_BASE 0x8007C000
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#define HW_USBPHY_PWD (*(volatile uint32_t *)(HW_USBPHY_BASE + 0))
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#define HW_USBPHY_CTRL (*(volatile uint32_t *)(HW_USBPHY_BASE + 0x30))
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void target_init(void)
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{
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/* detect family */
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uint16_t product_code = __XTRACT(HW_DIGCTL_CHIPID, PRODUCT_CODE);
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if(product_code >= 0x3600 && product_code < 0x3700)
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{
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logf("identified STMP3600 family\n");
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g_stmp_family = STMP3600;
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}
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else if(product_code == 0x3700)
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{
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logf("identified STMP3700 family\n");
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g_stmp_family = STMP3700;
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}
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else if(product_code == 0x37b0)
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{
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logf("identified STMP3770 family\n");
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g_stmp_family = STMP3770;
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}
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else if(product_code == 0x3780)
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{
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logf("identified STMP3780 family\n");
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g_stmp_family = STMP3780;
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}
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else
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logf("cannot identify family: 0x%x\n", product_code);
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if(g_stmp_family == STMP3600)
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{
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/* CPU clock is always derived from PLL, if we switch to PLL, cpu will
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* run at 480 MHz unprepared ! That's bad so prepare to run at slow sleed
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* (1.2MHz) for a safe transition */
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HW_CLKCTRL_CPUCLKCTRL = HW_CLKCTRL_CPUCLKCTRL__WAIT_PLL_LOCK | 400;
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/* We need to ensure that XBUS < HBUS but HBUS will be 1.2 MHz after the
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* switch so lower XBUS too */
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HW_CLKCTRL_XBUSCLKCTRL = 20;
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/* Power PLL */
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__REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__POWER;
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HW_CLKCTRL_PLLCTRL0 = (HW_CLKCTRL_PLLCTRL0 & ~0x3ff) | 480;
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/* Wait lock */
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while(!(HW_CLKCTRL_PLLCTRL1 & HW_CLKCTRL_PLLCTRL1__LOCK));
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/* Switch to PLL source */
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__REG_CLR(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__BYPASS;
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/* Get back XBUS = 24 MHz and CPU = HBUS = 64MHz */
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HW_CLKCTRL_CPUCLKCTRL = 7;
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HW_CLKCTRL_HBUSCLKCTRL = 7;
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HW_CLKCTRL_XBUSCLKCTRL = 1;
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__REG_CLR(HW_CLKCTRL_UTMICLKCTRL) = HW_CLKCTRL_UTMICLKCTRL__UTMI_CLK120M_GATE;
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__REG_CLR(HW_CLKCTRL_UTMICLKCTRL) = HW_CLKCTRL_UTMICLKCTRL__UTMI_CLK30M_GATE;
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}
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else
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__REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__POWER;
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/* enable USB PHY PLL */
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__REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
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/* power up USB PHY */
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__REG_CLR(HW_USBPHY_CTRL) = __BLOCK_CLKGATE | __BLOCK_SFTRST;
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HW_USBPHY_PWD = 0;
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/* enable USB controller */
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__REG_CLR(HW_DIGCTL_CTRL) = HW_DIGCTL_CTRL__USB_CLKGATE;
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}
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static struct usb_resp_info_stmp_t g_stmp;
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static struct usb_resp_info_target_t g_target =
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{
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.id = HWSTUB_TARGET_STMP,
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.name = "STMP3600 / STMP3700 / STMP3780 (i.MX233)"
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};
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int target_get_info(int info, void **buffer)
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{
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if(info == HWSTUB_INFO_STMP)
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{
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g_stmp.chipid = __XTRACT(HW_DIGCTL_CHIPID, PRODUCT_CODE);
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g_stmp.rev = __XTRACT(HW_DIGCTL_CHIPID, REVISION);
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g_stmp.is_supported = g_stmp_family != 0;
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*buffer = &g_stmp;
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return sizeof(g_stmp);
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}
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else
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return -1;
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}
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void target_exit(void)
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{
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}
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