208 lines
No EOL
8 KiB
C
208 lines
No EOL
8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "emi-imx233.h"
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#include "clkctrl-imx233.h"
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#include "string.h"
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struct emi_reg_t
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{
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int index;
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uint32_t value;
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};
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/* hardcode all the register values for the different settings. This avoid
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* computing the register values at runtime since they never change and also
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* avoid wasting some space in iram.
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* Values from IMX233 manual, for Mobile DDR 7.5ns (133 MHz and 64MHz)
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* Make sure the last value is written to register 40. */
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static struct emi_reg_t settings_60M[15] ICONST_ATTR =
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{
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{4, 0x01000101}, /* DLL bypass mode, concurrent auto-precharge and bank split */
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{7, 0x01000101}, /* Read/write grouping, extra clock for back to back, priority placement */
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{12, 0x02020002}, /* tWR = 2 cycles, tRRD = 1 cycles, tCKE = 2 cycles */
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{13, 0x06060a02}, /* CAS lat gate = 3.0 cycles, CAS lat = 3.0 cycles, tWTR = 2 */
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{15, 0x02040000}, /* tRP = 2 cycles, tDAL = 4 cycles */
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{17, 0x2d000005}, /* DDL: start point = 45, lock = 0, increment = 0, tRC = 5 cycles */
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{18, 0x00000000}, /* */
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{19, 0x01000b0b}, /* DLL: DQS out shift (bypass) = 1, DQS delay bypass (1/0) = 11 / 11 */
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{20, 0x02030a00}, /* tRCD = 2 cycles, tRAS (min) = 3 cycles, DQS write shift (bypass) = 10 */
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{21, 0x00000005}, /* tRFC = 5 cycles */
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{26, 0x000001cc}, /* tREF = 460 cycles */
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{32, 0x00081060}, /* tRAS (max) = 4192 cycles, tXSNR = 8 cycles */
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{33, 0x00000008}, /* tXSR = 8 cycles */
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{34, 0x00002ee5}, /* tINIT = 12005 cycles */
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{40, 0x00020000} /* tPDEX = 2 */
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};
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static struct emi_reg_t settings_133M[15] ICONST_ATTR =
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{
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{4, 0x00000101}, /* concurrent auto-precharge and bank split */
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{7, 0x01000001}, /* Read/write grouping, priority placement */
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{12, 0x02020002}, /* tWR = 2 cycles, tRRD = 2 cycles, tCKE = 2 cycles */
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{13, 0x06070a02}, /* CAS lat gate = 3.0 cycles, CAS lat = 3.5 cycles, tWTR = 2 */
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{15, 0x03050000}, /* tRP = 3 cycles, tDAL = 5 cycles */
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{17, 0x19000f0a}, /* DDL: start point = 25, lock = 0, increment = 15, tRC = 10 cycles */
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{18, 0x1f1f0000}, /* DLL: DQS delay (1/0) = 31 / 31 */
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{19, 0x000a0000}, /* DLL: DQS out shift = 10 */
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{20, 0x03060023}, /* tRCD = 3 cycles, tRAS (min) = 6 cycles, DQS write shift = 35 */
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{21, 0x0000000a}, /* tRFC = 10 cycles */
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{26, 0x000003f7}, /* tREF = 1015 cycles */
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{32, 0x001023cd}, /* tRAS (max) = 9165 cycles, tXSNR = 16 cycles */
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{33, 0x00000010}, /* tXSR = 16 cycles */
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{34, 0x00006665}, /* tINIT = 26213 cycles */
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{40, 0x00040000} /* tPDEX = 4 */
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};
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static struct emi_reg_t settings_155M[15] ICONST_ATTR __attribute__((alias("settings_133M")));
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static void set_frequency(unsigned long freq) ICODE_ATTR;
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#if IMX233_SUBTARGET >= 3700
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static void set_frequency(unsigned long freq)
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{
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/** WARNING all restriction of imx233_emi_set_frequency apply here !! */
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/* Set divider and clear clkgate. */
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unsigned fracdiv;
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unsigned div;
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switch(freq)
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{
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case IMX233_EMIFREQ_151_MHz:
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/* clk_emi@ref_emi/3*18/19 */
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fracdiv = 19;
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div = 3;
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/* ref_emi@480 MHz
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* clk_emi@151.58 MHz */
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break;
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case IMX233_EMIFREQ_130_MHz:
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/* clk_emi@ref_emi/2*18/33 */
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fracdiv = 33;
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div = 2;
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/* ref_emi@480 MHz
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* clk_emi@130.91 MHz */
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break;
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case IMX233_EMIFREQ_64_MHz:
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default:
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/* clk_emi@ref_emi/5*18/27 */
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fracdiv = 27;
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div = 5;
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/* ref_emi@480 MHz
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* clk_emi@64 MHz */
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break;
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}
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BF_WR(CLKCTRL_FRAC, CLKGATEEMI, 0);
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BF_WR(CLKCTRL_FRAC, EMIFRAC, fracdiv);
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BF_WR(CLKCTRL_EMI, CLKGATE, 0);
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BF_WR(CLKCTRL_EMI, DIV_EMI, div);
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}
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void imx233_emi_set_frequency(unsigned long freq) ICODE_ATTR;
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void imx233_emi_set_frequency(unsigned long freq)
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{
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/** FIXME we rely on the compiler to NOT use the stack here because it's
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* not in iram ! If it's not smart enough, one can switch the switch to use
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* the irq stack since we are running interrupts disable here ! */
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/** BUG for freq<=24 MHz we must keep bypass mode since we run on xtal
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* since this setting is unused by our code so ignore this bug for now */
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/** WARNING DANGER
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* Changing the EMI frequency is complicated because it requires to
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* completely shutdown the external memory interface. We must make sure
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* that this code and all the data it uses in in iram and that no access to
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* the sdram will be made during the change. Care must be taken w.r.t to
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* the cache also. */
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/** FIXME assume that auto-slow is disabled here since that could put some
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* clock below the minimum value and we want to spend as least time as
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* possible in this state anyway.
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* WARNING DANGER don't call any external function when sdram is disabled
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* otherwise you'll poke sdram and trigger a fatal data abort ! */
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/* first disable all interrupts */
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int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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/* flush the cache */
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commit_discard_idcache();
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/* put DRAM into self-refresh mode */
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HW_DRAM_CTL08 |= BM_DRAM_CTL08_SREFRESH;
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/* wait for DRAM to be halted */
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while(!BF_RD(EMI_STAT, DRAM_HALTED));
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/* load timings */
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struct emi_reg_t *regs;
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switch(freq)
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{
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case IMX233_EMIFREQ_151_MHz:
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regs = settings_155M;
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break;
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case IMX233_EMIFREQ_130_MHz:
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regs = settings_133M;
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break;
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case IMX233_EMIFREQ_64_MHz:
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default:
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regs = settings_60M;
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break;
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}
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do
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HW_DRAM_CTLxx(regs->index) = regs->value;
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while((regs++)->index != 40);
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/* switch emi to xtal */
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BF_SET(CLKCTRL_CLKSEQ, BYPASS_EMI);
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/* wait for transition */
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while(BF_RD(CLKCTRL_EMI, BUSY_REF_XTAL));
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/* put emi dll into reset mode */
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// FIXME Unsure about what to do for stmp37xx
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#if IMX233_SUBTARGET >= 3780
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HW_EMI_CTRL_SET = BM_EMI_CTRL_DLL_RESET | BM_EMI_CTRL_DLL_SHIFT_RESET;
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#endif
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/* load the new frequency dividers */
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set_frequency(freq);
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/* switch emi back to pll */
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BF_CLR(CLKCTRL_CLKSEQ, BYPASS_EMI);
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/* wait for transition */
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while(BF_RD(CLKCTRL_EMI, BUSY_REF_EMI));
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/* allow emi dll to lock again */
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#if IMX233_SUBTARGET >= 3780
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HW_EMI_CTRL_CLR = BM_EMI_CTRL_DLL_RESET | BM_EMI_CTRL_DLL_SHIFT_RESET;
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#endif
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/* wait for lock */
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while(!BF_RD(DRAM_CTL04, DLLLOCKREG));
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/* get DRAM out of self-refresh mode */
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HW_DRAM_CTL08 &= ~BM_DRAM_CTL08_SREFRESH;
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/* wait for DRAM to be to run again */
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while(HW_EMI_STAT & BM_EMI_STAT_DRAM_HALTED);
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restore_interrupt(oldstatus);
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}
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#endif
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struct imx233_emi_info_t imx233_emi_get_info(void)
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{
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struct imx233_emi_info_t info;
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memset(&info, 0, sizeof(info));
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#if IMX233_SUBTARGET >= 3700
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info.rows = 13 - BF_RD(DRAM_CTL10, ADDR_PINS);
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info.columns = 12 - BF_RD(DRAM_CTL11, COLUMN_SIZE);
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info.cas = BF_RD(DRAM_CTL13, CASLAT_LIN);
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info.banks = 4;
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info.chips = __builtin_popcount(BF_RD(DRAM_CTL14, CS_MAP));
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info.size = 2 * (1 << (info.rows + info.columns)) * info.chips * info.banks;
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#endif
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return info;
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} |