b424b852e5
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23243 a1c6a512-1295-4272-9138-f99709370657
495 lines
15 KiB
C
495 lines
15 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "kernel.h"
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#include "cpu.h"
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#include "inttypes.h"
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#include "nand-target.h"
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#include <pmu-target.h>
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#include <mmu-target.h>
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#include <string.h>
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#define NAND_CMD_READ 0x00
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#define NAND_CMD_PROGCNFRM 0x10
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#define NAND_CMD_READ2 0x30
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#define NAND_CMD_BLOCKERASE 0x60
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#define NAND_CMD_GET_STATUS 0x70
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#define NAND_CMD_PROGRAM 0x80
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#define NAND_CMD_ERASECNFRM 0xD0
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#define NAND_CMD_RESET 0xFF
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#define NAND_STATUS_READY 0x40
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#define NAND_DEVICEINFOTABLE_ENTRIES 33
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static const struct nand_device_info_type nand_deviceinfotable[] =
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{
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{0x1580F1EC, 1024, 968, 0x40, 6, 2, 1, 2, 1},
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{0x1580DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
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{0x15C1DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
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{0x1510DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0x95C1DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0x2514DCEC, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
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{0x2514D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0x2555D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0x2555D5EC, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
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{0x2585D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
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{0x9580DCAD, 4096, 3872, 0x40, 6, 3, 2, 3, 2},
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{0xA514D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
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{0xA550D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
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{0xA560D5AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
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{0xA555D5AD, 8192, 7744, 0x80, 7, 3, 2, 3, 2},
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{0xA585D598, 8320, 7744, 0x80, 7, 3, 1, 2, 1},
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{0xA584D398, 4160, 3872, 0x80, 7, 3, 1, 2, 1},
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{0x95D1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
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{0x1580DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0x15C1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
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{0x9590DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0xA594D32C, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0x2584DC2C, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
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{0xA5D5D52C, 8192, 7744, 0x80, 7, 3, 2, 2, 1},
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{0x95D1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
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{0x1580DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0x15C1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
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{0x9590DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0xA594D389, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0x2584DC89, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
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{0xA5D5D589, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
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{0xA514D320, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0xA555D520, 8192, 3872, 0x80, 7, 2, 1, 2, 1}
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};
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uint8_t nand_tunk1[4];
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uint8_t nand_twp[4];
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uint8_t nand_tunk2[4];
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uint8_t nand_tunk3[4];
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uint32_t nand_type[4];
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int nand_powered = 0;
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static struct mutex nand_mtx;
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static struct wakeup nand_wakeup;
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static struct mutex ecc_mtx;
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static struct wakeup ecc_wakeup;
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static uint8_t nand_data[0x800] __attribute__((aligned(16)));
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static uint8_t nand_ctrl[0x200] __attribute__((aligned(16)));
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static uint8_t nand_spare[0x40] __attribute__((aligned(16)));
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static uint8_t nand_ecc[0x30] __attribute__((aligned(16)));
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uint32_t nand_unlock(uint32_t rc)
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{
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mutex_unlock(&nand_mtx);
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return rc;
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}
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uint32_t ecc_unlock(uint32_t rc)
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{
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mutex_unlock(&ecc_mtx);
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return rc;
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}
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uint32_t nand_timeout(long timeout)
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{
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if (TIME_AFTER(current_tick, timeout)) return 1;
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else
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{
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yield();
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return 0;
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}
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}
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uint32_t nand_wait_rbbdone(void)
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{
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long timeout = current_tick + HZ / 50;
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while (!(FMCSTAT & FMCSTAT_RBBDONE))
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if (nand_timeout(timeout)) return 1;
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FMCSTAT = FMCSTAT_RBBDONE;
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return 0;
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}
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uint32_t nand_wait_cmddone(void)
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{
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long timeout = current_tick + HZ / 50;
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while (!(FMCSTAT & FMCSTAT_CMDDONE))
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if (nand_timeout(timeout)) return 1;
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FMCSTAT = FMCSTAT_CMDDONE;
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return 0;
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}
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uint32_t nand_wait_addrdone(void)
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{
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long timeout = current_tick + HZ / 50;
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while (!(FMCSTAT & FMCSTAT_ADDRDONE))
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if (nand_timeout(timeout)) return 1;
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FMCSTAT = FMCSTAT_ADDRDONE;
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return 0;
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}
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uint32_t nand_wait_chip_ready(uint32_t bank)
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{
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long timeout = current_tick + HZ / 50;
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while (!(FMCSTAT & (FMCSTAT_BANK0READY << bank)))
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if (nand_timeout(timeout)) return 1;
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FMCSTAT = (FMCSTAT_BANK0READY << bank);
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return 0;
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}
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void nand_set_fmctrl0(uint32_t bank, uint32_t flags)
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{
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FMCTRL0 = (nand_tunk1[bank] << 16) | (nand_twp[bank] << 12)
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| (1 << 11) | 1 | (1 << (bank + 1)) | flags;
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}
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uint32_t nand_send_cmd(uint32_t cmd)
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{
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FMCMD = cmd;
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return nand_wait_rbbdone();
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}
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uint32_t nand_send_address(uint32_t page, uint32_t offset)
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{
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FMANUM = 4;
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FMADDR0 = (page << 16) | offset;
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FMADDR1 = (page >> 16) & 0xFF;
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FMCTRL1 = FMCTRL1_DOTRANSADDR;
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return nand_wait_cmddone();
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}
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uint32_t nand_reset(uint32_t bank)
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{
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nand_set_fmctrl0(bank, 0);
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if (nand_send_cmd(NAND_CMD_RESET)) return 1;
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if (nand_wait_chip_ready(bank)) return 1;
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FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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return 0;
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}
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uint32_t nand_wait_status_ready(uint32_t bank)
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{
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long timeout = current_tick + HZ / 50;
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nand_set_fmctrl0(bank, 0);
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if ((FMCSTAT & (FMCSTAT_BANK0READY << bank)))
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FMCSTAT = (FMCSTAT_BANK0READY << bank);
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FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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if (nand_send_cmd(NAND_CMD_GET_STATUS)) return 1;
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while (1)
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{
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if (nand_timeout(timeout)) return 1;
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FMDNUM = 0;
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FMCTRL1 = FMCTRL1_DOREADDATA;
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if (nand_wait_addrdone()) return 1;
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if ((FMFIFO & NAND_STATUS_READY)) break;
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FMCTRL1 = FMCTRL1_CLEARRFIFO;
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}
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FMCTRL1 = FMCTRL1_CLEARRFIFO;
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return nand_send_cmd(NAND_CMD_READ);
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}
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uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
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void* buffer, uint32_t size)
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{
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long timeout = current_tick + HZ / 50;
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nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
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FMDNUM = size - 1;
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FMCTRL1 = FMCTRL1_DOREADDATA << direction;
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DMACON3 = (2 << DMACON_DEVICE_SHIFT)
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| (direction << DMACON_DIRECTION_SHIFT)
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| (2 << DMACON_DATA_SIZE_SHIFT)
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| (3 << DMACON_BURST_LEN_SHIFT);
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while ((DMAALLST & DMAALLST_CHAN3_MASK))
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DMACOM3 = DMACOM_CLEARBOTHDONE;
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DMABASE3 = (uint32_t)buffer;
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DMATCNT3 = (size >> 4) - 1;
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clean_dcache();
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DMACOM3 = 4;
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while ((DMAALLST & DMAALLST_DMABUSY3))
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if (nand_timeout(timeout)) return 1;
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if (!direction) invalidate_dcache();
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if (nand_wait_addrdone()) return 1;
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if (!direction) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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return 0;
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}
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uint32_t ecc_decode(uint32_t size, void* databuffer, void* sparebuffer)
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{
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mutex_lock(&ecc_mtx);
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long timeout = current_tick + HZ / 50;
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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ECC_UNK1 = size;
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ECC_DATA_PTR = (uint32_t)databuffer;
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ECC_SPARE_PTR = (uint32_t)sparebuffer;
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clean_dcache();
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ECC_CTRL = ECCCTRL_STARTDECODING;
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while (!(SRCPND & INTMSK_ECC))
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if (nand_timeout(timeout)) return ecc_unlock(1);
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invalidate_dcache();
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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return ecc_unlock(ECC_RESULT);
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}
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uint32_t ecc_encode(uint32_t size, void* databuffer, void* sparebuffer)
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{
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mutex_lock(&ecc_mtx);
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long timeout = current_tick + HZ / 50;
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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ECC_UNK1 = size;
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ECC_DATA_PTR = (uint32_t)databuffer;
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ECC_SPARE_PTR = (uint32_t)sparebuffer;
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clean_dcache();
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ECC_CTRL = ECCCTRL_STARTENCODING;
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while (!(SRCPND & INTMSK_ECC))
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if (nand_timeout(timeout)) return ecc_unlock(1);
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invalidate_dcache();
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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return ecc_unlock(0);
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}
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uint32_t nand_check_empty(uint8_t* buffer)
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{
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uint32_t i, count;
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count = 0;
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for (i = 0; i < 0x40; i++) if (buffer[i] != 0xFF) count++;
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if (count < 2) return 1;
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return 0;
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}
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uint32_t nand_get_chip_type(uint32_t bank)
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{
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mutex_lock(&nand_mtx);
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uint32_t result;
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if (nand_reset(bank)) return nand_unlock(0xFFFFFFFF);
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if (nand_send_cmd(0x90)) return nand_unlock(0xFFFFFFFF);
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FMANUM = 0;
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FMADDR0 = 0;
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FMCTRL1 = FMCTRL1_DOTRANSADDR;
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if (nand_wait_cmddone()) return nand_unlock(0xFFFFFFFF);
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FMDNUM = 4;
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FMCTRL1 = FMCTRL1_DOREADDATA;
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if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFF);
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result = FMFIFO;
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FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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return nand_unlock(result);
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}
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void nand_power_up(void)
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{
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uint32_t i;
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mutex_lock(&nand_mtx);
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PWRCONEXT &= ~0x40;
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PWRCON &= ~0x100000;
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PCON2 = 0x33333333;
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PDAT2 = 0;
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PCON3 = 0x11113333;
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PDAT3 = 0;
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PCON4 = 0x33333333;
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PDAT4 = 0;
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PCON5 = (PCON5 & ~0xF) | 3;
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PUNK5 = 1;
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pmu_ldo_set_voltage(4, 0x15);
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pmu_ldo_power_on(4);
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sleep(HZ / 20);
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for (i = 0; i < 4; i++) nand_reset(i);
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nand_powered = 1;
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mutex_unlock(&nand_mtx);
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}
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void nand_power_down(void)
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{
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mutex_lock(&nand_mtx);
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pmu_ldo_power_off(4);
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PCON2 = 0x11111111;
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PDAT2 = 0;
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PCON3 = 0x11111111;
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PDAT3 = 0;
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PCON4 = 0x11111111;
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PDAT4 = 0;
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PCON5 = (PCON5 & ~0xF) | 1;
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PUNK5 = 1;
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PWRCONEXT |= 0x40;
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PWRCON |= 0x100000;
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nand_powered = 0;
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mutex_unlock(&nand_mtx);
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}
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uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
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void* sparebuffer, uint32_t doecc,
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uint32_t checkempty)
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{
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uint8_t* data = nand_data;
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uint8_t* spare = nand_spare;
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if (databuffer && !((uint32_t)databuffer & 0xf))
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data = (uint8_t*)databuffer;
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if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
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spare = (uint8_t*)sparebuffer;
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mutex_lock(&nand_mtx);
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if (!nand_powered) nand_power_up();
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uint32_t rc, eccresult;
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nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
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if (nand_send_cmd(NAND_CMD_READ)) return nand_unlock(1);
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if (nand_send_address(page, databuffer ? 0 : 0x800))
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return nand_unlock(1);
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if (nand_send_cmd(NAND_CMD_READ2)) return nand_unlock(1);
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if (nand_wait_status_ready(bank)) return nand_unlock(1);
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if (databuffer)
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if (nand_transfer_data(bank, 0, data, 0x800))
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return nand_unlock(1);
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rc = 0;
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if (!doecc)
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{
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if (databuffer && data != databuffer) memcpy(databuffer, data, 0x800);
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if (sparebuffer)
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{
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if (nand_transfer_data(bank, 0, spare, 0x40))
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return nand_unlock(1);
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if (sparebuffer && spare != sparebuffer)
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memcpy(sparebuffer, spare, 0x800);
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if (checkempty)
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rc = nand_check_empty((uint8_t*)sparebuffer) << 1;
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}
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return nand_unlock(rc);
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}
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if (nand_transfer_data(bank, 0, spare, 0x40)) return nand_unlock(1);
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memcpy(nand_ecc, &spare[0xC], 0x28);
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rc |= (ecc_decode(3, data, nand_ecc) & 0xF) << 4;
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if (databuffer && data != databuffer) memcpy(databuffer, data, 0x800);
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memset(nand_ctrl, 0xFF, 0x200);
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memcpy(nand_ctrl, spare, 0xC);
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memcpy(nand_ecc, &spare[0x34], 0xC);
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eccresult = ecc_decode(0, nand_ctrl, nand_ecc);
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rc |= (eccresult & 0xF) << 8;
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if (sparebuffer)
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{
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if (spare != sparebuffer) memcpy(sparebuffer, spare, 0x40);
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if (eccresult & 1) memset(sparebuffer, 0xFF, 0xC);
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else memcpy(sparebuffer, nand_ctrl, 0xC);
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}
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if (checkempty) rc |= nand_check_empty(spare) << 1;
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return nand_unlock(rc);
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}
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uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
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void* sparebuffer, uint32_t doecc)
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{
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uint8_t* data = nand_data;
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uint8_t* spare = nand_spare;
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if (databuffer && !((uint32_t)databuffer & 0xf))
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data = (uint8_t*)databuffer;
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if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
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spare = (uint8_t*)sparebuffer;
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mutex_lock(&nand_mtx);
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if (!nand_powered) nand_power_up();
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if (sparebuffer)
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{
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if (spare != sparebuffer) memcpy(spare, sparebuffer, 0x40);
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}
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else memset(spare, 0xFF, 0x40);
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if (doecc)
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{
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if (databuffer && data != databuffer) memcpy(data, databuffer, 0x800);
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if (ecc_encode(3, data, nand_ecc)) return nand_unlock(1);
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memcpy(&spare[0xC], nand_ecc, 0x28);
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memset(nand_ctrl, 0xFF, 0x200);
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memcpy(nand_ctrl, spare, 0xC);
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if (ecc_encode(0, nand_ctrl, nand_ecc)) return nand_unlock(1);
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memcpy(&spare[0x34], nand_ecc, 0xC);
|
|
}
|
|
nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
|
|
if (nand_send_cmd(NAND_CMD_PROGRAM)) return nand_unlock(1);
|
|
if (nand_send_address(page, databuffer ? 0 : 0x800))
|
|
return nand_unlock(1);
|
|
if (databuffer)
|
|
if (nand_transfer_data(bank, 1, data, 0x800))
|
|
return nand_unlock(1);
|
|
if (sparebuffer || doecc)
|
|
if (nand_transfer_data(bank, 1, spare, 0x40))
|
|
return nand_unlock(1);
|
|
if (nand_send_cmd(NAND_CMD_PROGCNFRM)) return nand_unlock(1);
|
|
return nand_unlock(nand_wait_status_ready(bank));
|
|
}
|
|
|
|
uint32_t nand_block_erase(uint32_t bank, uint32_t page)
|
|
{
|
|
mutex_lock(&nand_mtx);
|
|
if (!nand_powered) nand_power_up();
|
|
nand_set_fmctrl0(bank, 0);
|
|
if (nand_send_cmd(NAND_CMD_BLOCKERASE)) return nand_unlock(1);
|
|
FMANUM = 2;
|
|
FMADDR0 = page;
|
|
FMCTRL1 = FMCTRL1_DOTRANSADDR;
|
|
if (nand_wait_cmddone()) return nand_unlock(1);
|
|
if (nand_send_cmd(NAND_CMD_ERASECNFRM)) return nand_unlock(1);
|
|
if (nand_wait_status_ready(bank)) return nand_unlock(1);
|
|
return nand_unlock(0);
|
|
}
|
|
|
|
const struct nand_device_info_type* nand_get_device_type(uint32_t bank)
|
|
{
|
|
if (nand_type[bank] == 0xFFFFFFFF)
|
|
return (struct nand_device_info_type*)0;
|
|
return &nand_deviceinfotable[nand_type[bank]];
|
|
}
|
|
|
|
uint32_t nand_device_init(void)
|
|
{
|
|
mutex_init(&nand_mtx);
|
|
wakeup_init(&nand_wakeup);
|
|
mutex_init(&ecc_mtx);
|
|
wakeup_init(&ecc_wakeup);
|
|
|
|
uint32_t type;
|
|
uint32_t i, j;
|
|
if (!nand_powered) nand_power_up();
|
|
for (i = 0; i < 4; i++)
|
|
{
|
|
nand_tunk1[i] = 7;
|
|
nand_twp[i] = 7;
|
|
nand_tunk2[i] = 7;
|
|
nand_tunk3[i] = 7;
|
|
type = nand_get_chip_type(i);
|
|
nand_type[i] = 0xFFFFFFFF;
|
|
if (type == 0xFFFFFFFF) continue;
|
|
for (j = 0; ; j++)
|
|
{
|
|
if (j == ARRAYLEN(nand_deviceinfotable)) break;
|
|
else if (nand_deviceinfotable[j].id == type)
|
|
{
|
|
nand_type[i] = j;
|
|
break;
|
|
}
|
|
}
|
|
nand_tunk1[i] = nand_deviceinfotable[nand_type[i]].tunk1;
|
|
nand_twp[i] = nand_deviceinfotable[nand_type[i]].twp;
|
|
nand_tunk2[i] = nand_deviceinfotable[nand_type[i]].tunk2;
|
|
nand_tunk3[i] = nand_deviceinfotable[nand_type[i]].tunk3;
|
|
}
|
|
if (nand_type[0] == 0xFFFFFFFF) return 1;
|
|
return 0;
|
|
}
|