eac1ca22bd
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
840 lines
56 KiB
C
840 lines
56 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* stmp3600 version: 2.4.0
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* stmp3600 authors: Amaury Pouly
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_STMP3600_LRADC_H__
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#define __HEADERGEN_STMP3600_LRADC_H__
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#define HW_LRADC_CTRL0 HW(LRADC_CTRL0)
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#define HWA_LRADC_CTRL0 (0x80050000 + 0x0)
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#define HWT_LRADC_CTRL0 HWIO_32_RW
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#define HWN_LRADC_CTRL0 LRADC_CTRL0
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#define HWI_LRADC_CTRL0
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#define HW_LRADC_CTRL0_SET HW(LRADC_CTRL0_SET)
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#define HWA_LRADC_CTRL0_SET (HWA_LRADC_CTRL0 + 0x4)
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#define HWT_LRADC_CTRL0_SET HWIO_32_WO
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#define HWN_LRADC_CTRL0_SET LRADC_CTRL0
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#define HWI_LRADC_CTRL0_SET
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#define HW_LRADC_CTRL0_CLR HW(LRADC_CTRL0_CLR)
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#define HWA_LRADC_CTRL0_CLR (HWA_LRADC_CTRL0 + 0x8)
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#define HWT_LRADC_CTRL0_CLR HWIO_32_WO
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#define HWN_LRADC_CTRL0_CLR LRADC_CTRL0
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#define HWI_LRADC_CTRL0_CLR
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#define HW_LRADC_CTRL0_TOG HW(LRADC_CTRL0_TOG)
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#define HWA_LRADC_CTRL0_TOG (HWA_LRADC_CTRL0 + 0xc)
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#define HWT_LRADC_CTRL0_TOG HWIO_32_WO
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#define HWN_LRADC_CTRL0_TOG LRADC_CTRL0
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#define HWI_LRADC_CTRL0_TOG
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#define BP_LRADC_CTRL0_SFTRST 31
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#define BM_LRADC_CTRL0_SFTRST 0x80000000
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#define BF_LRADC_CTRL0_SFTRST(v) (((v) & 0x1) << 31)
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#define BFM_LRADC_CTRL0_SFTRST(v) BM_LRADC_CTRL0_SFTRST
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#define BF_LRADC_CTRL0_SFTRST_V(e) BF_LRADC_CTRL0_SFTRST(BV_LRADC_CTRL0_SFTRST__##e)
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#define BFM_LRADC_CTRL0_SFTRST_V(v) BM_LRADC_CTRL0_SFTRST
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#define BP_LRADC_CTRL0_CLKGATE 30
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#define BM_LRADC_CTRL0_CLKGATE 0x40000000
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#define BF_LRADC_CTRL0_CLKGATE(v) (((v) & 0x1) << 30)
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#define BFM_LRADC_CTRL0_CLKGATE(v) BM_LRADC_CTRL0_CLKGATE
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#define BF_LRADC_CTRL0_CLKGATE_V(e) BF_LRADC_CTRL0_CLKGATE(BV_LRADC_CTRL0_CLKGATE__##e)
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#define BFM_LRADC_CTRL0_CLKGATE_V(v) BM_LRADC_CTRL0_CLKGATE
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#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF 21
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#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x200000
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#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0
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#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1
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#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v) (((v) & 0x1) << 21)
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#define BFM_LRADC_CTRL0_ONCHIP_GROUNDREF(v) BM_LRADC_CTRL0_ONCHIP_GROUNDREF
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#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(e) BF_LRADC_CTRL0_ONCHIP_GROUNDREF(BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##e)
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#define BFM_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v) BM_LRADC_CTRL0_ONCHIP_GROUNDREF
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#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE 20
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#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x100000
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#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0
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#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1
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#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v) (((v) & 0x1) << 20)
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#define BFM_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v) BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE
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#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(e) BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##e)
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#define BFM_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE
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#define BP_LRADC_CTRL0_YMINUS_ENABLE 19
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#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x80000
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#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0
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#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1
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#define BF_LRADC_CTRL0_YMINUS_ENABLE(v) (((v) & 0x1) << 19)
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#define BFM_LRADC_CTRL0_YMINUS_ENABLE(v) BM_LRADC_CTRL0_YMINUS_ENABLE
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#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(e) BF_LRADC_CTRL0_YMINUS_ENABLE(BV_LRADC_CTRL0_YMINUS_ENABLE__##e)
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#define BFM_LRADC_CTRL0_YMINUS_ENABLE_V(v) BM_LRADC_CTRL0_YMINUS_ENABLE
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#define BP_LRADC_CTRL0_XMINUS_ENABLE 18
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#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x40000
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#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0
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#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1
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#define BF_LRADC_CTRL0_XMINUS_ENABLE(v) (((v) & 0x1) << 18)
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#define BFM_LRADC_CTRL0_XMINUS_ENABLE(v) BM_LRADC_CTRL0_XMINUS_ENABLE
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#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(e) BF_LRADC_CTRL0_XMINUS_ENABLE(BV_LRADC_CTRL0_XMINUS_ENABLE__##e)
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#define BFM_LRADC_CTRL0_XMINUS_ENABLE_V(v) BM_LRADC_CTRL0_XMINUS_ENABLE
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#define BP_LRADC_CTRL0_YPLUS_ENABLE 17
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#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x20000
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#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0
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#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1
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#define BF_LRADC_CTRL0_YPLUS_ENABLE(v) (((v) & 0x1) << 17)
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#define BFM_LRADC_CTRL0_YPLUS_ENABLE(v) BM_LRADC_CTRL0_YPLUS_ENABLE
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#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(e) BF_LRADC_CTRL0_YPLUS_ENABLE(BV_LRADC_CTRL0_YPLUS_ENABLE__##e)
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#define BFM_LRADC_CTRL0_YPLUS_ENABLE_V(v) BM_LRADC_CTRL0_YPLUS_ENABLE
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#define BP_LRADC_CTRL0_XPLUS_ENABLE 16
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#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x10000
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#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0
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#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1
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#define BF_LRADC_CTRL0_XPLUS_ENABLE(v) (((v) & 0x1) << 16)
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#define BFM_LRADC_CTRL0_XPLUS_ENABLE(v) BM_LRADC_CTRL0_XPLUS_ENABLE
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#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(e) BF_LRADC_CTRL0_XPLUS_ENABLE(BV_LRADC_CTRL0_XPLUS_ENABLE__##e)
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#define BFM_LRADC_CTRL0_XPLUS_ENABLE_V(v) BM_LRADC_CTRL0_XPLUS_ENABLE
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#define BP_LRADC_CTRL0_SCHEDULE 0
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#define BM_LRADC_CTRL0_SCHEDULE 0xff
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#define BF_LRADC_CTRL0_SCHEDULE(v) (((v) & 0xff) << 0)
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#define BFM_LRADC_CTRL0_SCHEDULE(v) BM_LRADC_CTRL0_SCHEDULE
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#define BF_LRADC_CTRL0_SCHEDULE_V(e) BF_LRADC_CTRL0_SCHEDULE(BV_LRADC_CTRL0_SCHEDULE__##e)
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#define BFM_LRADC_CTRL0_SCHEDULE_V(v) BM_LRADC_CTRL0_SCHEDULE
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#define HW_LRADC_CTRL1 HW(LRADC_CTRL1)
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#define HWA_LRADC_CTRL1 (0x80050000 + 0x10)
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#define HWT_LRADC_CTRL1 HWIO_32_RW
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#define HWN_LRADC_CTRL1 LRADC_CTRL1
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#define HWI_LRADC_CTRL1
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#define HW_LRADC_CTRL1_SET HW(LRADC_CTRL1_SET)
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#define HWA_LRADC_CTRL1_SET (HWA_LRADC_CTRL1 + 0x4)
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#define HWT_LRADC_CTRL1_SET HWIO_32_WO
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#define HWN_LRADC_CTRL1_SET LRADC_CTRL1
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#define HWI_LRADC_CTRL1_SET
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#define HW_LRADC_CTRL1_CLR HW(LRADC_CTRL1_CLR)
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#define HWA_LRADC_CTRL1_CLR (HWA_LRADC_CTRL1 + 0x8)
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#define HWT_LRADC_CTRL1_CLR HWIO_32_WO
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#define HWN_LRADC_CTRL1_CLR LRADC_CTRL1
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#define HWI_LRADC_CTRL1_CLR
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#define HW_LRADC_CTRL1_TOG HW(LRADC_CTRL1_TOG)
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#define HWA_LRADC_CTRL1_TOG (HWA_LRADC_CTRL1 + 0xc)
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#define HWT_LRADC_CTRL1_TOG HWIO_32_WO
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#define HWN_LRADC_CTRL1_TOG LRADC_CTRL1
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#define HWI_LRADC_CTRL1_TOG
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#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 24
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#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x1000000
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#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
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#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1
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#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v) (((v) & 0x1) << 24)
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#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v) BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN
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#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(e) BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##e)
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#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v) BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN
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#define BP_LRADC_CTRL1_LRADC7_IRQ_EN 23
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#define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x800000
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#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0
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#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1
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#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v) (((v) & 0x1) << 23)
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#define BFM_LRADC_CTRL1_LRADC7_IRQ_EN(v) BM_LRADC_CTRL1_LRADC7_IRQ_EN
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#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(e) BF_LRADC_CTRL1_LRADC7_IRQ_EN(BV_LRADC_CTRL1_LRADC7_IRQ_EN__##e)
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#define BFM_LRADC_CTRL1_LRADC7_IRQ_EN_V(v) BM_LRADC_CTRL1_LRADC7_IRQ_EN
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#define BP_LRADC_CTRL1_LRADC6_IRQ_EN 22
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#define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x400000
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#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0
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#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1
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#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v) (((v) & 0x1) << 22)
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#define BFM_LRADC_CTRL1_LRADC6_IRQ_EN(v) BM_LRADC_CTRL1_LRADC6_IRQ_EN
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#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(e) BF_LRADC_CTRL1_LRADC6_IRQ_EN(BV_LRADC_CTRL1_LRADC6_IRQ_EN__##e)
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#define BFM_LRADC_CTRL1_LRADC6_IRQ_EN_V(v) BM_LRADC_CTRL1_LRADC6_IRQ_EN
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#define BP_LRADC_CTRL1_LRADC5_IRQ_EN 21
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#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x200000
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#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0
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#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1
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#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v) (((v) & 0x1) << 21)
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#define BFM_LRADC_CTRL1_LRADC5_IRQ_EN(v) BM_LRADC_CTRL1_LRADC5_IRQ_EN
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#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(e) BF_LRADC_CTRL1_LRADC5_IRQ_EN(BV_LRADC_CTRL1_LRADC5_IRQ_EN__##e)
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#define BFM_LRADC_CTRL1_LRADC5_IRQ_EN_V(v) BM_LRADC_CTRL1_LRADC5_IRQ_EN
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#define BP_LRADC_CTRL1_LRADC4_IRQ_EN 20
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#define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x100000
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#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0
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#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1
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#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v) (((v) & 0x1) << 20)
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#define BFM_LRADC_CTRL1_LRADC4_IRQ_EN(v) BM_LRADC_CTRL1_LRADC4_IRQ_EN
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#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(e) BF_LRADC_CTRL1_LRADC4_IRQ_EN(BV_LRADC_CTRL1_LRADC4_IRQ_EN__##e)
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#define BFM_LRADC_CTRL1_LRADC4_IRQ_EN_V(v) BM_LRADC_CTRL1_LRADC4_IRQ_EN
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#define BP_LRADC_CTRL1_LRADC3_IRQ_EN 19
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#define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x80000
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#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0
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#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1
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#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v) (((v) & 0x1) << 19)
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#define BFM_LRADC_CTRL1_LRADC3_IRQ_EN(v) BM_LRADC_CTRL1_LRADC3_IRQ_EN
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#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(e) BF_LRADC_CTRL1_LRADC3_IRQ_EN(BV_LRADC_CTRL1_LRADC3_IRQ_EN__##e)
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#define BFM_LRADC_CTRL1_LRADC3_IRQ_EN_V(v) BM_LRADC_CTRL1_LRADC3_IRQ_EN
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#define BP_LRADC_CTRL1_LRADC2_IRQ_EN 18
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#define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x40000
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#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0
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#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1
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#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v) (((v) & 0x1) << 18)
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#define BFM_LRADC_CTRL1_LRADC2_IRQ_EN(v) BM_LRADC_CTRL1_LRADC2_IRQ_EN
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#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(e) BF_LRADC_CTRL1_LRADC2_IRQ_EN(BV_LRADC_CTRL1_LRADC2_IRQ_EN__##e)
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#define BFM_LRADC_CTRL1_LRADC2_IRQ_EN_V(v) BM_LRADC_CTRL1_LRADC2_IRQ_EN
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#define BP_LRADC_CTRL1_LRADC1_IRQ_EN 17
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#define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x20000
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#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0
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#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1
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#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v) (((v) & 0x1) << 17)
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#define BFM_LRADC_CTRL1_LRADC1_IRQ_EN(v) BM_LRADC_CTRL1_LRADC1_IRQ_EN
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#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(e) BF_LRADC_CTRL1_LRADC1_IRQ_EN(BV_LRADC_CTRL1_LRADC1_IRQ_EN__##e)
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#define BFM_LRADC_CTRL1_LRADC1_IRQ_EN_V(v) BM_LRADC_CTRL1_LRADC1_IRQ_EN
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#define BP_LRADC_CTRL1_LRADC0_IRQ_EN 16
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#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x10000
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#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0
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#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1
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#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v) (((v) & 0x1) << 16)
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#define BFM_LRADC_CTRL1_LRADC0_IRQ_EN(v) BM_LRADC_CTRL1_LRADC0_IRQ_EN
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#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(e) BF_LRADC_CTRL1_LRADC0_IRQ_EN(BV_LRADC_CTRL1_LRADC0_IRQ_EN__##e)
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#define BFM_LRADC_CTRL1_LRADC0_IRQ_EN_V(v) BM_LRADC_CTRL1_LRADC0_IRQ_EN
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#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ 8
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#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x100
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#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0
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#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1
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#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v) (((v) & 0x1) << 8)
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#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ(v) BM_LRADC_CTRL1_TOUCH_DETECT_IRQ
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#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(e) BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##e)
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#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v) BM_LRADC_CTRL1_TOUCH_DETECT_IRQ
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#define BP_LRADC_CTRL1_LRADC7_IRQ 7
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#define BM_LRADC_CTRL1_LRADC7_IRQ 0x80
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#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0
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#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1
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#define BF_LRADC_CTRL1_LRADC7_IRQ(v) (((v) & 0x1) << 7)
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#define BFM_LRADC_CTRL1_LRADC7_IRQ(v) BM_LRADC_CTRL1_LRADC7_IRQ
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#define BF_LRADC_CTRL1_LRADC7_IRQ_V(e) BF_LRADC_CTRL1_LRADC7_IRQ(BV_LRADC_CTRL1_LRADC7_IRQ__##e)
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#define BFM_LRADC_CTRL1_LRADC7_IRQ_V(v) BM_LRADC_CTRL1_LRADC7_IRQ
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#define BP_LRADC_CTRL1_LRADC6_IRQ 6
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#define BM_LRADC_CTRL1_LRADC6_IRQ 0x40
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#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0
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#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1
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#define BF_LRADC_CTRL1_LRADC6_IRQ(v) (((v) & 0x1) << 6)
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#define BFM_LRADC_CTRL1_LRADC6_IRQ(v) BM_LRADC_CTRL1_LRADC6_IRQ
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#define BF_LRADC_CTRL1_LRADC6_IRQ_V(e) BF_LRADC_CTRL1_LRADC6_IRQ(BV_LRADC_CTRL1_LRADC6_IRQ__##e)
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#define BFM_LRADC_CTRL1_LRADC6_IRQ_V(v) BM_LRADC_CTRL1_LRADC6_IRQ
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#define BP_LRADC_CTRL1_LRADC5_IRQ 5
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#define BM_LRADC_CTRL1_LRADC5_IRQ 0x20
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#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0
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#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1
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#define BF_LRADC_CTRL1_LRADC5_IRQ(v) (((v) & 0x1) << 5)
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#define BFM_LRADC_CTRL1_LRADC5_IRQ(v) BM_LRADC_CTRL1_LRADC5_IRQ
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#define BF_LRADC_CTRL1_LRADC5_IRQ_V(e) BF_LRADC_CTRL1_LRADC5_IRQ(BV_LRADC_CTRL1_LRADC5_IRQ__##e)
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#define BFM_LRADC_CTRL1_LRADC5_IRQ_V(v) BM_LRADC_CTRL1_LRADC5_IRQ
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#define BP_LRADC_CTRL1_LRADC4_IRQ 4
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#define BM_LRADC_CTRL1_LRADC4_IRQ 0x10
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#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0
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#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1
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#define BF_LRADC_CTRL1_LRADC4_IRQ(v) (((v) & 0x1) << 4)
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#define BFM_LRADC_CTRL1_LRADC4_IRQ(v) BM_LRADC_CTRL1_LRADC4_IRQ
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#define BF_LRADC_CTRL1_LRADC4_IRQ_V(e) BF_LRADC_CTRL1_LRADC4_IRQ(BV_LRADC_CTRL1_LRADC4_IRQ__##e)
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#define BFM_LRADC_CTRL1_LRADC4_IRQ_V(v) BM_LRADC_CTRL1_LRADC4_IRQ
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#define BP_LRADC_CTRL1_LRADC3_IRQ 3
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#define BM_LRADC_CTRL1_LRADC3_IRQ 0x8
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#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0
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#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1
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#define BF_LRADC_CTRL1_LRADC3_IRQ(v) (((v) & 0x1) << 3)
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#define BFM_LRADC_CTRL1_LRADC3_IRQ(v) BM_LRADC_CTRL1_LRADC3_IRQ
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#define BF_LRADC_CTRL1_LRADC3_IRQ_V(e) BF_LRADC_CTRL1_LRADC3_IRQ(BV_LRADC_CTRL1_LRADC3_IRQ__##e)
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#define BFM_LRADC_CTRL1_LRADC3_IRQ_V(v) BM_LRADC_CTRL1_LRADC3_IRQ
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#define BP_LRADC_CTRL1_LRADC2_IRQ 2
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#define BM_LRADC_CTRL1_LRADC2_IRQ 0x4
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#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0
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#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1
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#define BF_LRADC_CTRL1_LRADC2_IRQ(v) (((v) & 0x1) << 2)
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#define BFM_LRADC_CTRL1_LRADC2_IRQ(v) BM_LRADC_CTRL1_LRADC2_IRQ
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#define BF_LRADC_CTRL1_LRADC2_IRQ_V(e) BF_LRADC_CTRL1_LRADC2_IRQ(BV_LRADC_CTRL1_LRADC2_IRQ__##e)
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#define BFM_LRADC_CTRL1_LRADC2_IRQ_V(v) BM_LRADC_CTRL1_LRADC2_IRQ
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#define BP_LRADC_CTRL1_LRADC1_IRQ 1
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#define BM_LRADC_CTRL1_LRADC1_IRQ 0x2
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#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0
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#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1
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#define BF_LRADC_CTRL1_LRADC1_IRQ(v) (((v) & 0x1) << 1)
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#define BFM_LRADC_CTRL1_LRADC1_IRQ(v) BM_LRADC_CTRL1_LRADC1_IRQ
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#define BF_LRADC_CTRL1_LRADC1_IRQ_V(e) BF_LRADC_CTRL1_LRADC1_IRQ(BV_LRADC_CTRL1_LRADC1_IRQ__##e)
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#define BFM_LRADC_CTRL1_LRADC1_IRQ_V(v) BM_LRADC_CTRL1_LRADC1_IRQ
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#define BP_LRADC_CTRL1_LRADC0_IRQ 0
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#define BM_LRADC_CTRL1_LRADC0_IRQ 0x1
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#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0
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#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1
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#define BF_LRADC_CTRL1_LRADC0_IRQ(v) (((v) & 0x1) << 0)
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#define BFM_LRADC_CTRL1_LRADC0_IRQ(v) BM_LRADC_CTRL1_LRADC0_IRQ
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#define BF_LRADC_CTRL1_LRADC0_IRQ_V(e) BF_LRADC_CTRL1_LRADC0_IRQ(BV_LRADC_CTRL1_LRADC0_IRQ__##e)
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#define BFM_LRADC_CTRL1_LRADC0_IRQ_V(v) BM_LRADC_CTRL1_LRADC0_IRQ
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#define HW_LRADC_CTRL2 HW(LRADC_CTRL2)
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#define HWA_LRADC_CTRL2 (0x80050000 + 0x20)
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#define HWT_LRADC_CTRL2 HWIO_32_RW
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#define HWN_LRADC_CTRL2 LRADC_CTRL2
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#define HWI_LRADC_CTRL2
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#define HW_LRADC_CTRL2_SET HW(LRADC_CTRL2_SET)
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#define HWA_LRADC_CTRL2_SET (HWA_LRADC_CTRL2 + 0x4)
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#define HWT_LRADC_CTRL2_SET HWIO_32_WO
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#define HWN_LRADC_CTRL2_SET LRADC_CTRL2
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#define HWI_LRADC_CTRL2_SET
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#define HW_LRADC_CTRL2_CLR HW(LRADC_CTRL2_CLR)
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#define HWA_LRADC_CTRL2_CLR (HWA_LRADC_CTRL2 + 0x8)
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#define HWT_LRADC_CTRL2_CLR HWIO_32_WO
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#define HWN_LRADC_CTRL2_CLR LRADC_CTRL2
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#define HWI_LRADC_CTRL2_CLR
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#define HW_LRADC_CTRL2_TOG HW(LRADC_CTRL2_TOG)
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#define HWA_LRADC_CTRL2_TOG (HWA_LRADC_CTRL2 + 0xc)
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#define HWT_LRADC_CTRL2_TOG HWIO_32_WO
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#define HWN_LRADC_CTRL2_TOG LRADC_CTRL2
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#define HWI_LRADC_CTRL2_TOG
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#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
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#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xff000000
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#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) (((v) & 0xff) << 24)
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#define BFM_LRADC_CTRL2_DIVIDE_BY_TWO(v) BM_LRADC_CTRL2_DIVIDE_BY_TWO
|
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#define BF_LRADC_CTRL2_DIVIDE_BY_TWO_V(e) BF_LRADC_CTRL2_DIVIDE_BY_TWO(BV_LRADC_CTRL2_DIVIDE_BY_TWO__##e)
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#define BFM_LRADC_CTRL2_DIVIDE_BY_TWO_V(v) BM_LRADC_CTRL2_DIVIDE_BY_TWO
|
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#define BP_LRADC_CTRL2_LRADC6SELECT 20
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#define BM_LRADC_CTRL2_LRADC6SELECT 0xf00000
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL0 0x0
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL1 0x1
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL2 0x2
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL3 0x3
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL4 0x4
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL5 0x5
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL6 0x6
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL7 0x7
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL8 0x8
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL9 0x9
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL10 0xa
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL11 0xb
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL12 0xc
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL13 0xd
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL14 0xe
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#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL15 0xf
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#define BF_LRADC_CTRL2_LRADC6SELECT(v) (((v) & 0xf) << 20)
|
|
#define BFM_LRADC_CTRL2_LRADC6SELECT(v) BM_LRADC_CTRL2_LRADC6SELECT
|
|
#define BF_LRADC_CTRL2_LRADC6SELECT_V(e) BF_LRADC_CTRL2_LRADC6SELECT(BV_LRADC_CTRL2_LRADC6SELECT__##e)
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|
#define BFM_LRADC_CTRL2_LRADC6SELECT_V(v) BM_LRADC_CTRL2_LRADC6SELECT
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#define BP_LRADC_CTRL2_LRADC7SELECT 16
|
|
#define BM_LRADC_CTRL2_LRADC7SELECT 0xf0000
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|
#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL0 0x0
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL1 0x1
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL2 0x2
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|
#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL3 0x3
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL4 0x4
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL5 0x5
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL6 0x6
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL7 0x7
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|
#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL8 0x8
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|
#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL9 0x9
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL10 0xa
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|
#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL11 0xb
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|
#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL12 0xc
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL13 0xd
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL14 0xe
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#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL15 0xf
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#define BF_LRADC_CTRL2_LRADC7SELECT(v) (((v) & 0xf) << 16)
|
|
#define BFM_LRADC_CTRL2_LRADC7SELECT(v) BM_LRADC_CTRL2_LRADC7SELECT
|
|
#define BF_LRADC_CTRL2_LRADC7SELECT_V(e) BF_LRADC_CTRL2_LRADC7SELECT(BV_LRADC_CTRL2_LRADC7SELECT__##e)
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|
#define BFM_LRADC_CTRL2_LRADC7SELECT_V(v) BM_LRADC_CTRL2_LRADC7SELECT
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|
#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 9
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|
#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x200
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|
#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0
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#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1
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|
#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v) (((v) & 0x1) << 9)
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#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v) BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1
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|
#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(e) BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##e)
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|
#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v) BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1
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#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 8
|
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#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x100
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|
#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0
|
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#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1
|
|
#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v) (((v) & 0x1) << 8)
|
|
#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v) BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0
|
|
#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(e) BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##e)
|
|
#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v) BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0
|
|
#define BP_LRADC_CTRL2_TEMP_ISRC1 4
|
|
#define BM_LRADC_CTRL2_TEMP_ISRC1 0xf0
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xf
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xe
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xd
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xc
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xb
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xa
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0
|
|
#define BF_LRADC_CTRL2_TEMP_ISRC1(v) (((v) & 0xf) << 4)
|
|
#define BFM_LRADC_CTRL2_TEMP_ISRC1(v) BM_LRADC_CTRL2_TEMP_ISRC1
|
|
#define BF_LRADC_CTRL2_TEMP_ISRC1_V(e) BF_LRADC_CTRL2_TEMP_ISRC1(BV_LRADC_CTRL2_TEMP_ISRC1__##e)
|
|
#define BFM_LRADC_CTRL2_TEMP_ISRC1_V(v) BM_LRADC_CTRL2_TEMP_ISRC1
|
|
#define BP_LRADC_CTRL2_TEMP_ISRC0 0
|
|
#define BM_LRADC_CTRL2_TEMP_ISRC0 0xf
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xf
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xe
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xd
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xc
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xb
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xa
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1
|
|
#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0
|
|
#define BF_LRADC_CTRL2_TEMP_ISRC0(v) (((v) & 0xf) << 0)
|
|
#define BFM_LRADC_CTRL2_TEMP_ISRC0(v) BM_LRADC_CTRL2_TEMP_ISRC0
|
|
#define BF_LRADC_CTRL2_TEMP_ISRC0_V(e) BF_LRADC_CTRL2_TEMP_ISRC0(BV_LRADC_CTRL2_TEMP_ISRC0__##e)
|
|
#define BFM_LRADC_CTRL2_TEMP_ISRC0_V(v) BM_LRADC_CTRL2_TEMP_ISRC0
|
|
|
|
#define HW_LRADC_CTRL3 HW(LRADC_CTRL3)
|
|
#define HWA_LRADC_CTRL3 (0x80050000 + 0x30)
|
|
#define HWT_LRADC_CTRL3 HWIO_32_RW
|
|
#define HWN_LRADC_CTRL3 LRADC_CTRL3
|
|
#define HWI_LRADC_CTRL3
|
|
#define HW_LRADC_CTRL3_SET HW(LRADC_CTRL3_SET)
|
|
#define HWA_LRADC_CTRL3_SET (HWA_LRADC_CTRL3 + 0x4)
|
|
#define HWT_LRADC_CTRL3_SET HWIO_32_WO
|
|
#define HWN_LRADC_CTRL3_SET LRADC_CTRL3
|
|
#define HWI_LRADC_CTRL3_SET
|
|
#define HW_LRADC_CTRL3_CLR HW(LRADC_CTRL3_CLR)
|
|
#define HWA_LRADC_CTRL3_CLR (HWA_LRADC_CTRL3 + 0x8)
|
|
#define HWT_LRADC_CTRL3_CLR HWIO_32_WO
|
|
#define HWN_LRADC_CTRL3_CLR LRADC_CTRL3
|
|
#define HWI_LRADC_CTRL3_CLR
|
|
#define HW_LRADC_CTRL3_TOG HW(LRADC_CTRL3_TOG)
|
|
#define HWA_LRADC_CTRL3_TOG (HWA_LRADC_CTRL3 + 0xc)
|
|
#define HWT_LRADC_CTRL3_TOG HWIO_32_WO
|
|
#define HWN_LRADC_CTRL3_TOG LRADC_CTRL3
|
|
#define HWI_LRADC_CTRL3_TOG
|
|
#define BP_LRADC_CTRL3_DISCARD 24
|
|
#define BM_LRADC_CTRL3_DISCARD 0x3000000
|
|
#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1
|
|
#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2
|
|
#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3
|
|
#define BF_LRADC_CTRL3_DISCARD(v) (((v) & 0x3) << 24)
|
|
#define BFM_LRADC_CTRL3_DISCARD(v) BM_LRADC_CTRL3_DISCARD
|
|
#define BF_LRADC_CTRL3_DISCARD_V(e) BF_LRADC_CTRL3_DISCARD(BV_LRADC_CTRL3_DISCARD__##e)
|
|
#define BFM_LRADC_CTRL3_DISCARD_V(v) BM_LRADC_CTRL3_DISCARD
|
|
#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP 23
|
|
#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x800000
|
|
#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0
|
|
#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1
|
|
#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v) (((v) & 0x1) << 23)
|
|
#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWUP(v) BM_LRADC_CTRL3_FORCE_ANALOG_PWUP
|
|
#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(e) BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##e)
|
|
#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v) BM_LRADC_CTRL3_FORCE_ANALOG_PWUP
|
|
#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN 22
|
|
#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x400000
|
|
#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0
|
|
#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1
|
|
#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v) (((v) & 0x1) << 22)
|
|
#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWDN(v) BM_LRADC_CTRL3_FORCE_ANALOG_PWDN
|
|
#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(e) BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##e)
|
|
#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v) BM_LRADC_CTRL3_FORCE_ANALOG_PWDN
|
|
#define BP_LRADC_CTRL3_FORCE_PWD40UA_PWUP 21
|
|
#define BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP 0x200000
|
|
#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__OFF 0x0
|
|
#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__ON 0x1
|
|
#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP(v) (((v) & 0x1) << 21)
|
|
#define BFM_LRADC_CTRL3_FORCE_PWD40UA_PWUP(v) BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP
|
|
#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP_V(e) BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP(BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__##e)
|
|
#define BFM_LRADC_CTRL3_FORCE_PWD40UA_PWUP_V(v) BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP
|
|
#define BP_LRADC_CTRL3_FORCE_PWD40UA_PWDN 20
|
|
#define BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN 0x100000
|
|
#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__ON 0x0
|
|
#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__OFF 0x1
|
|
#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN(v) (((v) & 0x1) << 20)
|
|
#define BFM_LRADC_CTRL3_FORCE_PWD40UA_PWDN(v) BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN
|
|
#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN_V(e) BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN(BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__##e)
|
|
#define BFM_LRADC_CTRL3_FORCE_PWD40UA_PWDN_V(v) BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN
|
|
#define BP_LRADC_CTRL3_VDD_FILTER 16
|
|
#define BM_LRADC_CTRL3_VDD_FILTER 0x30000
|
|
#define BV_LRADC_CTRL3_VDD_FILTER__0OHMS 0x0
|
|
#define BV_LRADC_CTRL3_VDD_FILTER__100OHMS 0x1
|
|
#define BV_LRADC_CTRL3_VDD_FILTER__250OHMS 0x2
|
|
#define BV_LRADC_CTRL3_VDD_FILTER__5000OHMS 0x3
|
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#define BF_LRADC_CTRL3_VDD_FILTER(v) (((v) & 0x3) << 16)
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#define BFM_LRADC_CTRL3_VDD_FILTER(v) BM_LRADC_CTRL3_VDD_FILTER
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#define BF_LRADC_CTRL3_VDD_FILTER_V(e) BF_LRADC_CTRL3_VDD_FILTER(BV_LRADC_CTRL3_VDD_FILTER__##e)
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#define BFM_LRADC_CTRL3_VDD_FILTER_V(v) BM_LRADC_CTRL3_VDD_FILTER
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#define BP_LRADC_CTRL3_ADD_CAP2INPUTS 12
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#define BM_LRADC_CTRL3_ADD_CAP2INPUTS 0x3000
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#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0PF 0x0
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#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0_5PF 0x1
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#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__1_0PF 0x2
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#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__2_5PF 0x3
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#define BF_LRADC_CTRL3_ADD_CAP2INPUTS(v) (((v) & 0x3) << 12)
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#define BFM_LRADC_CTRL3_ADD_CAP2INPUTS(v) BM_LRADC_CTRL3_ADD_CAP2INPUTS
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#define BF_LRADC_CTRL3_ADD_CAP2INPUTS_V(e) BF_LRADC_CTRL3_ADD_CAP2INPUTS(BV_LRADC_CTRL3_ADD_CAP2INPUTS__##e)
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#define BFM_LRADC_CTRL3_ADD_CAP2INPUTS_V(v) BM_LRADC_CTRL3_ADD_CAP2INPUTS
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#define BP_LRADC_CTRL3_CYCLE_TIME 8
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#define BM_LRADC_CTRL3_CYCLE_TIME 0x300
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#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0
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#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1
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#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2
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#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3
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#define BF_LRADC_CTRL3_CYCLE_TIME(v) (((v) & 0x3) << 8)
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#define BFM_LRADC_CTRL3_CYCLE_TIME(v) BM_LRADC_CTRL3_CYCLE_TIME
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#define BF_LRADC_CTRL3_CYCLE_TIME_V(e) BF_LRADC_CTRL3_CYCLE_TIME(BV_LRADC_CTRL3_CYCLE_TIME__##e)
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#define BFM_LRADC_CTRL3_CYCLE_TIME_V(v) BM_LRADC_CTRL3_CYCLE_TIME
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#define BP_LRADC_CTRL3_HIGH_TIME 4
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#define BM_LRADC_CTRL3_HIGH_TIME 0x30
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#define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0
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#define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1
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#define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2
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#define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3
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#define BF_LRADC_CTRL3_HIGH_TIME(v) (((v) & 0x3) << 4)
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#define BFM_LRADC_CTRL3_HIGH_TIME(v) BM_LRADC_CTRL3_HIGH_TIME
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#define BF_LRADC_CTRL3_HIGH_TIME_V(e) BF_LRADC_CTRL3_HIGH_TIME(BV_LRADC_CTRL3_HIGH_TIME__##e)
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#define BFM_LRADC_CTRL3_HIGH_TIME_V(v) BM_LRADC_CTRL3_HIGH_TIME
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#define BP_LRADC_CTRL3_REMOVE_CFILT 3
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#define BM_LRADC_CTRL3_REMOVE_CFILT 0x8
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#define BV_LRADC_CTRL3_REMOVE_CFILT__OFF 0x0
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#define BV_LRADC_CTRL3_REMOVE_CFILT__ON 0x1
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#define BF_LRADC_CTRL3_REMOVE_CFILT(v) (((v) & 0x1) << 3)
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#define BFM_LRADC_CTRL3_REMOVE_CFILT(v) BM_LRADC_CTRL3_REMOVE_CFILT
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#define BF_LRADC_CTRL3_REMOVE_CFILT_V(e) BF_LRADC_CTRL3_REMOVE_CFILT(BV_LRADC_CTRL3_REMOVE_CFILT__##e)
|
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#define BFM_LRADC_CTRL3_REMOVE_CFILT_V(v) BM_LRADC_CTRL3_REMOVE_CFILT
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#define BP_LRADC_CTRL3_SHORT_RFILT 2
|
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#define BM_LRADC_CTRL3_SHORT_RFILT 0x4
|
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#define BV_LRADC_CTRL3_SHORT_RFILT__OFF 0x0
|
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#define BV_LRADC_CTRL3_SHORT_RFILT__ON 0x1
|
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#define BF_LRADC_CTRL3_SHORT_RFILT(v) (((v) & 0x1) << 2)
|
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#define BFM_LRADC_CTRL3_SHORT_RFILT(v) BM_LRADC_CTRL3_SHORT_RFILT
|
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#define BF_LRADC_CTRL3_SHORT_RFILT_V(e) BF_LRADC_CTRL3_SHORT_RFILT(BV_LRADC_CTRL3_SHORT_RFILT__##e)
|
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#define BFM_LRADC_CTRL3_SHORT_RFILT_V(v) BM_LRADC_CTRL3_SHORT_RFILT
|
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#define BP_LRADC_CTRL3_DELAY_CLOCK 1
|
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#define BM_LRADC_CTRL3_DELAY_CLOCK 0x2
|
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#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0
|
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#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1
|
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#define BF_LRADC_CTRL3_DELAY_CLOCK(v) (((v) & 0x1) << 1)
|
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#define BFM_LRADC_CTRL3_DELAY_CLOCK(v) BM_LRADC_CTRL3_DELAY_CLOCK
|
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#define BF_LRADC_CTRL3_DELAY_CLOCK_V(e) BF_LRADC_CTRL3_DELAY_CLOCK(BV_LRADC_CTRL3_DELAY_CLOCK__##e)
|
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#define BFM_LRADC_CTRL3_DELAY_CLOCK_V(v) BM_LRADC_CTRL3_DELAY_CLOCK
|
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#define BP_LRADC_CTRL3_INVERT_CLOCK 0
|
|
#define BM_LRADC_CTRL3_INVERT_CLOCK 0x1
|
|
#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0
|
|
#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1
|
|
#define BF_LRADC_CTRL3_INVERT_CLOCK(v) (((v) & 0x1) << 0)
|
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#define BFM_LRADC_CTRL3_INVERT_CLOCK(v) BM_LRADC_CTRL3_INVERT_CLOCK
|
|
#define BF_LRADC_CTRL3_INVERT_CLOCK_V(e) BF_LRADC_CTRL3_INVERT_CLOCK(BV_LRADC_CTRL3_INVERT_CLOCK__##e)
|
|
#define BFM_LRADC_CTRL3_INVERT_CLOCK_V(v) BM_LRADC_CTRL3_INVERT_CLOCK
|
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|
|
#define HW_LRADC_STATUS HW(LRADC_STATUS)
|
|
#define HWA_LRADC_STATUS (0x80050000 + 0x40)
|
|
#define HWT_LRADC_STATUS HWIO_32_RW
|
|
#define HWN_LRADC_STATUS LRADC_STATUS
|
|
#define HWI_LRADC_STATUS
|
|
#define BP_LRADC_STATUS_TEMP1_PRESENT 26
|
|
#define BM_LRADC_STATUS_TEMP1_PRESENT 0x4000000
|
|
#define BF_LRADC_STATUS_TEMP1_PRESENT(v) (((v) & 0x1) << 26)
|
|
#define BFM_LRADC_STATUS_TEMP1_PRESENT(v) BM_LRADC_STATUS_TEMP1_PRESENT
|
|
#define BF_LRADC_STATUS_TEMP1_PRESENT_V(e) BF_LRADC_STATUS_TEMP1_PRESENT(BV_LRADC_STATUS_TEMP1_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_TEMP1_PRESENT_V(v) BM_LRADC_STATUS_TEMP1_PRESENT
|
|
#define BP_LRADC_STATUS_TEMP0_PRESENT 25
|
|
#define BM_LRADC_STATUS_TEMP0_PRESENT 0x2000000
|
|
#define BF_LRADC_STATUS_TEMP0_PRESENT(v) (((v) & 0x1) << 25)
|
|
#define BFM_LRADC_STATUS_TEMP0_PRESENT(v) BM_LRADC_STATUS_TEMP0_PRESENT
|
|
#define BF_LRADC_STATUS_TEMP0_PRESENT_V(e) BF_LRADC_STATUS_TEMP0_PRESENT(BV_LRADC_STATUS_TEMP0_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_TEMP0_PRESENT_V(v) BM_LRADC_STATUS_TEMP0_PRESENT
|
|
#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT 24
|
|
#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x1000000
|
|
#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v) (((v) & 0x1) << 24)
|
|
#define BFM_LRADC_STATUS_TOUCH_PANEL_PRESENT(v) BM_LRADC_STATUS_TOUCH_PANEL_PRESENT
|
|
#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT_V(e) BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(BV_LRADC_STATUS_TOUCH_PANEL_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_TOUCH_PANEL_PRESENT_V(v) BM_LRADC_STATUS_TOUCH_PANEL_PRESENT
|
|
#define BP_LRADC_STATUS_CHANNEL7_PRESENT 23
|
|
#define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x800000
|
|
#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v) (((v) & 0x1) << 23)
|
|
#define BFM_LRADC_STATUS_CHANNEL7_PRESENT(v) BM_LRADC_STATUS_CHANNEL7_PRESENT
|
|
#define BF_LRADC_STATUS_CHANNEL7_PRESENT_V(e) BF_LRADC_STATUS_CHANNEL7_PRESENT(BV_LRADC_STATUS_CHANNEL7_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_CHANNEL7_PRESENT_V(v) BM_LRADC_STATUS_CHANNEL7_PRESENT
|
|
#define BP_LRADC_STATUS_CHANNEL6_PRESENT 22
|
|
#define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x400000
|
|
#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v) (((v) & 0x1) << 22)
|
|
#define BFM_LRADC_STATUS_CHANNEL6_PRESENT(v) BM_LRADC_STATUS_CHANNEL6_PRESENT
|
|
#define BF_LRADC_STATUS_CHANNEL6_PRESENT_V(e) BF_LRADC_STATUS_CHANNEL6_PRESENT(BV_LRADC_STATUS_CHANNEL6_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_CHANNEL6_PRESENT_V(v) BM_LRADC_STATUS_CHANNEL6_PRESENT
|
|
#define BP_LRADC_STATUS_CHANNEL5_PRESENT 21
|
|
#define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x200000
|
|
#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v) (((v) & 0x1) << 21)
|
|
#define BFM_LRADC_STATUS_CHANNEL5_PRESENT(v) BM_LRADC_STATUS_CHANNEL5_PRESENT
|
|
#define BF_LRADC_STATUS_CHANNEL5_PRESENT_V(e) BF_LRADC_STATUS_CHANNEL5_PRESENT(BV_LRADC_STATUS_CHANNEL5_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_CHANNEL5_PRESENT_V(v) BM_LRADC_STATUS_CHANNEL5_PRESENT
|
|
#define BP_LRADC_STATUS_CHANNEL4_PRESENT 20
|
|
#define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x100000
|
|
#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v) (((v) & 0x1) << 20)
|
|
#define BFM_LRADC_STATUS_CHANNEL4_PRESENT(v) BM_LRADC_STATUS_CHANNEL4_PRESENT
|
|
#define BF_LRADC_STATUS_CHANNEL4_PRESENT_V(e) BF_LRADC_STATUS_CHANNEL4_PRESENT(BV_LRADC_STATUS_CHANNEL4_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_CHANNEL4_PRESENT_V(v) BM_LRADC_STATUS_CHANNEL4_PRESENT
|
|
#define BP_LRADC_STATUS_CHANNEL3_PRESENT 19
|
|
#define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x80000
|
|
#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v) (((v) & 0x1) << 19)
|
|
#define BFM_LRADC_STATUS_CHANNEL3_PRESENT(v) BM_LRADC_STATUS_CHANNEL3_PRESENT
|
|
#define BF_LRADC_STATUS_CHANNEL3_PRESENT_V(e) BF_LRADC_STATUS_CHANNEL3_PRESENT(BV_LRADC_STATUS_CHANNEL3_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_CHANNEL3_PRESENT_V(v) BM_LRADC_STATUS_CHANNEL3_PRESENT
|
|
#define BP_LRADC_STATUS_CHANNEL2_PRESENT 18
|
|
#define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x40000
|
|
#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v) (((v) & 0x1) << 18)
|
|
#define BFM_LRADC_STATUS_CHANNEL2_PRESENT(v) BM_LRADC_STATUS_CHANNEL2_PRESENT
|
|
#define BF_LRADC_STATUS_CHANNEL2_PRESENT_V(e) BF_LRADC_STATUS_CHANNEL2_PRESENT(BV_LRADC_STATUS_CHANNEL2_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_CHANNEL2_PRESENT_V(v) BM_LRADC_STATUS_CHANNEL2_PRESENT
|
|
#define BP_LRADC_STATUS_CHANNEL1_PRESENT 17
|
|
#define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x20000
|
|
#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v) (((v) & 0x1) << 17)
|
|
#define BFM_LRADC_STATUS_CHANNEL1_PRESENT(v) BM_LRADC_STATUS_CHANNEL1_PRESENT
|
|
#define BF_LRADC_STATUS_CHANNEL1_PRESENT_V(e) BF_LRADC_STATUS_CHANNEL1_PRESENT(BV_LRADC_STATUS_CHANNEL1_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_CHANNEL1_PRESENT_V(v) BM_LRADC_STATUS_CHANNEL1_PRESENT
|
|
#define BP_LRADC_STATUS_CHANNEL0_PRESENT 16
|
|
#define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x10000
|
|
#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v) (((v) & 0x1) << 16)
|
|
#define BFM_LRADC_STATUS_CHANNEL0_PRESENT(v) BM_LRADC_STATUS_CHANNEL0_PRESENT
|
|
#define BF_LRADC_STATUS_CHANNEL0_PRESENT_V(e) BF_LRADC_STATUS_CHANNEL0_PRESENT(BV_LRADC_STATUS_CHANNEL0_PRESENT__##e)
|
|
#define BFM_LRADC_STATUS_CHANNEL0_PRESENT_V(v) BM_LRADC_STATUS_CHANNEL0_PRESENT
|
|
#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
|
|
#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x1
|
|
#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0
|
|
#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1
|
|
#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v) (((v) & 0x1) << 0)
|
|
#define BFM_LRADC_STATUS_TOUCH_DETECT_RAW(v) BM_LRADC_STATUS_TOUCH_DETECT_RAW
|
|
#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(e) BF_LRADC_STATUS_TOUCH_DETECT_RAW(BV_LRADC_STATUS_TOUCH_DETECT_RAW__##e)
|
|
#define BFM_LRADC_STATUS_TOUCH_DETECT_RAW_V(v) BM_LRADC_STATUS_TOUCH_DETECT_RAW
|
|
|
|
#define HW_LRADC_DEBUG0 HW(LRADC_DEBUG0)
|
|
#define HWA_LRADC_DEBUG0 (0x80050000 + 0x110)
|
|
#define HWT_LRADC_DEBUG0 HWIO_32_RW
|
|
#define HWN_LRADC_DEBUG0 LRADC_DEBUG0
|
|
#define HWI_LRADC_DEBUG0
|
|
#define BP_LRADC_DEBUG0_READONLY 16
|
|
#define BM_LRADC_DEBUG0_READONLY 0xffff0000
|
|
#define BF_LRADC_DEBUG0_READONLY(v) (((v) & 0xffff) << 16)
|
|
#define BFM_LRADC_DEBUG0_READONLY(v) BM_LRADC_DEBUG0_READONLY
|
|
#define BF_LRADC_DEBUG0_READONLY_V(e) BF_LRADC_DEBUG0_READONLY(BV_LRADC_DEBUG0_READONLY__##e)
|
|
#define BFM_LRADC_DEBUG0_READONLY_V(v) BM_LRADC_DEBUG0_READONLY
|
|
#define BP_LRADC_DEBUG0_STATE 0
|
|
#define BM_LRADC_DEBUG0_STATE 0xfff
|
|
#define BF_LRADC_DEBUG0_STATE(v) (((v) & 0xfff) << 0)
|
|
#define BFM_LRADC_DEBUG0_STATE(v) BM_LRADC_DEBUG0_STATE
|
|
#define BF_LRADC_DEBUG0_STATE_V(e) BF_LRADC_DEBUG0_STATE(BV_LRADC_DEBUG0_STATE__##e)
|
|
#define BFM_LRADC_DEBUG0_STATE_V(v) BM_LRADC_DEBUG0_STATE
|
|
|
|
#define HW_LRADC_DEBUG1 HW(LRADC_DEBUG1)
|
|
#define HWA_LRADC_DEBUG1 (0x80050000 + 0x120)
|
|
#define HWT_LRADC_DEBUG1 HWIO_32_RW
|
|
#define HWN_LRADC_DEBUG1 LRADC_DEBUG1
|
|
#define HWI_LRADC_DEBUG1
|
|
#define HW_LRADC_DEBUG1_SET HW(LRADC_DEBUG1_SET)
|
|
#define HWA_LRADC_DEBUG1_SET (HWA_LRADC_DEBUG1 + 0x4)
|
|
#define HWT_LRADC_DEBUG1_SET HWIO_32_WO
|
|
#define HWN_LRADC_DEBUG1_SET LRADC_DEBUG1
|
|
#define HWI_LRADC_DEBUG1_SET
|
|
#define HW_LRADC_DEBUG1_CLR HW(LRADC_DEBUG1_CLR)
|
|
#define HWA_LRADC_DEBUG1_CLR (HWA_LRADC_DEBUG1 + 0x8)
|
|
#define HWT_LRADC_DEBUG1_CLR HWIO_32_WO
|
|
#define HWN_LRADC_DEBUG1_CLR LRADC_DEBUG1
|
|
#define HWI_LRADC_DEBUG1_CLR
|
|
#define HW_LRADC_DEBUG1_TOG HW(LRADC_DEBUG1_TOG)
|
|
#define HWA_LRADC_DEBUG1_TOG (HWA_LRADC_DEBUG1 + 0xc)
|
|
#define HWT_LRADC_DEBUG1_TOG HWIO_32_WO
|
|
#define HWN_LRADC_DEBUG1_TOG LRADC_DEBUG1
|
|
#define HWI_LRADC_DEBUG1_TOG
|
|
#define BP_LRADC_DEBUG1_REQUEST 16
|
|
#define BM_LRADC_DEBUG1_REQUEST 0xff0000
|
|
#define BF_LRADC_DEBUG1_REQUEST(v) (((v) & 0xff) << 16)
|
|
#define BFM_LRADC_DEBUG1_REQUEST(v) BM_LRADC_DEBUG1_REQUEST
|
|
#define BF_LRADC_DEBUG1_REQUEST_V(e) BF_LRADC_DEBUG1_REQUEST(BV_LRADC_DEBUG1_REQUEST__##e)
|
|
#define BFM_LRADC_DEBUG1_REQUEST_V(v) BM_LRADC_DEBUG1_REQUEST
|
|
#define BP_LRADC_DEBUG1_TESTMODE_COUNT 8
|
|
#define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x1f00
|
|
#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) (((v) & 0x1f) << 8)
|
|
#define BFM_LRADC_DEBUG1_TESTMODE_COUNT(v) BM_LRADC_DEBUG1_TESTMODE_COUNT
|
|
#define BF_LRADC_DEBUG1_TESTMODE_COUNT_V(e) BF_LRADC_DEBUG1_TESTMODE_COUNT(BV_LRADC_DEBUG1_TESTMODE_COUNT__##e)
|
|
#define BFM_LRADC_DEBUG1_TESTMODE_COUNT_V(v) BM_LRADC_DEBUG1_TESTMODE_COUNT
|
|
#define BP_LRADC_DEBUG1_TESTMODE6 2
|
|
#define BM_LRADC_DEBUG1_TESTMODE6 0x4
|
|
#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0
|
|
#define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1
|
|
#define BF_LRADC_DEBUG1_TESTMODE6(v) (((v) & 0x1) << 2)
|
|
#define BFM_LRADC_DEBUG1_TESTMODE6(v) BM_LRADC_DEBUG1_TESTMODE6
|
|
#define BF_LRADC_DEBUG1_TESTMODE6_V(e) BF_LRADC_DEBUG1_TESTMODE6(BV_LRADC_DEBUG1_TESTMODE6__##e)
|
|
#define BFM_LRADC_DEBUG1_TESTMODE6_V(v) BM_LRADC_DEBUG1_TESTMODE6
|
|
#define BP_LRADC_DEBUG1_TESTMODE5 1
|
|
#define BM_LRADC_DEBUG1_TESTMODE5 0x2
|
|
#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0
|
|
#define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1
|
|
#define BF_LRADC_DEBUG1_TESTMODE5(v) (((v) & 0x1) << 1)
|
|
#define BFM_LRADC_DEBUG1_TESTMODE5(v) BM_LRADC_DEBUG1_TESTMODE5
|
|
#define BF_LRADC_DEBUG1_TESTMODE5_V(e) BF_LRADC_DEBUG1_TESTMODE5(BV_LRADC_DEBUG1_TESTMODE5__##e)
|
|
#define BFM_LRADC_DEBUG1_TESTMODE5_V(v) BM_LRADC_DEBUG1_TESTMODE5
|
|
#define BP_LRADC_DEBUG1_TESTMODE 0
|
|
#define BM_LRADC_DEBUG1_TESTMODE 0x1
|
|
#define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0
|
|
#define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1
|
|
#define BF_LRADC_DEBUG1_TESTMODE(v) (((v) & 0x1) << 0)
|
|
#define BFM_LRADC_DEBUG1_TESTMODE(v) BM_LRADC_DEBUG1_TESTMODE
|
|
#define BF_LRADC_DEBUG1_TESTMODE_V(e) BF_LRADC_DEBUG1_TESTMODE(BV_LRADC_DEBUG1_TESTMODE__##e)
|
|
#define BFM_LRADC_DEBUG1_TESTMODE_V(v) BM_LRADC_DEBUG1_TESTMODE
|
|
|
|
#define HW_LRADC_CONVERSION HW(LRADC_CONVERSION)
|
|
#define HWA_LRADC_CONVERSION (0x80050000 + 0x130)
|
|
#define HWT_LRADC_CONVERSION HWIO_32_RW
|
|
#define HWN_LRADC_CONVERSION LRADC_CONVERSION
|
|
#define HWI_LRADC_CONVERSION
|
|
#define HW_LRADC_CONVERSION_SET HW(LRADC_CONVERSION_SET)
|
|
#define HWA_LRADC_CONVERSION_SET (HWA_LRADC_CONVERSION + 0x4)
|
|
#define HWT_LRADC_CONVERSION_SET HWIO_32_WO
|
|
#define HWN_LRADC_CONVERSION_SET LRADC_CONVERSION
|
|
#define HWI_LRADC_CONVERSION_SET
|
|
#define HW_LRADC_CONVERSION_CLR HW(LRADC_CONVERSION_CLR)
|
|
#define HWA_LRADC_CONVERSION_CLR (HWA_LRADC_CONVERSION + 0x8)
|
|
#define HWT_LRADC_CONVERSION_CLR HWIO_32_WO
|
|
#define HWN_LRADC_CONVERSION_CLR LRADC_CONVERSION
|
|
#define HWI_LRADC_CONVERSION_CLR
|
|
#define HW_LRADC_CONVERSION_TOG HW(LRADC_CONVERSION_TOG)
|
|
#define HWA_LRADC_CONVERSION_TOG (HWA_LRADC_CONVERSION + 0xc)
|
|
#define HWT_LRADC_CONVERSION_TOG HWIO_32_WO
|
|
#define HWN_LRADC_CONVERSION_TOG LRADC_CONVERSION
|
|
#define HWI_LRADC_CONVERSION_TOG
|
|
#define BP_LRADC_CONVERSION_AUTOMATIC 20
|
|
#define BM_LRADC_CONVERSION_AUTOMATIC 0x100000
|
|
#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0
|
|
#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1
|
|
#define BF_LRADC_CONVERSION_AUTOMATIC(v) (((v) & 0x1) << 20)
|
|
#define BFM_LRADC_CONVERSION_AUTOMATIC(v) BM_LRADC_CONVERSION_AUTOMATIC
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#define BF_LRADC_CONVERSION_AUTOMATIC_V(e) BF_LRADC_CONVERSION_AUTOMATIC(BV_LRADC_CONVERSION_AUTOMATIC__##e)
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#define BFM_LRADC_CONVERSION_AUTOMATIC_V(v) BM_LRADC_CONVERSION_AUTOMATIC
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#define BP_LRADC_CONVERSION_SCALE_FACTOR 16
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#define BM_LRADC_CONVERSION_SCALE_FACTOR 0x30000
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#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0
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#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1
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#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2
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#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3
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#define BF_LRADC_CONVERSION_SCALE_FACTOR(v) (((v) & 0x3) << 16)
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#define BFM_LRADC_CONVERSION_SCALE_FACTOR(v) BM_LRADC_CONVERSION_SCALE_FACTOR
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#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(e) BF_LRADC_CONVERSION_SCALE_FACTOR(BV_LRADC_CONVERSION_SCALE_FACTOR__##e)
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#define BFM_LRADC_CONVERSION_SCALE_FACTOR_V(v) BM_LRADC_CONVERSION_SCALE_FACTOR
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#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0
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#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x3ff
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#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) (((v) & 0x3ff) << 0)
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#define BFM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE
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#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE_V(e) BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(BV_LRADC_CONVERSION_SCALED_BATT_VOLTAGE__##e)
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#define BFM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE_V(v) BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE
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#define HW_LRADC_DELAYn(_n1) HW(LRADC_DELAYn(_n1))
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#define HWA_LRADC_DELAYn(_n1) (0x80050000 + 0xd0 + (_n1) * 0x10)
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#define HWT_LRADC_DELAYn(_n1) HWIO_32_RW
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#define HWN_LRADC_DELAYn(_n1) LRADC_DELAYn
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#define HWI_LRADC_DELAYn(_n1) (_n1)
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#define HW_LRADC_DELAYn_SET(_n1) HW(LRADC_DELAYn_SET(_n1))
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#define HWA_LRADC_DELAYn_SET(_n1) (HWA_LRADC_DELAYn(_n1) + 0x4)
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#define HWT_LRADC_DELAYn_SET(_n1) HWIO_32_WO
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#define HWN_LRADC_DELAYn_SET(_n1) LRADC_DELAYn
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#define HWI_LRADC_DELAYn_SET(_n1) (_n1)
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#define HW_LRADC_DELAYn_CLR(_n1) HW(LRADC_DELAYn_CLR(_n1))
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#define HWA_LRADC_DELAYn_CLR(_n1) (HWA_LRADC_DELAYn(_n1) + 0x8)
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#define HWT_LRADC_DELAYn_CLR(_n1) HWIO_32_WO
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#define HWN_LRADC_DELAYn_CLR(_n1) LRADC_DELAYn
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#define HWI_LRADC_DELAYn_CLR(_n1) (_n1)
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#define HW_LRADC_DELAYn_TOG(_n1) HW(LRADC_DELAYn_TOG(_n1))
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#define HWA_LRADC_DELAYn_TOG(_n1) (HWA_LRADC_DELAYn(_n1) + 0xc)
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#define HWT_LRADC_DELAYn_TOG(_n1) HWIO_32_WO
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#define HWN_LRADC_DELAYn_TOG(_n1) LRADC_DELAYn
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#define HWI_LRADC_DELAYn_TOG(_n1) (_n1)
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#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
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#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xff000000
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#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) (((v) & 0xff) << 24)
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#define BFM_LRADC_DELAYn_TRIGGER_LRADCS(v) BM_LRADC_DELAYn_TRIGGER_LRADCS
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#define BF_LRADC_DELAYn_TRIGGER_LRADCS_V(e) BF_LRADC_DELAYn_TRIGGER_LRADCS(BV_LRADC_DELAYn_TRIGGER_LRADCS__##e)
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#define BFM_LRADC_DELAYn_TRIGGER_LRADCS_V(v) BM_LRADC_DELAYn_TRIGGER_LRADCS
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#define BP_LRADC_DELAYn_KICK 20
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#define BM_LRADC_DELAYn_KICK 0x100000
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#define BF_LRADC_DELAYn_KICK(v) (((v) & 0x1) << 20)
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#define BFM_LRADC_DELAYn_KICK(v) BM_LRADC_DELAYn_KICK
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#define BF_LRADC_DELAYn_KICK_V(e) BF_LRADC_DELAYn_KICK(BV_LRADC_DELAYn_KICK__##e)
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#define BFM_LRADC_DELAYn_KICK_V(v) BM_LRADC_DELAYn_KICK
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#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
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#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0xf0000
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#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) (((v) & 0xf) << 16)
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#define BFM_LRADC_DELAYn_TRIGGER_DELAYS(v) BM_LRADC_DELAYn_TRIGGER_DELAYS
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#define BF_LRADC_DELAYn_TRIGGER_DELAYS_V(e) BF_LRADC_DELAYn_TRIGGER_DELAYS(BV_LRADC_DELAYn_TRIGGER_DELAYS__##e)
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#define BFM_LRADC_DELAYn_TRIGGER_DELAYS_V(v) BM_LRADC_DELAYn_TRIGGER_DELAYS
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#define BP_LRADC_DELAYn_LOOP_COUNT 11
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#define BM_LRADC_DELAYn_LOOP_COUNT 0xf800
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#define BF_LRADC_DELAYn_LOOP_COUNT(v) (((v) & 0x1f) << 11)
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#define BFM_LRADC_DELAYn_LOOP_COUNT(v) BM_LRADC_DELAYn_LOOP_COUNT
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#define BF_LRADC_DELAYn_LOOP_COUNT_V(e) BF_LRADC_DELAYn_LOOP_COUNT(BV_LRADC_DELAYn_LOOP_COUNT__##e)
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#define BFM_LRADC_DELAYn_LOOP_COUNT_V(v) BM_LRADC_DELAYn_LOOP_COUNT
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#define BP_LRADC_DELAYn_DELAY 0
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#define BM_LRADC_DELAYn_DELAY 0x7ff
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#define BF_LRADC_DELAYn_DELAY(v) (((v) & 0x7ff) << 0)
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#define BFM_LRADC_DELAYn_DELAY(v) BM_LRADC_DELAYn_DELAY
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#define BF_LRADC_DELAYn_DELAY_V(e) BF_LRADC_DELAYn_DELAY(BV_LRADC_DELAYn_DELAY__##e)
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#define BFM_LRADC_DELAYn_DELAY_V(v) BM_LRADC_DELAYn_DELAY
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#define HW_LRADC_CHn(_n1) HW(LRADC_CHn(_n1))
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#define HWA_LRADC_CHn(_n1) (0x80050000 + 0x50 + (_n1) * 0x10)
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#define HWT_LRADC_CHn(_n1) HWIO_32_RW
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#define HWN_LRADC_CHn(_n1) LRADC_CHn
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#define HWI_LRADC_CHn(_n1) (_n1)
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#define HW_LRADC_CHn_SET(_n1) HW(LRADC_CHn_SET(_n1))
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#define HWA_LRADC_CHn_SET(_n1) (HWA_LRADC_CHn(_n1) + 0x4)
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#define HWT_LRADC_CHn_SET(_n1) HWIO_32_WO
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#define HWN_LRADC_CHn_SET(_n1) LRADC_CHn
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#define HWI_LRADC_CHn_SET(_n1) (_n1)
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#define HW_LRADC_CHn_CLR(_n1) HW(LRADC_CHn_CLR(_n1))
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#define HWA_LRADC_CHn_CLR(_n1) (HWA_LRADC_CHn(_n1) + 0x8)
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#define HWT_LRADC_CHn_CLR(_n1) HWIO_32_WO
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#define HWN_LRADC_CHn_CLR(_n1) LRADC_CHn
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#define HWI_LRADC_CHn_CLR(_n1) (_n1)
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#define HW_LRADC_CHn_TOG(_n1) HW(LRADC_CHn_TOG(_n1))
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#define HWA_LRADC_CHn_TOG(_n1) (HWA_LRADC_CHn(_n1) + 0xc)
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#define HWT_LRADC_CHn_TOG(_n1) HWIO_32_WO
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#define HWN_LRADC_CHn_TOG(_n1) LRADC_CHn
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#define HWI_LRADC_CHn_TOG(_n1) (_n1)
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#define BP_LRADC_CHn_TOGGLE 31
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#define BM_LRADC_CHn_TOGGLE 0x80000000
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#define BF_LRADC_CHn_TOGGLE(v) (((v) & 0x1) << 31)
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#define BFM_LRADC_CHn_TOGGLE(v) BM_LRADC_CHn_TOGGLE
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#define BF_LRADC_CHn_TOGGLE_V(e) BF_LRADC_CHn_TOGGLE(BV_LRADC_CHn_TOGGLE__##e)
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#define BFM_LRADC_CHn_TOGGLE_V(v) BM_LRADC_CHn_TOGGLE
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#define BP_LRADC_CHn_ACCUMULATE 29
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#define BM_LRADC_CHn_ACCUMULATE 0x20000000
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#define BF_LRADC_CHn_ACCUMULATE(v) (((v) & 0x1) << 29)
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#define BFM_LRADC_CHn_ACCUMULATE(v) BM_LRADC_CHn_ACCUMULATE
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#define BF_LRADC_CHn_ACCUMULATE_V(e) BF_LRADC_CHn_ACCUMULATE(BV_LRADC_CHn_ACCUMULATE__##e)
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#define BFM_LRADC_CHn_ACCUMULATE_V(v) BM_LRADC_CHn_ACCUMULATE
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#define BP_LRADC_CHn_NUM_SAMPLES 24
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#define BM_LRADC_CHn_NUM_SAMPLES 0x1f000000
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#define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) & 0x1f) << 24)
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#define BFM_LRADC_CHn_NUM_SAMPLES(v) BM_LRADC_CHn_NUM_SAMPLES
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#define BF_LRADC_CHn_NUM_SAMPLES_V(e) BF_LRADC_CHn_NUM_SAMPLES(BV_LRADC_CHn_NUM_SAMPLES__##e)
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#define BFM_LRADC_CHn_NUM_SAMPLES_V(v) BM_LRADC_CHn_NUM_SAMPLES
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#define BP_LRADC_CHn_VALUE 0
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#define BM_LRADC_CHn_VALUE 0x3ffff
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#define BF_LRADC_CHn_VALUE(v) (((v) & 0x3ffff) << 0)
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#define BFM_LRADC_CHn_VALUE(v) BM_LRADC_CHn_VALUE
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#define BF_LRADC_CHn_VALUE_V(e) BF_LRADC_CHn_VALUE(BV_LRADC_CHn_VALUE__##e)
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#define BFM_LRADC_CHn_VALUE_V(v) BM_LRADC_CHn_VALUE
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#endif /* __HEADERGEN_STMP3600_LRADC_H__*/
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