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rockbox/firmware/target/arm/imx233/regs/stmp3600/ir.h
Amaury Pouly eac1ca22bd imx233: generate register headers using headergen_v2 and update code for it 
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.

The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
  BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
  BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
  its equivalent for BF_WR(reg_SET, ...)

I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".

Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml

Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-28 16:49:22 +02:00

751 lines
41 KiB
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stmp3600 version: 2.4.0
* stmp3600 authors: Amaury Pouly
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_STMP3600_IR_H__
#define __HEADERGEN_STMP3600_IR_H__
#define HW_IR_CTRL HW(IR_CTRL)
#define HWA_IR_CTRL (0x80078000 + 0x0)
#define HWT_IR_CTRL HWIO_32_RW
#define HWN_IR_CTRL IR_CTRL
#define HWI_IR_CTRL
#define HW_IR_CTRL_SET HW(IR_CTRL_SET)
#define HWA_IR_CTRL_SET (HWA_IR_CTRL + 0x4)
#define HWT_IR_CTRL_SET HWIO_32_WO
#define HWN_IR_CTRL_SET IR_CTRL
#define HWI_IR_CTRL_SET
#define HW_IR_CTRL_CLR HW(IR_CTRL_CLR)
#define HWA_IR_CTRL_CLR (HWA_IR_CTRL + 0x8)
#define HWT_IR_CTRL_CLR HWIO_32_WO
#define HWN_IR_CTRL_CLR IR_CTRL
#define HWI_IR_CTRL_CLR
#define HW_IR_CTRL_TOG HW(IR_CTRL_TOG)
#define HWA_IR_CTRL_TOG (HWA_IR_CTRL + 0xc)
#define HWT_IR_CTRL_TOG HWIO_32_WO
#define HWN_IR_CTRL_TOG IR_CTRL
#define HWI_IR_CTRL_TOG
#define BP_IR_CTRL_SFTRST 31
#define BM_IR_CTRL_SFTRST 0x80000000
#define BV_IR_CTRL_SFTRST__RUN 0x0
#define BV_IR_CTRL_SFTRST__RESET 0x1
#define BF_IR_CTRL_SFTRST(v) (((v) & 0x1) << 31)
#define BFM_IR_CTRL_SFTRST(v) BM_IR_CTRL_SFTRST
#define BF_IR_CTRL_SFTRST_V(e) BF_IR_CTRL_SFTRST(BV_IR_CTRL_SFTRST__##e)
#define BFM_IR_CTRL_SFTRST_V(v) BM_IR_CTRL_SFTRST
#define BP_IR_CTRL_CLKGATE 30
#define BM_IR_CTRL_CLKGATE 0x40000000
#define BF_IR_CTRL_CLKGATE(v) (((v) & 0x1) << 30)
#define BFM_IR_CTRL_CLKGATE(v) BM_IR_CTRL_CLKGATE
#define BF_IR_CTRL_CLKGATE_V(e) BF_IR_CTRL_CLKGATE(BV_IR_CTRL_CLKGATE__##e)
#define BFM_IR_CTRL_CLKGATE_V(v) BM_IR_CTRL_CLKGATE
#define BP_IR_CTRL_MTA 24
#define BM_IR_CTRL_MTA 0x7000000
#define BV_IR_CTRL_MTA__MTA_10MS 0x0
#define BV_IR_CTRL_MTA__MTA_5MS 0x1
#define BV_IR_CTRL_MTA__MTA_1MS 0x2
#define BV_IR_CTRL_MTA__MTA_500US 0x3
#define BV_IR_CTRL_MTA__MTA_100US 0x4
#define BV_IR_CTRL_MTA__MTA_50US 0x5
#define BV_IR_CTRL_MTA__MTA_10US 0x6
#define BV_IR_CTRL_MTA__MTA_0 0x7
#define BF_IR_CTRL_MTA(v) (((v) & 0x7) << 24)
#define BFM_IR_CTRL_MTA(v) BM_IR_CTRL_MTA
#define BF_IR_CTRL_MTA_V(e) BF_IR_CTRL_MTA(BV_IR_CTRL_MTA__##e)
#define BFM_IR_CTRL_MTA_V(v) BM_IR_CTRL_MTA
#define BP_IR_CTRL_MODE 22
#define BM_IR_CTRL_MODE 0xc00000
#define BV_IR_CTRL_MODE__SIR 0x0
#define BV_IR_CTRL_MODE__MIR 0x1
#define BV_IR_CTRL_MODE__FIR 0x2
#define BV_IR_CTRL_MODE__VFIR 0x3
#define BF_IR_CTRL_MODE(v) (((v) & 0x3) << 22)
#define BFM_IR_CTRL_MODE(v) BM_IR_CTRL_MODE
#define BF_IR_CTRL_MODE_V(e) BF_IR_CTRL_MODE(BV_IR_CTRL_MODE__##e)
#define BFM_IR_CTRL_MODE_V(v) BM_IR_CTRL_MODE
#define BP_IR_CTRL_SPEED 19
#define BM_IR_CTRL_SPEED 0x380000
#define BV_IR_CTRL_SPEED__SPD000 0x0
#define BV_IR_CTRL_SPEED__SPD001 0x1
#define BV_IR_CTRL_SPEED__SPD010 0x2
#define BV_IR_CTRL_SPEED__SPD011 0x3
#define BV_IR_CTRL_SPEED__SPD100 0x4
#define BV_IR_CTRL_SPEED__SPD101 0x5
#define BF_IR_CTRL_SPEED(v) (((v) & 0x7) << 19)
#define BFM_IR_CTRL_SPEED(v) BM_IR_CTRL_SPEED
#define BF_IR_CTRL_SPEED_V(e) BF_IR_CTRL_SPEED(BV_IR_CTRL_SPEED__##e)
#define BFM_IR_CTRL_SPEED_V(v) BM_IR_CTRL_SPEED
#define BP_IR_CTRL_TC_TIME_DIV 8
#define BM_IR_CTRL_TC_TIME_DIV 0x3f00
#define BF_IR_CTRL_TC_TIME_DIV(v) (((v) & 0x3f) << 8)
#define BFM_IR_CTRL_TC_TIME_DIV(v) BM_IR_CTRL_TC_TIME_DIV
#define BF_IR_CTRL_TC_TIME_DIV_V(e) BF_IR_CTRL_TC_TIME_DIV(BV_IR_CTRL_TC_TIME_DIV__##e)
#define BFM_IR_CTRL_TC_TIME_DIV_V(v) BM_IR_CTRL_TC_TIME_DIV
#define BP_IR_CTRL_TC_TYPE 7
#define BM_IR_CTRL_TC_TYPE 0x80
#define BF_IR_CTRL_TC_TYPE(v) (((v) & 0x1) << 7)
#define BFM_IR_CTRL_TC_TYPE(v) BM_IR_CTRL_TC_TYPE
#define BF_IR_CTRL_TC_TYPE_V(e) BF_IR_CTRL_TC_TYPE(BV_IR_CTRL_TC_TYPE__##e)
#define BFM_IR_CTRL_TC_TYPE_V(v) BM_IR_CTRL_TC_TYPE
#define BP_IR_CTRL_SIR_GAP 4
#define BM_IR_CTRL_SIR_GAP 0x70
#define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0
#define BV_IR_CTRL_SIR_GAP__GAP_5K 0x1
#define BV_IR_CTRL_SIR_GAP__GAP_1K 0x2
#define BV_IR_CTRL_SIR_GAP__GAP_500 0x3
#define BV_IR_CTRL_SIR_GAP__GAP_100 0x4
#define BV_IR_CTRL_SIR_GAP__GAP_50 0x5
#define BV_IR_CTRL_SIR_GAP__GAP_10 0x6
#define BV_IR_CTRL_SIR_GAP__GAP_0 0x7
#define BF_IR_CTRL_SIR_GAP(v) (((v) & 0x7) << 4)
#define BFM_IR_CTRL_SIR_GAP(v) BM_IR_CTRL_SIR_GAP
#define BF_IR_CTRL_SIR_GAP_V(e) BF_IR_CTRL_SIR_GAP(BV_IR_CTRL_SIR_GAP__##e)
#define BFM_IR_CTRL_SIR_GAP_V(v) BM_IR_CTRL_SIR_GAP
#define BP_IR_CTRL_SIPEN 3
#define BM_IR_CTRL_SIPEN 0x8
#define BF_IR_CTRL_SIPEN(v) (((v) & 0x1) << 3)
#define BFM_IR_CTRL_SIPEN(v) BM_IR_CTRL_SIPEN
#define BF_IR_CTRL_SIPEN_V(e) BF_IR_CTRL_SIPEN(BV_IR_CTRL_SIPEN__##e)
#define BFM_IR_CTRL_SIPEN_V(v) BM_IR_CTRL_SIPEN
#define BP_IR_CTRL_TCEN 2
#define BM_IR_CTRL_TCEN 0x4
#define BF_IR_CTRL_TCEN(v) (((v) & 0x1) << 2)
#define BFM_IR_CTRL_TCEN(v) BM_IR_CTRL_TCEN
#define BF_IR_CTRL_TCEN_V(e) BF_IR_CTRL_TCEN(BV_IR_CTRL_TCEN__##e)
#define BFM_IR_CTRL_TCEN_V(v) BM_IR_CTRL_TCEN
#define BP_IR_CTRL_TXEN 1
#define BM_IR_CTRL_TXEN 0x2
#define BF_IR_CTRL_TXEN(v) (((v) & 0x1) << 1)
#define BFM_IR_CTRL_TXEN(v) BM_IR_CTRL_TXEN
#define BF_IR_CTRL_TXEN_V(e) BF_IR_CTRL_TXEN(BV_IR_CTRL_TXEN__##e)
#define BFM_IR_CTRL_TXEN_V(v) BM_IR_CTRL_TXEN
#define BP_IR_CTRL_RXEN 0
#define BM_IR_CTRL_RXEN 0x1
#define BF_IR_CTRL_RXEN(v) (((v) & 0x1) << 0)
#define BFM_IR_CTRL_RXEN(v) BM_IR_CTRL_RXEN
#define BF_IR_CTRL_RXEN_V(e) BF_IR_CTRL_RXEN(BV_IR_CTRL_RXEN__##e)
#define BFM_IR_CTRL_RXEN_V(v) BM_IR_CTRL_RXEN
#define HW_IR_TXDMA HW(IR_TXDMA)
#define HWA_IR_TXDMA (0x80078000 + 0x10)
#define HWT_IR_TXDMA HWIO_32_RW
#define HWN_IR_TXDMA IR_TXDMA
#define HWI_IR_TXDMA
#define HW_IR_TXDMA_SET HW(IR_TXDMA_SET)
#define HWA_IR_TXDMA_SET (HWA_IR_TXDMA + 0x4)
#define HWT_IR_TXDMA_SET HWIO_32_WO
#define HWN_IR_TXDMA_SET IR_TXDMA
#define HWI_IR_TXDMA_SET
#define HW_IR_TXDMA_CLR HW(IR_TXDMA_CLR)
#define HWA_IR_TXDMA_CLR (HWA_IR_TXDMA + 0x8)
#define HWT_IR_TXDMA_CLR HWIO_32_WO
#define HWN_IR_TXDMA_CLR IR_TXDMA
#define HWI_IR_TXDMA_CLR
#define HW_IR_TXDMA_TOG HW(IR_TXDMA_TOG)
#define HWA_IR_TXDMA_TOG (HWA_IR_TXDMA + 0xc)
#define HWT_IR_TXDMA_TOG HWIO_32_WO
#define HWN_IR_TXDMA_TOG IR_TXDMA
#define HWI_IR_TXDMA_TOG
#define BP_IR_TXDMA_RUN 31
#define BM_IR_TXDMA_RUN 0x80000000
#define BF_IR_TXDMA_RUN(v) (((v) & 0x1) << 31)
#define BFM_IR_TXDMA_RUN(v) BM_IR_TXDMA_RUN
#define BF_IR_TXDMA_RUN_V(e) BF_IR_TXDMA_RUN(BV_IR_TXDMA_RUN__##e)
#define BFM_IR_TXDMA_RUN_V(v) BM_IR_TXDMA_RUN
#define BP_IR_TXDMA_EMPTY 29
#define BM_IR_TXDMA_EMPTY 0x20000000
#define BF_IR_TXDMA_EMPTY(v) (((v) & 0x1) << 29)
#define BFM_IR_TXDMA_EMPTY(v) BM_IR_TXDMA_EMPTY
#define BF_IR_TXDMA_EMPTY_V(e) BF_IR_TXDMA_EMPTY(BV_IR_TXDMA_EMPTY__##e)
#define BFM_IR_TXDMA_EMPTY_V(v) BM_IR_TXDMA_EMPTY
#define BP_IR_TXDMA_INT 28
#define BM_IR_TXDMA_INT 0x10000000
#define BF_IR_TXDMA_INT(v) (((v) & 0x1) << 28)
#define BFM_IR_TXDMA_INT(v) BM_IR_TXDMA_INT
#define BF_IR_TXDMA_INT_V(e) BF_IR_TXDMA_INT(BV_IR_TXDMA_INT__##e)
#define BFM_IR_TXDMA_INT_V(v) BM_IR_TXDMA_INT
#define BP_IR_TXDMA_CHANGE 27
#define BM_IR_TXDMA_CHANGE 0x8000000
#define BF_IR_TXDMA_CHANGE(v) (((v) & 0x1) << 27)
#define BFM_IR_TXDMA_CHANGE(v) BM_IR_TXDMA_CHANGE
#define BF_IR_TXDMA_CHANGE_V(e) BF_IR_TXDMA_CHANGE(BV_IR_TXDMA_CHANGE__##e)
#define BFM_IR_TXDMA_CHANGE_V(v) BM_IR_TXDMA_CHANGE
#define BP_IR_TXDMA_NEW_MTA 24
#define BM_IR_TXDMA_NEW_MTA 0x7000000
#define BF_IR_TXDMA_NEW_MTA(v) (((v) & 0x7) << 24)
#define BFM_IR_TXDMA_NEW_MTA(v) BM_IR_TXDMA_NEW_MTA
#define BF_IR_TXDMA_NEW_MTA_V(e) BF_IR_TXDMA_NEW_MTA(BV_IR_TXDMA_NEW_MTA__##e)
#define BFM_IR_TXDMA_NEW_MTA_V(v) BM_IR_TXDMA_NEW_MTA
#define BP_IR_TXDMA_NEW_MODE 22
#define BM_IR_TXDMA_NEW_MODE 0xc00000
#define BF_IR_TXDMA_NEW_MODE(v) (((v) & 0x3) << 22)
#define BFM_IR_TXDMA_NEW_MODE(v) BM_IR_TXDMA_NEW_MODE
#define BF_IR_TXDMA_NEW_MODE_V(e) BF_IR_TXDMA_NEW_MODE(BV_IR_TXDMA_NEW_MODE__##e)
#define BFM_IR_TXDMA_NEW_MODE_V(v) BM_IR_TXDMA_NEW_MODE
#define BP_IR_TXDMA_NEW_SPEED 19
#define BM_IR_TXDMA_NEW_SPEED 0x380000
#define BF_IR_TXDMA_NEW_SPEED(v) (((v) & 0x7) << 19)
#define BFM_IR_TXDMA_NEW_SPEED(v) BM_IR_TXDMA_NEW_SPEED
#define BF_IR_TXDMA_NEW_SPEED_V(e) BF_IR_TXDMA_NEW_SPEED(BV_IR_TXDMA_NEW_SPEED__##e)
#define BFM_IR_TXDMA_NEW_SPEED_V(v) BM_IR_TXDMA_NEW_SPEED
#define BP_IR_TXDMA_BOF_TYPE 18
#define BM_IR_TXDMA_BOF_TYPE 0x40000
#define BF_IR_TXDMA_BOF_TYPE(v) (((v) & 0x1) << 18)
#define BFM_IR_TXDMA_BOF_TYPE(v) BM_IR_TXDMA_BOF_TYPE
#define BF_IR_TXDMA_BOF_TYPE_V(e) BF_IR_TXDMA_BOF_TYPE(BV_IR_TXDMA_BOF_TYPE__##e)
#define BFM_IR_TXDMA_BOF_TYPE_V(v) BM_IR_TXDMA_BOF_TYPE
#define BP_IR_TXDMA_XBOFS 12
#define BM_IR_TXDMA_XBOFS 0x3f000
#define BF_IR_TXDMA_XBOFS(v) (((v) & 0x3f) << 12)
#define BFM_IR_TXDMA_XBOFS(v) BM_IR_TXDMA_XBOFS
#define BF_IR_TXDMA_XBOFS_V(e) BF_IR_TXDMA_XBOFS(BV_IR_TXDMA_XBOFS__##e)
#define BFM_IR_TXDMA_XBOFS_V(v) BM_IR_TXDMA_XBOFS
#define BP_IR_TXDMA_XFER_COUNT 0
#define BM_IR_TXDMA_XFER_COUNT 0xfff
#define BF_IR_TXDMA_XFER_COUNT(v) (((v) & 0xfff) << 0)
#define BFM_IR_TXDMA_XFER_COUNT(v) BM_IR_TXDMA_XFER_COUNT
#define BF_IR_TXDMA_XFER_COUNT_V(e) BF_IR_TXDMA_XFER_COUNT(BV_IR_TXDMA_XFER_COUNT__##e)
#define BFM_IR_TXDMA_XFER_COUNT_V(v) BM_IR_TXDMA_XFER_COUNT
#define HW_IR_RXDMA HW(IR_RXDMA)
#define HWA_IR_RXDMA (0x80078000 + 0x20)
#define HWT_IR_RXDMA HWIO_32_RW
#define HWN_IR_RXDMA IR_RXDMA
#define HWI_IR_RXDMA
#define HW_IR_RXDMA_SET HW(IR_RXDMA_SET)
#define HWA_IR_RXDMA_SET (HWA_IR_RXDMA + 0x4)
#define HWT_IR_RXDMA_SET HWIO_32_WO
#define HWN_IR_RXDMA_SET IR_RXDMA
#define HWI_IR_RXDMA_SET
#define HW_IR_RXDMA_CLR HW(IR_RXDMA_CLR)
#define HWA_IR_RXDMA_CLR (HWA_IR_RXDMA + 0x8)
#define HWT_IR_RXDMA_CLR HWIO_32_WO
#define HWN_IR_RXDMA_CLR IR_RXDMA
#define HWI_IR_RXDMA_CLR
#define HW_IR_RXDMA_TOG HW(IR_RXDMA_TOG)
#define HWA_IR_RXDMA_TOG (HWA_IR_RXDMA + 0xc)
#define HWT_IR_RXDMA_TOG HWIO_32_WO
#define HWN_IR_RXDMA_TOG IR_RXDMA
#define HWI_IR_RXDMA_TOG
#define BP_IR_RXDMA_RUN 31
#define BM_IR_RXDMA_RUN 0x80000000
#define BF_IR_RXDMA_RUN(v) (((v) & 0x1) << 31)
#define BFM_IR_RXDMA_RUN(v) BM_IR_RXDMA_RUN
#define BF_IR_RXDMA_RUN_V(e) BF_IR_RXDMA_RUN(BV_IR_RXDMA_RUN__##e)
#define BFM_IR_RXDMA_RUN_V(v) BM_IR_RXDMA_RUN
#define BP_IR_RXDMA_XFER_COUNT 0
#define BM_IR_RXDMA_XFER_COUNT 0x3ff
#define BF_IR_RXDMA_XFER_COUNT(v) (((v) & 0x3ff) << 0)
#define BFM_IR_RXDMA_XFER_COUNT(v) BM_IR_RXDMA_XFER_COUNT
#define BF_IR_RXDMA_XFER_COUNT_V(e) BF_IR_RXDMA_XFER_COUNT(BV_IR_RXDMA_XFER_COUNT__##e)
#define BFM_IR_RXDMA_XFER_COUNT_V(v) BM_IR_RXDMA_XFER_COUNT
#define HW_IR_DBGCTRL HW(IR_DBGCTRL)
#define HWA_IR_DBGCTRL (0x80078000 + 0x30)
#define HWT_IR_DBGCTRL HWIO_32_RW
#define HWN_IR_DBGCTRL IR_DBGCTRL
#define HWI_IR_DBGCTRL
#define HW_IR_DBGCTRL_SET HW(IR_DBGCTRL_SET)
#define HWA_IR_DBGCTRL_SET (HWA_IR_DBGCTRL + 0x4)
#define HWT_IR_DBGCTRL_SET HWIO_32_WO
#define HWN_IR_DBGCTRL_SET IR_DBGCTRL
#define HWI_IR_DBGCTRL_SET
#define HW_IR_DBGCTRL_CLR HW(IR_DBGCTRL_CLR)
#define HWA_IR_DBGCTRL_CLR (HWA_IR_DBGCTRL + 0x8)
#define HWT_IR_DBGCTRL_CLR HWIO_32_WO
#define HWN_IR_DBGCTRL_CLR IR_DBGCTRL
#define HWI_IR_DBGCTRL_CLR
#define HW_IR_DBGCTRL_TOG HW(IR_DBGCTRL_TOG)
#define HWA_IR_DBGCTRL_TOG (HWA_IR_DBGCTRL + 0xc)
#define HWT_IR_DBGCTRL_TOG HWIO_32_WO
#define HWN_IR_DBGCTRL_TOG IR_DBGCTRL
#define HWI_IR_DBGCTRL_TOG
#define BP_IR_DBGCTRL_VFIRSWZ 12
#define BM_IR_DBGCTRL_VFIRSWZ 0x1000
#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL 0x0
#define BV_IR_DBGCTRL_VFIRSWZ__SWAP 0x1
#define BF_IR_DBGCTRL_VFIRSWZ(v) (((v) & 0x1) << 12)
#define BFM_IR_DBGCTRL_VFIRSWZ(v) BM_IR_DBGCTRL_VFIRSWZ
#define BF_IR_DBGCTRL_VFIRSWZ_V(e) BF_IR_DBGCTRL_VFIRSWZ(BV_IR_DBGCTRL_VFIRSWZ__##e)
#define BFM_IR_DBGCTRL_VFIRSWZ_V(v) BM_IR_DBGCTRL_VFIRSWZ
#define BP_IR_DBGCTRL_RXFRMOFF 11
#define BM_IR_DBGCTRL_RXFRMOFF 0x800
#define BF_IR_DBGCTRL_RXFRMOFF(v) (((v) & 0x1) << 11)
#define BFM_IR_DBGCTRL_RXFRMOFF(v) BM_IR_DBGCTRL_RXFRMOFF
#define BF_IR_DBGCTRL_RXFRMOFF_V(e) BF_IR_DBGCTRL_RXFRMOFF(BV_IR_DBGCTRL_RXFRMOFF__##e)
#define BFM_IR_DBGCTRL_RXFRMOFF_V(v) BM_IR_DBGCTRL_RXFRMOFF
#define BP_IR_DBGCTRL_RXCRCOFF 10
#define BM_IR_DBGCTRL_RXCRCOFF 0x400
#define BF_IR_DBGCTRL_RXCRCOFF(v) (((v) & 0x1) << 10)
#define BFM_IR_DBGCTRL_RXCRCOFF(v) BM_IR_DBGCTRL_RXCRCOFF
#define BF_IR_DBGCTRL_RXCRCOFF_V(e) BF_IR_DBGCTRL_RXCRCOFF(BV_IR_DBGCTRL_RXCRCOFF__##e)
#define BFM_IR_DBGCTRL_RXCRCOFF_V(v) BM_IR_DBGCTRL_RXCRCOFF
#define BP_IR_DBGCTRL_RXINVERT 9
#define BM_IR_DBGCTRL_RXINVERT 0x200
#define BF_IR_DBGCTRL_RXINVERT(v) (((v) & 0x1) << 9)
#define BFM_IR_DBGCTRL_RXINVERT(v) BM_IR_DBGCTRL_RXINVERT
#define BF_IR_DBGCTRL_RXINVERT_V(e) BF_IR_DBGCTRL_RXINVERT(BV_IR_DBGCTRL_RXINVERT__##e)
#define BFM_IR_DBGCTRL_RXINVERT_V(v) BM_IR_DBGCTRL_RXINVERT
#define BP_IR_DBGCTRL_TXFRMOFF 8
#define BM_IR_DBGCTRL_TXFRMOFF 0x100
#define BF_IR_DBGCTRL_TXFRMOFF(v) (((v) & 0x1) << 8)
#define BFM_IR_DBGCTRL_TXFRMOFF(v) BM_IR_DBGCTRL_TXFRMOFF
#define BF_IR_DBGCTRL_TXFRMOFF_V(e) BF_IR_DBGCTRL_TXFRMOFF(BV_IR_DBGCTRL_TXFRMOFF__##e)
#define BFM_IR_DBGCTRL_TXFRMOFF_V(v) BM_IR_DBGCTRL_TXFRMOFF
#define BP_IR_DBGCTRL_TXCRCOFF 7
#define BM_IR_DBGCTRL_TXCRCOFF 0x80
#define BF_IR_DBGCTRL_TXCRCOFF(v) (((v) & 0x1) << 7)
#define BFM_IR_DBGCTRL_TXCRCOFF(v) BM_IR_DBGCTRL_TXCRCOFF
#define BF_IR_DBGCTRL_TXCRCOFF_V(e) BF_IR_DBGCTRL_TXCRCOFF(BV_IR_DBGCTRL_TXCRCOFF__##e)
#define BFM_IR_DBGCTRL_TXCRCOFF_V(v) BM_IR_DBGCTRL_TXCRCOFF
#define BP_IR_DBGCTRL_TXINVERT 6
#define BM_IR_DBGCTRL_TXINVERT 0x40
#define BF_IR_DBGCTRL_TXINVERT(v) (((v) & 0x1) << 6)
#define BFM_IR_DBGCTRL_TXINVERT(v) BM_IR_DBGCTRL_TXINVERT
#define BF_IR_DBGCTRL_TXINVERT_V(e) BF_IR_DBGCTRL_TXINVERT(BV_IR_DBGCTRL_TXINVERT__##e)
#define BFM_IR_DBGCTRL_TXINVERT_V(v) BM_IR_DBGCTRL_TXINVERT
#define BP_IR_DBGCTRL_INTLOOPBACK 5
#define BM_IR_DBGCTRL_INTLOOPBACK 0x20
#define BF_IR_DBGCTRL_INTLOOPBACK(v) (((v) & 0x1) << 5)
#define BFM_IR_DBGCTRL_INTLOOPBACK(v) BM_IR_DBGCTRL_INTLOOPBACK
#define BF_IR_DBGCTRL_INTLOOPBACK_V(e) BF_IR_DBGCTRL_INTLOOPBACK(BV_IR_DBGCTRL_INTLOOPBACK__##e)
#define BFM_IR_DBGCTRL_INTLOOPBACK_V(v) BM_IR_DBGCTRL_INTLOOPBACK
#define BP_IR_DBGCTRL_DUPLEX 4
#define BM_IR_DBGCTRL_DUPLEX 0x10
#define BF_IR_DBGCTRL_DUPLEX(v) (((v) & 0x1) << 4)
#define BFM_IR_DBGCTRL_DUPLEX(v) BM_IR_DBGCTRL_DUPLEX
#define BF_IR_DBGCTRL_DUPLEX_V(e) BF_IR_DBGCTRL_DUPLEX(BV_IR_DBGCTRL_DUPLEX__##e)
#define BFM_IR_DBGCTRL_DUPLEX_V(v) BM_IR_DBGCTRL_DUPLEX
#define BP_IR_DBGCTRL_MIO_RX 3
#define BM_IR_DBGCTRL_MIO_RX 0x8
#define BF_IR_DBGCTRL_MIO_RX(v) (((v) & 0x1) << 3)
#define BFM_IR_DBGCTRL_MIO_RX(v) BM_IR_DBGCTRL_MIO_RX
#define BF_IR_DBGCTRL_MIO_RX_V(e) BF_IR_DBGCTRL_MIO_RX(BV_IR_DBGCTRL_MIO_RX__##e)
#define BFM_IR_DBGCTRL_MIO_RX_V(v) BM_IR_DBGCTRL_MIO_RX
#define BP_IR_DBGCTRL_MIO_TX 2
#define BM_IR_DBGCTRL_MIO_TX 0x4
#define BF_IR_DBGCTRL_MIO_TX(v) (((v) & 0x1) << 2)
#define BFM_IR_DBGCTRL_MIO_TX(v) BM_IR_DBGCTRL_MIO_TX
#define BF_IR_DBGCTRL_MIO_TX_V(e) BF_IR_DBGCTRL_MIO_TX(BV_IR_DBGCTRL_MIO_TX__##e)
#define BFM_IR_DBGCTRL_MIO_TX_V(v) BM_IR_DBGCTRL_MIO_TX
#define BP_IR_DBGCTRL_MIO_SCLK 1
#define BM_IR_DBGCTRL_MIO_SCLK 0x2
#define BF_IR_DBGCTRL_MIO_SCLK(v) (((v) & 0x1) << 1)
#define BFM_IR_DBGCTRL_MIO_SCLK(v) BM_IR_DBGCTRL_MIO_SCLK
#define BF_IR_DBGCTRL_MIO_SCLK_V(e) BF_IR_DBGCTRL_MIO_SCLK(BV_IR_DBGCTRL_MIO_SCLK__##e)
#define BFM_IR_DBGCTRL_MIO_SCLK_V(v) BM_IR_DBGCTRL_MIO_SCLK
#define BP_IR_DBGCTRL_MIO_EN 0
#define BM_IR_DBGCTRL_MIO_EN 0x1
#define BF_IR_DBGCTRL_MIO_EN(v) (((v) & 0x1) << 0)
#define BFM_IR_DBGCTRL_MIO_EN(v) BM_IR_DBGCTRL_MIO_EN
#define BF_IR_DBGCTRL_MIO_EN_V(e) BF_IR_DBGCTRL_MIO_EN(BV_IR_DBGCTRL_MIO_EN__##e)
#define BFM_IR_DBGCTRL_MIO_EN_V(v) BM_IR_DBGCTRL_MIO_EN
#define HW_IR_INTR HW(IR_INTR)
#define HWA_IR_INTR (0x80078000 + 0x40)
#define HWT_IR_INTR HWIO_32_RW
#define HWN_IR_INTR IR_INTR
#define HWI_IR_INTR
#define HW_IR_INTR_SET HW(IR_INTR_SET)
#define HWA_IR_INTR_SET (HWA_IR_INTR + 0x4)
#define HWT_IR_INTR_SET HWIO_32_WO
#define HWN_IR_INTR_SET IR_INTR
#define HWI_IR_INTR_SET
#define HW_IR_INTR_CLR HW(IR_INTR_CLR)
#define HWA_IR_INTR_CLR (HWA_IR_INTR + 0x8)
#define HWT_IR_INTR_CLR HWIO_32_WO
#define HWN_IR_INTR_CLR IR_INTR
#define HWI_IR_INTR_CLR
#define HW_IR_INTR_TOG HW(IR_INTR_TOG)
#define HWA_IR_INTR_TOG (HWA_IR_INTR + 0xc)
#define HWT_IR_INTR_TOG HWIO_32_WO
#define HWN_IR_INTR_TOG IR_INTR
#define HWI_IR_INTR_TOG
#define BP_IR_INTR_RXABORT_IRQ_EN 22
#define BM_IR_INTR_RXABORT_IRQ_EN 0x400000
#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_RXABORT_IRQ_EN(v) (((v) & 0x1) << 22)
#define BFM_IR_INTR_RXABORT_IRQ_EN(v) BM_IR_INTR_RXABORT_IRQ_EN
#define BF_IR_INTR_RXABORT_IRQ_EN_V(e) BF_IR_INTR_RXABORT_IRQ_EN(BV_IR_INTR_RXABORT_IRQ_EN__##e)
#define BFM_IR_INTR_RXABORT_IRQ_EN_V(v) BM_IR_INTR_RXABORT_IRQ_EN
#define BP_IR_INTR_SPEED_IRQ_EN 21
#define BM_IR_INTR_SPEED_IRQ_EN 0x200000
#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_SPEED_IRQ_EN(v) (((v) & 0x1) << 21)
#define BFM_IR_INTR_SPEED_IRQ_EN(v) BM_IR_INTR_SPEED_IRQ_EN
#define BF_IR_INTR_SPEED_IRQ_EN_V(e) BF_IR_INTR_SPEED_IRQ_EN(BV_IR_INTR_SPEED_IRQ_EN__##e)
#define BFM_IR_INTR_SPEED_IRQ_EN_V(v) BM_IR_INTR_SPEED_IRQ_EN
#define BP_IR_INTR_RXOF_IRQ_EN 20
#define BM_IR_INTR_RXOF_IRQ_EN 0x100000
#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_RXOF_IRQ_EN(v) (((v) & 0x1) << 20)
#define BFM_IR_INTR_RXOF_IRQ_EN(v) BM_IR_INTR_RXOF_IRQ_EN
#define BF_IR_INTR_RXOF_IRQ_EN_V(e) BF_IR_INTR_RXOF_IRQ_EN(BV_IR_INTR_RXOF_IRQ_EN__##e)
#define BFM_IR_INTR_RXOF_IRQ_EN_V(v) BM_IR_INTR_RXOF_IRQ_EN
#define BP_IR_INTR_TXUF_IRQ_EN 19
#define BM_IR_INTR_TXUF_IRQ_EN 0x80000
#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_TXUF_IRQ_EN(v) (((v) & 0x1) << 19)
#define BFM_IR_INTR_TXUF_IRQ_EN(v) BM_IR_INTR_TXUF_IRQ_EN
#define BF_IR_INTR_TXUF_IRQ_EN_V(e) BF_IR_INTR_TXUF_IRQ_EN(BV_IR_INTR_TXUF_IRQ_EN__##e)
#define BFM_IR_INTR_TXUF_IRQ_EN_V(v) BM_IR_INTR_TXUF_IRQ_EN
#define BP_IR_INTR_TC_IRQ_EN 18
#define BM_IR_INTR_TC_IRQ_EN 0x40000
#define BV_IR_INTR_TC_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_TC_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_TC_IRQ_EN(v) (((v) & 0x1) << 18)
#define BFM_IR_INTR_TC_IRQ_EN(v) BM_IR_INTR_TC_IRQ_EN
#define BF_IR_INTR_TC_IRQ_EN_V(e) BF_IR_INTR_TC_IRQ_EN(BV_IR_INTR_TC_IRQ_EN__##e)
#define BFM_IR_INTR_TC_IRQ_EN_V(v) BM_IR_INTR_TC_IRQ_EN
#define BP_IR_INTR_RX_IRQ_EN 17
#define BM_IR_INTR_RX_IRQ_EN 0x20000
#define BV_IR_INTR_RX_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_RX_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_RX_IRQ_EN(v) (((v) & 0x1) << 17)
#define BFM_IR_INTR_RX_IRQ_EN(v) BM_IR_INTR_RX_IRQ_EN
#define BF_IR_INTR_RX_IRQ_EN_V(e) BF_IR_INTR_RX_IRQ_EN(BV_IR_INTR_RX_IRQ_EN__##e)
#define BFM_IR_INTR_RX_IRQ_EN_V(v) BM_IR_INTR_RX_IRQ_EN
#define BP_IR_INTR_TX_IRQ_EN 16
#define BM_IR_INTR_TX_IRQ_EN 0x10000
#define BV_IR_INTR_TX_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_TX_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_TX_IRQ_EN(v) (((v) & 0x1) << 16)
#define BFM_IR_INTR_TX_IRQ_EN(v) BM_IR_INTR_TX_IRQ_EN
#define BF_IR_INTR_TX_IRQ_EN_V(e) BF_IR_INTR_TX_IRQ_EN(BV_IR_INTR_TX_IRQ_EN__##e)
#define BFM_IR_INTR_TX_IRQ_EN_V(v) BM_IR_INTR_TX_IRQ_EN
#define BP_IR_INTR_RXABORT_IRQ 6
#define BM_IR_INTR_RXABORT_IRQ 0x40
#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_RXABORT_IRQ__REQUEST 0x1
#define BF_IR_INTR_RXABORT_IRQ(v) (((v) & 0x1) << 6)
#define BFM_IR_INTR_RXABORT_IRQ(v) BM_IR_INTR_RXABORT_IRQ
#define BF_IR_INTR_RXABORT_IRQ_V(e) BF_IR_INTR_RXABORT_IRQ(BV_IR_INTR_RXABORT_IRQ__##e)
#define BFM_IR_INTR_RXABORT_IRQ_V(v) BM_IR_INTR_RXABORT_IRQ
#define BP_IR_INTR_SPEED_IRQ 5
#define BM_IR_INTR_SPEED_IRQ 0x20
#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_SPEED_IRQ__REQUEST 0x1
#define BF_IR_INTR_SPEED_IRQ(v) (((v) & 0x1) << 5)
#define BFM_IR_INTR_SPEED_IRQ(v) BM_IR_INTR_SPEED_IRQ
#define BF_IR_INTR_SPEED_IRQ_V(e) BF_IR_INTR_SPEED_IRQ(BV_IR_INTR_SPEED_IRQ__##e)
#define BFM_IR_INTR_SPEED_IRQ_V(v) BM_IR_INTR_SPEED_IRQ
#define BP_IR_INTR_RXOF_IRQ 4
#define BM_IR_INTR_RXOF_IRQ 0x10
#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_RXOF_IRQ__REQUEST 0x1
#define BF_IR_INTR_RXOF_IRQ(v) (((v) & 0x1) << 4)
#define BFM_IR_INTR_RXOF_IRQ(v) BM_IR_INTR_RXOF_IRQ
#define BF_IR_INTR_RXOF_IRQ_V(e) BF_IR_INTR_RXOF_IRQ(BV_IR_INTR_RXOF_IRQ__##e)
#define BFM_IR_INTR_RXOF_IRQ_V(v) BM_IR_INTR_RXOF_IRQ
#define BP_IR_INTR_TXUF_IRQ 3
#define BM_IR_INTR_TXUF_IRQ 0x8
#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_TXUF_IRQ__REQUEST 0x1
#define BF_IR_INTR_TXUF_IRQ(v) (((v) & 0x1) << 3)
#define BFM_IR_INTR_TXUF_IRQ(v) BM_IR_INTR_TXUF_IRQ
#define BF_IR_INTR_TXUF_IRQ_V(e) BF_IR_INTR_TXUF_IRQ(BV_IR_INTR_TXUF_IRQ__##e)
#define BFM_IR_INTR_TXUF_IRQ_V(v) BM_IR_INTR_TXUF_IRQ
#define BP_IR_INTR_TC_IRQ 2
#define BM_IR_INTR_TC_IRQ 0x4
#define BV_IR_INTR_TC_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_TC_IRQ__REQUEST 0x1
#define BF_IR_INTR_TC_IRQ(v) (((v) & 0x1) << 2)
#define BFM_IR_INTR_TC_IRQ(v) BM_IR_INTR_TC_IRQ
#define BF_IR_INTR_TC_IRQ_V(e) BF_IR_INTR_TC_IRQ(BV_IR_INTR_TC_IRQ__##e)
#define BFM_IR_INTR_TC_IRQ_V(v) BM_IR_INTR_TC_IRQ
#define BP_IR_INTR_RX_IRQ 1
#define BM_IR_INTR_RX_IRQ 0x2
#define BV_IR_INTR_RX_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_RX_IRQ__REQUEST 0x1
#define BF_IR_INTR_RX_IRQ(v) (((v) & 0x1) << 1)
#define BFM_IR_INTR_RX_IRQ(v) BM_IR_INTR_RX_IRQ
#define BF_IR_INTR_RX_IRQ_V(e) BF_IR_INTR_RX_IRQ(BV_IR_INTR_RX_IRQ__##e)
#define BFM_IR_INTR_RX_IRQ_V(v) BM_IR_INTR_RX_IRQ
#define BP_IR_INTR_TX_IRQ 0
#define BM_IR_INTR_TX_IRQ 0x1
#define BV_IR_INTR_TX_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_TX_IRQ__REQUEST 0x1
#define BF_IR_INTR_TX_IRQ(v) (((v) & 0x1) << 0)
#define BFM_IR_INTR_TX_IRQ(v) BM_IR_INTR_TX_IRQ
#define BF_IR_INTR_TX_IRQ_V(e) BF_IR_INTR_TX_IRQ(BV_IR_INTR_TX_IRQ__##e)
#define BFM_IR_INTR_TX_IRQ_V(v) BM_IR_INTR_TX_IRQ
#define HW_IR_DATA HW(IR_DATA)
#define HWA_IR_DATA (0x80078000 + 0x50)
#define HWT_IR_DATA HWIO_32_RW
#define HWN_IR_DATA IR_DATA
#define HWI_IR_DATA
#define BP_IR_DATA_DATA 0
#define BM_IR_DATA_DATA 0xffffffff
#define BF_IR_DATA_DATA(v) (((v) & 0xffffffff) << 0)
#define BFM_IR_DATA_DATA(v) BM_IR_DATA_DATA
#define BF_IR_DATA_DATA_V(e) BF_IR_DATA_DATA(BV_IR_DATA_DATA__##e)
#define BFM_IR_DATA_DATA_V(v) BM_IR_DATA_DATA
#define HW_IR_STAT HW(IR_STAT)
#define HWA_IR_STAT (0x80078000 + 0x60)
#define HWT_IR_STAT HWIO_32_RW
#define HWN_IR_STAT IR_STAT
#define HWI_IR_STAT
#define BP_IR_STAT_PRESENT 31
#define BM_IR_STAT_PRESENT 0x80000000
#define BV_IR_STAT_PRESENT__UNAVAILABLE 0x0
#define BV_IR_STAT_PRESENT__AVAILABLE 0x1
#define BF_IR_STAT_PRESENT(v) (((v) & 0x1) << 31)
#define BFM_IR_STAT_PRESENT(v) BM_IR_STAT_PRESENT
#define BF_IR_STAT_PRESENT_V(e) BF_IR_STAT_PRESENT(BV_IR_STAT_PRESENT__##e)
#define BFM_IR_STAT_PRESENT_V(v) BM_IR_STAT_PRESENT
#define BP_IR_STAT_MODE_ALLOWED 29
#define BM_IR_STAT_MODE_ALLOWED 0x60000000
#define BV_IR_STAT_MODE_ALLOWED__VFIR 0x0
#define BV_IR_STAT_MODE_ALLOWED__FIR 0x1
#define BV_IR_STAT_MODE_ALLOWED__MIR 0x2
#define BV_IR_STAT_MODE_ALLOWED__SIR 0x3
#define BF_IR_STAT_MODE_ALLOWED(v) (((v) & 0x3) << 29)
#define BFM_IR_STAT_MODE_ALLOWED(v) BM_IR_STAT_MODE_ALLOWED
#define BF_IR_STAT_MODE_ALLOWED_V(e) BF_IR_STAT_MODE_ALLOWED(BV_IR_STAT_MODE_ALLOWED__##e)
#define BFM_IR_STAT_MODE_ALLOWED_V(v) BM_IR_STAT_MODE_ALLOWED
#define BP_IR_STAT_ANY_IRQ 28
#define BM_IR_STAT_ANY_IRQ 0x10000000
#define BV_IR_STAT_ANY_IRQ__NO_REQUEST 0x0
#define BV_IR_STAT_ANY_IRQ__REQUEST 0x1
#define BF_IR_STAT_ANY_IRQ(v) (((v) & 0x1) << 28)
#define BFM_IR_STAT_ANY_IRQ(v) BM_IR_STAT_ANY_IRQ
#define BF_IR_STAT_ANY_IRQ_V(e) BF_IR_STAT_ANY_IRQ(BV_IR_STAT_ANY_IRQ__##e)
#define BFM_IR_STAT_ANY_IRQ_V(v) BM_IR_STAT_ANY_IRQ
#define BP_IR_STAT_RXABORT_SUMMARY 22
#define BM_IR_STAT_RXABORT_SUMMARY 0x400000
#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_RXABORT_SUMMARY(v) (((v) & 0x1) << 22)
#define BFM_IR_STAT_RXABORT_SUMMARY(v) BM_IR_STAT_RXABORT_SUMMARY
#define BF_IR_STAT_RXABORT_SUMMARY_V(e) BF_IR_STAT_RXABORT_SUMMARY(BV_IR_STAT_RXABORT_SUMMARY__##e)
#define BFM_IR_STAT_RXABORT_SUMMARY_V(v) BM_IR_STAT_RXABORT_SUMMARY
#define BP_IR_STAT_SPEED_SUMMARY 21
#define BM_IR_STAT_SPEED_SUMMARY 0x200000
#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_SPEED_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_SPEED_SUMMARY(v) (((v) & 0x1) << 21)
#define BFM_IR_STAT_SPEED_SUMMARY(v) BM_IR_STAT_SPEED_SUMMARY
#define BF_IR_STAT_SPEED_SUMMARY_V(e) BF_IR_STAT_SPEED_SUMMARY(BV_IR_STAT_SPEED_SUMMARY__##e)
#define BFM_IR_STAT_SPEED_SUMMARY_V(v) BM_IR_STAT_SPEED_SUMMARY
#define BP_IR_STAT_RXOF_SUMMARY 20
#define BM_IR_STAT_RXOF_SUMMARY 0x100000
#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_RXOF_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_RXOF_SUMMARY(v) (((v) & 0x1) << 20)
#define BFM_IR_STAT_RXOF_SUMMARY(v) BM_IR_STAT_RXOF_SUMMARY
#define BF_IR_STAT_RXOF_SUMMARY_V(e) BF_IR_STAT_RXOF_SUMMARY(BV_IR_STAT_RXOF_SUMMARY__##e)
#define BFM_IR_STAT_RXOF_SUMMARY_V(v) BM_IR_STAT_RXOF_SUMMARY
#define BP_IR_STAT_TXUF_SUMMARY 19
#define BM_IR_STAT_TXUF_SUMMARY 0x80000
#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_TXUF_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_TXUF_SUMMARY(v) (((v) & 0x1) << 19)
#define BFM_IR_STAT_TXUF_SUMMARY(v) BM_IR_STAT_TXUF_SUMMARY
#define BF_IR_STAT_TXUF_SUMMARY_V(e) BF_IR_STAT_TXUF_SUMMARY(BV_IR_STAT_TXUF_SUMMARY__##e)
#define BFM_IR_STAT_TXUF_SUMMARY_V(v) BM_IR_STAT_TXUF_SUMMARY
#define BP_IR_STAT_TC_SUMMARY 18
#define BM_IR_STAT_TC_SUMMARY 0x40000
#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_TC_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_TC_SUMMARY(v) (((v) & 0x1) << 18)
#define BFM_IR_STAT_TC_SUMMARY(v) BM_IR_STAT_TC_SUMMARY
#define BF_IR_STAT_TC_SUMMARY_V(e) BF_IR_STAT_TC_SUMMARY(BV_IR_STAT_TC_SUMMARY__##e)
#define BFM_IR_STAT_TC_SUMMARY_V(v) BM_IR_STAT_TC_SUMMARY
#define BP_IR_STAT_RX_SUMMARY 17
#define BM_IR_STAT_RX_SUMMARY 0x20000
#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_RX_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_RX_SUMMARY(v) (((v) & 0x1) << 17)
#define BFM_IR_STAT_RX_SUMMARY(v) BM_IR_STAT_RX_SUMMARY
#define BF_IR_STAT_RX_SUMMARY_V(e) BF_IR_STAT_RX_SUMMARY(BV_IR_STAT_RX_SUMMARY__##e)
#define BFM_IR_STAT_RX_SUMMARY_V(v) BM_IR_STAT_RX_SUMMARY
#define BP_IR_STAT_TX_SUMMARY 16
#define BM_IR_STAT_TX_SUMMARY 0x10000
#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_TX_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_TX_SUMMARY(v) (((v) & 0x1) << 16)
#define BFM_IR_STAT_TX_SUMMARY(v) BM_IR_STAT_TX_SUMMARY
#define BF_IR_STAT_TX_SUMMARY_V(e) BF_IR_STAT_TX_SUMMARY(BV_IR_STAT_TX_SUMMARY__##e)
#define BFM_IR_STAT_TX_SUMMARY_V(v) BM_IR_STAT_TX_SUMMARY
#define BP_IR_STAT_MEDIA_BUSY 2
#define BM_IR_STAT_MEDIA_BUSY 0x4
#define BF_IR_STAT_MEDIA_BUSY(v) (((v) & 0x1) << 2)
#define BFM_IR_STAT_MEDIA_BUSY(v) BM_IR_STAT_MEDIA_BUSY
#define BF_IR_STAT_MEDIA_BUSY_V(e) BF_IR_STAT_MEDIA_BUSY(BV_IR_STAT_MEDIA_BUSY__##e)
#define BFM_IR_STAT_MEDIA_BUSY_V(v) BM_IR_STAT_MEDIA_BUSY
#define BP_IR_STAT_RX_ACTIVE 1
#define BM_IR_STAT_RX_ACTIVE 0x2
#define BF_IR_STAT_RX_ACTIVE(v) (((v) & 0x1) << 1)
#define BFM_IR_STAT_RX_ACTIVE(v) BM_IR_STAT_RX_ACTIVE
#define BF_IR_STAT_RX_ACTIVE_V(e) BF_IR_STAT_RX_ACTIVE(BV_IR_STAT_RX_ACTIVE__##e)
#define BFM_IR_STAT_RX_ACTIVE_V(v) BM_IR_STAT_RX_ACTIVE
#define BP_IR_STAT_TX_ACTIVE 0
#define BM_IR_STAT_TX_ACTIVE 0x1
#define BF_IR_STAT_TX_ACTIVE(v) (((v) & 0x1) << 0)
#define BFM_IR_STAT_TX_ACTIVE(v) BM_IR_STAT_TX_ACTIVE
#define BF_IR_STAT_TX_ACTIVE_V(e) BF_IR_STAT_TX_ACTIVE(BV_IR_STAT_TX_ACTIVE__##e)
#define BFM_IR_STAT_TX_ACTIVE_V(v) BM_IR_STAT_TX_ACTIVE
#define HW_IR_TCCTRL HW(IR_TCCTRL)
#define HWA_IR_TCCTRL (0x80078000 + 0x70)
#define HWT_IR_TCCTRL HWIO_32_RW
#define HWN_IR_TCCTRL IR_TCCTRL
#define HWI_IR_TCCTRL
#define HW_IR_TCCTRL_SET HW(IR_TCCTRL_SET)
#define HWA_IR_TCCTRL_SET (HWA_IR_TCCTRL + 0x4)
#define HWT_IR_TCCTRL_SET HWIO_32_WO
#define HWN_IR_TCCTRL_SET IR_TCCTRL
#define HWI_IR_TCCTRL_SET
#define HW_IR_TCCTRL_CLR HW(IR_TCCTRL_CLR)
#define HWA_IR_TCCTRL_CLR (HWA_IR_TCCTRL + 0x8)
#define HWT_IR_TCCTRL_CLR HWIO_32_WO
#define HWN_IR_TCCTRL_CLR IR_TCCTRL
#define HWI_IR_TCCTRL_CLR
#define HW_IR_TCCTRL_TOG HW(IR_TCCTRL_TOG)
#define HWA_IR_TCCTRL_TOG (HWA_IR_TCCTRL + 0xc)
#define HWT_IR_TCCTRL_TOG HWIO_32_WO
#define HWN_IR_TCCTRL_TOG IR_TCCTRL
#define HWI_IR_TCCTRL_TOG
#define BP_IR_TCCTRL_INIT 31
#define BM_IR_TCCTRL_INIT 0x80000000
#define BF_IR_TCCTRL_INIT(v) (((v) & 0x1) << 31)
#define BFM_IR_TCCTRL_INIT(v) BM_IR_TCCTRL_INIT
#define BF_IR_TCCTRL_INIT_V(e) BF_IR_TCCTRL_INIT(BV_IR_TCCTRL_INIT__##e)
#define BFM_IR_TCCTRL_INIT_V(v) BM_IR_TCCTRL_INIT
#define BP_IR_TCCTRL_GO 30
#define BM_IR_TCCTRL_GO 0x40000000
#define BF_IR_TCCTRL_GO(v) (((v) & 0x1) << 30)
#define BFM_IR_TCCTRL_GO(v) BM_IR_TCCTRL_GO
#define BF_IR_TCCTRL_GO_V(e) BF_IR_TCCTRL_GO(BV_IR_TCCTRL_GO__##e)
#define BFM_IR_TCCTRL_GO_V(v) BM_IR_TCCTRL_GO
#define BP_IR_TCCTRL_BUSY 29
#define BM_IR_TCCTRL_BUSY 0x20000000
#define BF_IR_TCCTRL_BUSY(v) (((v) & 0x1) << 29)
#define BFM_IR_TCCTRL_BUSY(v) BM_IR_TCCTRL_BUSY
#define BF_IR_TCCTRL_BUSY_V(e) BF_IR_TCCTRL_BUSY(BV_IR_TCCTRL_BUSY__##e)
#define BFM_IR_TCCTRL_BUSY_V(v) BM_IR_TCCTRL_BUSY
#define BP_IR_TCCTRL_TEMIC 24
#define BM_IR_TCCTRL_TEMIC 0x1000000
#define BV_IR_TCCTRL_TEMIC__LOW 0x0
#define BV_IR_TCCTRL_TEMIC__HIGH 0x1
#define BF_IR_TCCTRL_TEMIC(v) (((v) & 0x1) << 24)
#define BFM_IR_TCCTRL_TEMIC(v) BM_IR_TCCTRL_TEMIC
#define BF_IR_TCCTRL_TEMIC_V(e) BF_IR_TCCTRL_TEMIC(BV_IR_TCCTRL_TEMIC__##e)
#define BFM_IR_TCCTRL_TEMIC_V(v) BM_IR_TCCTRL_TEMIC
#define BP_IR_TCCTRL_EXT_DATA 16
#define BM_IR_TCCTRL_EXT_DATA 0xff0000
#define BF_IR_TCCTRL_EXT_DATA(v) (((v) & 0xff) << 16)
#define BFM_IR_TCCTRL_EXT_DATA(v) BM_IR_TCCTRL_EXT_DATA
#define BF_IR_TCCTRL_EXT_DATA_V(e) BF_IR_TCCTRL_EXT_DATA(BV_IR_TCCTRL_EXT_DATA__##e)
#define BFM_IR_TCCTRL_EXT_DATA_V(v) BM_IR_TCCTRL_EXT_DATA
#define BP_IR_TCCTRL_DATA 8
#define BM_IR_TCCTRL_DATA 0xff00
#define BF_IR_TCCTRL_DATA(v) (((v) & 0xff) << 8)
#define BFM_IR_TCCTRL_DATA(v) BM_IR_TCCTRL_DATA
#define BF_IR_TCCTRL_DATA_V(e) BF_IR_TCCTRL_DATA(BV_IR_TCCTRL_DATA__##e)
#define BFM_IR_TCCTRL_DATA_V(v) BM_IR_TCCTRL_DATA
#define BP_IR_TCCTRL_ADDR 5
#define BM_IR_TCCTRL_ADDR 0xe0
#define BF_IR_TCCTRL_ADDR(v) (((v) & 0x7) << 5)
#define BFM_IR_TCCTRL_ADDR(v) BM_IR_TCCTRL_ADDR
#define BF_IR_TCCTRL_ADDR_V(e) BF_IR_TCCTRL_ADDR(BV_IR_TCCTRL_ADDR__##e)
#define BFM_IR_TCCTRL_ADDR_V(v) BM_IR_TCCTRL_ADDR
#define BP_IR_TCCTRL_INDX 1
#define BM_IR_TCCTRL_INDX 0x1e
#define BF_IR_TCCTRL_INDX(v) (((v) & 0xf) << 1)
#define BFM_IR_TCCTRL_INDX(v) BM_IR_TCCTRL_INDX
#define BF_IR_TCCTRL_INDX_V(e) BF_IR_TCCTRL_INDX(BV_IR_TCCTRL_INDX__##e)
#define BFM_IR_TCCTRL_INDX_V(v) BM_IR_TCCTRL_INDX
#define BP_IR_TCCTRL_C 0
#define BM_IR_TCCTRL_C 0x1
#define BF_IR_TCCTRL_C(v) (((v) & 0x1) << 0)
#define BFM_IR_TCCTRL_C(v) BM_IR_TCCTRL_C
#define BF_IR_TCCTRL_C_V(e) BF_IR_TCCTRL_C(BV_IR_TCCTRL_C__##e)
#define BFM_IR_TCCTRL_C_V(v) BM_IR_TCCTRL_C
#define HW_IR_SI_READ HW(IR_SI_READ)
#define HWA_IR_SI_READ (0x80078000 + 0x80)
#define HWT_IR_SI_READ HWIO_32_RW
#define HWN_IR_SI_READ IR_SI_READ
#define HWI_IR_SI_READ
#define BP_IR_SI_READ_ABORT 8
#define BM_IR_SI_READ_ABORT 0x100
#define BF_IR_SI_READ_ABORT(v) (((v) & 0x1) << 8)
#define BFM_IR_SI_READ_ABORT(v) BM_IR_SI_READ_ABORT
#define BF_IR_SI_READ_ABORT_V(e) BF_IR_SI_READ_ABORT(BV_IR_SI_READ_ABORT__##e)
#define BFM_IR_SI_READ_ABORT_V(v) BM_IR_SI_READ_ABORT
#define BP_IR_SI_READ_DATA 0
#define BM_IR_SI_READ_DATA 0xff
#define BF_IR_SI_READ_DATA(v) (((v) & 0xff) << 0)
#define BFM_IR_SI_READ_DATA(v) BM_IR_SI_READ_DATA
#define BF_IR_SI_READ_DATA_V(e) BF_IR_SI_READ_DATA(BV_IR_SI_READ_DATA__##e)
#define BFM_IR_SI_READ_DATA_V(v) BM_IR_SI_READ_DATA
#define HW_IR_DEBUG HW(IR_DEBUG)
#define HWA_IR_DEBUG (0x80078000 + 0x90)
#define HWT_IR_DEBUG HWIO_32_RW
#define HWN_IR_DEBUG IR_DEBUG
#define HWI_IR_DEBUG
#define BP_IR_DEBUG_TXDMAKICK 5
#define BM_IR_DEBUG_TXDMAKICK 0x20
#define BF_IR_DEBUG_TXDMAKICK(v) (((v) & 0x1) << 5)
#define BFM_IR_DEBUG_TXDMAKICK(v) BM_IR_DEBUG_TXDMAKICK
#define BF_IR_DEBUG_TXDMAKICK_V(e) BF_IR_DEBUG_TXDMAKICK(BV_IR_DEBUG_TXDMAKICK__##e)
#define BFM_IR_DEBUG_TXDMAKICK_V(v) BM_IR_DEBUG_TXDMAKICK
#define BP_IR_DEBUG_RXDMAKICK 4
#define BM_IR_DEBUG_RXDMAKICK 0x10
#define BF_IR_DEBUG_RXDMAKICK(v) (((v) & 0x1) << 4)
#define BFM_IR_DEBUG_RXDMAKICK(v) BM_IR_DEBUG_RXDMAKICK
#define BF_IR_DEBUG_RXDMAKICK_V(e) BF_IR_DEBUG_RXDMAKICK(BV_IR_DEBUG_RXDMAKICK__##e)
#define BFM_IR_DEBUG_RXDMAKICK_V(v) BM_IR_DEBUG_RXDMAKICK
#define BP_IR_DEBUG_TXDMAEND 3
#define BM_IR_DEBUG_TXDMAEND 0x8
#define BF_IR_DEBUG_TXDMAEND(v) (((v) & 0x1) << 3)
#define BFM_IR_DEBUG_TXDMAEND(v) BM_IR_DEBUG_TXDMAEND
#define BF_IR_DEBUG_TXDMAEND_V(e) BF_IR_DEBUG_TXDMAEND(BV_IR_DEBUG_TXDMAEND__##e)
#define BFM_IR_DEBUG_TXDMAEND_V(v) BM_IR_DEBUG_TXDMAEND
#define BP_IR_DEBUG_RXDMAEND 2
#define BM_IR_DEBUG_RXDMAEND 0x4
#define BF_IR_DEBUG_RXDMAEND(v) (((v) & 0x1) << 2)
#define BFM_IR_DEBUG_RXDMAEND(v) BM_IR_DEBUG_RXDMAEND
#define BF_IR_DEBUG_RXDMAEND_V(e) BF_IR_DEBUG_RXDMAEND(BV_IR_DEBUG_RXDMAEND__##e)
#define BFM_IR_DEBUG_RXDMAEND_V(v) BM_IR_DEBUG_RXDMAEND
#define BP_IR_DEBUG_TXDMAREQ 1
#define BM_IR_DEBUG_TXDMAREQ 0x2
#define BF_IR_DEBUG_TXDMAREQ(v) (((v) & 0x1) << 1)
#define BFM_IR_DEBUG_TXDMAREQ(v) BM_IR_DEBUG_TXDMAREQ
#define BF_IR_DEBUG_TXDMAREQ_V(e) BF_IR_DEBUG_TXDMAREQ(BV_IR_DEBUG_TXDMAREQ__##e)
#define BFM_IR_DEBUG_TXDMAREQ_V(v) BM_IR_DEBUG_TXDMAREQ
#define BP_IR_DEBUG_RXDMAREQ 0
#define BM_IR_DEBUG_RXDMAREQ 0x1
#define BF_IR_DEBUG_RXDMAREQ(v) (((v) & 0x1) << 0)
#define BFM_IR_DEBUG_RXDMAREQ(v) BM_IR_DEBUG_RXDMAREQ
#define BF_IR_DEBUG_RXDMAREQ_V(e) BF_IR_DEBUG_RXDMAREQ(BV_IR_DEBUG_RXDMAREQ__##e)
#define BFM_IR_DEBUG_RXDMAREQ_V(v) BM_IR_DEBUG_RXDMAREQ
#endif /* __HEADERGEN_STMP3600_IR_H__*/
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