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rockbox/firmware/target/arm/imx233/regs/stmp3600/emi.h
Amaury Pouly eac1ca22bd imx233: generate register headers using headergen_v2 and update code for it 
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.

The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
  BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
  BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
  its equivalent for BF_WR(reg_SET, ...)

I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".

Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml

Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-28 16:49:22 +02:00

472 lines
28 KiB
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stmp3600 version: 2.4.0
* stmp3600 authors: Amaury Pouly
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_STMP3600_EMI_H__
#define __HEADERGEN_STMP3600_EMI_H__
#define HW_EMI_CTRL HW(EMI_CTRL)
#define HWA_EMI_CTRL (0x80020000 + 0x0)
#define HWT_EMI_CTRL HWIO_32_RW
#define HWN_EMI_CTRL EMI_CTRL
#define HWI_EMI_CTRL
#define HW_EMI_CTRL_SET HW(EMI_CTRL_SET)
#define HWA_EMI_CTRL_SET (HWA_EMI_CTRL + 0x4)
#define HWT_EMI_CTRL_SET HWIO_32_WO
#define HWN_EMI_CTRL_SET EMI_CTRL
#define HWI_EMI_CTRL_SET
#define HW_EMI_CTRL_CLR HW(EMI_CTRL_CLR)
#define HWA_EMI_CTRL_CLR (HWA_EMI_CTRL + 0x8)
#define HWT_EMI_CTRL_CLR HWIO_32_WO
#define HWN_EMI_CTRL_CLR EMI_CTRL
#define HWI_EMI_CTRL_CLR
#define HW_EMI_CTRL_TOG HW(EMI_CTRL_TOG)
#define HWA_EMI_CTRL_TOG (HWA_EMI_CTRL + 0xc)
#define HWT_EMI_CTRL_TOG HWIO_32_WO
#define HWN_EMI_CTRL_TOG EMI_CTRL
#define HWI_EMI_CTRL_TOG
#define BP_EMI_CTRL_SFTRST 31
#define BM_EMI_CTRL_SFTRST 0x80000000
#define BF_EMI_CTRL_SFTRST(v) (((v) & 0x1) << 31)
#define BFM_EMI_CTRL_SFTRST(v) BM_EMI_CTRL_SFTRST
#define BF_EMI_CTRL_SFTRST_V(e) BF_EMI_CTRL_SFTRST(BV_EMI_CTRL_SFTRST__##e)
#define BFM_EMI_CTRL_SFTRST_V(v) BM_EMI_CTRL_SFTRST
#define BP_EMI_CTRL_CLKGATE 30
#define BM_EMI_CTRL_CLKGATE 0x40000000
#define BF_EMI_CTRL_CLKGATE(v) (((v) & 0x1) << 30)
#define BFM_EMI_CTRL_CLKGATE(v) BM_EMI_CTRL_CLKGATE
#define BF_EMI_CTRL_CLKGATE_V(e) BF_EMI_CTRL_CLKGATE(BV_EMI_CTRL_CLKGATE__##e)
#define BFM_EMI_CTRL_CLKGATE_V(v) BM_EMI_CTRL_CLKGATE
#define BP_EMI_CTRL_CE3_MODE 3
#define BM_EMI_CTRL_CE3_MODE 0x8
#define BV_EMI_CTRL_CE3_MODE__STATIC 0x0
#define BV_EMI_CTRL_CE3_MODE__DRAM 0x1
#define BF_EMI_CTRL_CE3_MODE(v) (((v) & 0x1) << 3)
#define BFM_EMI_CTRL_CE3_MODE(v) BM_EMI_CTRL_CE3_MODE
#define BF_EMI_CTRL_CE3_MODE_V(e) BF_EMI_CTRL_CE3_MODE(BV_EMI_CTRL_CE3_MODE__##e)
#define BFM_EMI_CTRL_CE3_MODE_V(v) BM_EMI_CTRL_CE3_MODE
#define BP_EMI_CTRL_CE2_MODE 2
#define BM_EMI_CTRL_CE2_MODE 0x4
#define BV_EMI_CTRL_CE2_MODE__STATIC 0x0
#define BV_EMI_CTRL_CE2_MODE__DRAM 0x1
#define BF_EMI_CTRL_CE2_MODE(v) (((v) & 0x1) << 2)
#define BFM_EMI_CTRL_CE2_MODE(v) BM_EMI_CTRL_CE2_MODE
#define BF_EMI_CTRL_CE2_MODE_V(e) BF_EMI_CTRL_CE2_MODE(BV_EMI_CTRL_CE2_MODE__##e)
#define BFM_EMI_CTRL_CE2_MODE_V(v) BM_EMI_CTRL_CE2_MODE
#define BP_EMI_CTRL_CE1_MODE 1
#define BM_EMI_CTRL_CE1_MODE 0x2
#define BV_EMI_CTRL_CE1_MODE__STATIC 0x0
#define BV_EMI_CTRL_CE1_MODE__DRAM 0x1
#define BF_EMI_CTRL_CE1_MODE(v) (((v) & 0x1) << 1)
#define BFM_EMI_CTRL_CE1_MODE(v) BM_EMI_CTRL_CE1_MODE
#define BF_EMI_CTRL_CE1_MODE_V(e) BF_EMI_CTRL_CE1_MODE(BV_EMI_CTRL_CE1_MODE__##e)
#define BFM_EMI_CTRL_CE1_MODE_V(v) BM_EMI_CTRL_CE1_MODE
#define BP_EMI_CTRL_CE0_MODE 0
#define BM_EMI_CTRL_CE0_MODE 0x1
#define BV_EMI_CTRL_CE0_MODE__STATIC 0x0
#define BV_EMI_CTRL_CE0_MODE__DRAM 0x1
#define BF_EMI_CTRL_CE0_MODE(v) (((v) & 0x1) << 0)
#define BFM_EMI_CTRL_CE0_MODE(v) BM_EMI_CTRL_CE0_MODE
#define BF_EMI_CTRL_CE0_MODE_V(e) BF_EMI_CTRL_CE0_MODE(BV_EMI_CTRL_CE0_MODE__##e)
#define BFM_EMI_CTRL_CE0_MODE_V(v) BM_EMI_CTRL_CE0_MODE
#define HW_EMI_STAT HW(EMI_STAT)
#define HWA_EMI_STAT (0x80020000 + 0x10)
#define HWT_EMI_STAT HWIO_32_RW
#define HWN_EMI_STAT EMI_STAT
#define HWI_EMI_STAT
#define BP_EMI_STAT_DRAM_PRESENT 31
#define BM_EMI_STAT_DRAM_PRESENT 0x80000000
#define BF_EMI_STAT_DRAM_PRESENT(v) (((v) & 0x1) << 31)
#define BFM_EMI_STAT_DRAM_PRESENT(v) BM_EMI_STAT_DRAM_PRESENT
#define BF_EMI_STAT_DRAM_PRESENT_V(e) BF_EMI_STAT_DRAM_PRESENT(BV_EMI_STAT_DRAM_PRESENT__##e)
#define BFM_EMI_STAT_DRAM_PRESENT_V(v) BM_EMI_STAT_DRAM_PRESENT
#define BP_EMI_STAT_STATIC_PRESENT 30
#define BM_EMI_STAT_STATIC_PRESENT 0x40000000
#define BF_EMI_STAT_STATIC_PRESENT(v) (((v) & 0x1) << 30)
#define BFM_EMI_STAT_STATIC_PRESENT(v) BM_EMI_STAT_STATIC_PRESENT
#define BF_EMI_STAT_STATIC_PRESENT_V(e) BF_EMI_STAT_STATIC_PRESENT(BV_EMI_STAT_STATIC_PRESENT__##e)
#define BFM_EMI_STAT_STATIC_PRESENT_V(v) BM_EMI_STAT_STATIC_PRESENT
#define BP_EMI_STAT_LARGE_DRAM_ENABLED 29
#define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000
#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v) (((v) & 0x1) << 29)
#define BFM_EMI_STAT_LARGE_DRAM_ENABLED(v) BM_EMI_STAT_LARGE_DRAM_ENABLED
#define BF_EMI_STAT_LARGE_DRAM_ENABLED_V(e) BF_EMI_STAT_LARGE_DRAM_ENABLED(BV_EMI_STAT_LARGE_DRAM_ENABLED__##e)
#define BFM_EMI_STAT_LARGE_DRAM_ENABLED_V(v) BM_EMI_STAT_LARGE_DRAM_ENABLED
#define BP_EMI_STAT_WRITE_BUFFER_DATA 1
#define BM_EMI_STAT_WRITE_BUFFER_DATA 0x2
#define BV_EMI_STAT_WRITE_BUFFER_DATA__EMPTY 0x0
#define BV_EMI_STAT_WRITE_BUFFER_DATA__NOT_EMPTY 0x1
#define BF_EMI_STAT_WRITE_BUFFER_DATA(v) (((v) & 0x1) << 1)
#define BFM_EMI_STAT_WRITE_BUFFER_DATA(v) BM_EMI_STAT_WRITE_BUFFER_DATA
#define BF_EMI_STAT_WRITE_BUFFER_DATA_V(e) BF_EMI_STAT_WRITE_BUFFER_DATA(BV_EMI_STAT_WRITE_BUFFER_DATA__##e)
#define BFM_EMI_STAT_WRITE_BUFFER_DATA_V(v) BM_EMI_STAT_WRITE_BUFFER_DATA
#define BP_EMI_STAT_BUSY 0
#define BM_EMI_STAT_BUSY 0x1
#define BV_EMI_STAT_BUSY__NOT_BUSY 0x0
#define BV_EMI_STAT_BUSY__BUSY 0x1
#define BF_EMI_STAT_BUSY(v) (((v) & 0x1) << 0)
#define BFM_EMI_STAT_BUSY(v) BM_EMI_STAT_BUSY
#define BF_EMI_STAT_BUSY_V(e) BF_EMI_STAT_BUSY(BV_EMI_STAT_BUSY__##e)
#define BFM_EMI_STAT_BUSY_V(v) BM_EMI_STAT_BUSY
#define HW_EMI_DEBUG HW(EMI_DEBUG)
#define HWA_EMI_DEBUG (0x80020000 + 0x20)
#define HWT_EMI_DEBUG HWIO_32_RW
#define HWN_EMI_DEBUG EMI_DEBUG
#define HWI_EMI_DEBUG
#define BP_EMI_DEBUG_STATIC_STATE 16
#define BM_EMI_DEBUG_STATIC_STATE 0x70000
#define BF_EMI_DEBUG_STATIC_STATE(v) (((v) & 0x7) << 16)
#define BFM_EMI_DEBUG_STATIC_STATE(v) BM_EMI_DEBUG_STATIC_STATE
#define BF_EMI_DEBUG_STATIC_STATE_V(e) BF_EMI_DEBUG_STATIC_STATE(BV_EMI_DEBUG_STATIC_STATE__##e)
#define BFM_EMI_DEBUG_STATIC_STATE_V(v) BM_EMI_DEBUG_STATIC_STATE
#define BP_EMI_DEBUG_DRAM_STATE 0
#define BM_EMI_DEBUG_DRAM_STATE 0x1f
#define BF_EMI_DEBUG_DRAM_STATE(v) (((v) & 0x1f) << 0)
#define BFM_EMI_DEBUG_DRAM_STATE(v) BM_EMI_DEBUG_DRAM_STATE
#define BF_EMI_DEBUG_DRAM_STATE_V(e) BF_EMI_DEBUG_DRAM_STATE(BV_EMI_DEBUG_DRAM_STATE__##e)
#define BFM_EMI_DEBUG_DRAM_STATE_V(v) BM_EMI_DEBUG_DRAM_STATE
#define HW_EMI_DRAMSTAT HW(EMI_DRAMSTAT)
#define HWA_EMI_DRAMSTAT (0x80020000 + 0x80)
#define HWT_EMI_DRAMSTAT HWIO_32_RW
#define HWN_EMI_DRAMSTAT EMI_DRAMSTAT
#define HWI_EMI_DRAMSTAT
#define BP_EMI_DRAMSTAT_SELF_REFRESH_ACK 2
#define BM_EMI_DRAMSTAT_SELF_REFRESH_ACK 0x4
#define BF_EMI_DRAMSTAT_SELF_REFRESH_ACK(v) (((v) & 0x1) << 2)
#define BFM_EMI_DRAMSTAT_SELF_REFRESH_ACK(v) BM_EMI_DRAMSTAT_SELF_REFRESH_ACK
#define BF_EMI_DRAMSTAT_SELF_REFRESH_ACK_V(e) BF_EMI_DRAMSTAT_SELF_REFRESH_ACK(BV_EMI_DRAMSTAT_SELF_REFRESH_ACK__##e)
#define BFM_EMI_DRAMSTAT_SELF_REFRESH_ACK_V(v) BM_EMI_DRAMSTAT_SELF_REFRESH_ACK
#define BP_EMI_DRAMSTAT_BUSY 1
#define BM_EMI_DRAMSTAT_BUSY 0x2
#define BF_EMI_DRAMSTAT_BUSY(v) (((v) & 0x1) << 1)
#define BFM_EMI_DRAMSTAT_BUSY(v) BM_EMI_DRAMSTAT_BUSY
#define BF_EMI_DRAMSTAT_BUSY_V(e) BF_EMI_DRAMSTAT_BUSY(BV_EMI_DRAMSTAT_BUSY__##e)
#define BFM_EMI_DRAMSTAT_BUSY_V(v) BM_EMI_DRAMSTAT_BUSY
#define BP_EMI_DRAMSTAT_READY 0
#define BM_EMI_DRAMSTAT_READY 0x1
#define BF_EMI_DRAMSTAT_READY(v) (((v) & 0x1) << 0)
#define BFM_EMI_DRAMSTAT_READY(v) BM_EMI_DRAMSTAT_READY
#define BF_EMI_DRAMSTAT_READY_V(e) BF_EMI_DRAMSTAT_READY(BV_EMI_DRAMSTAT_READY__##e)
#define BFM_EMI_DRAMSTAT_READY_V(v) BM_EMI_DRAMSTAT_READY
#define HW_EMI_DRAMCTRL HW(EMI_DRAMCTRL)
#define HWA_EMI_DRAMCTRL (0x80020000 + 0x90)
#define HWT_EMI_DRAMCTRL HWIO_32_RW
#define HWN_EMI_DRAMCTRL EMI_DRAMCTRL
#define HWI_EMI_DRAMCTRL
#define HW_EMI_DRAMCTRL_SET HW(EMI_DRAMCTRL_SET)
#define HWA_EMI_DRAMCTRL_SET (HWA_EMI_DRAMCTRL + 0x4)
#define HWT_EMI_DRAMCTRL_SET HWIO_32_WO
#define HWN_EMI_DRAMCTRL_SET EMI_DRAMCTRL
#define HWI_EMI_DRAMCTRL_SET
#define HW_EMI_DRAMCTRL_CLR HW(EMI_DRAMCTRL_CLR)
#define HWA_EMI_DRAMCTRL_CLR (HWA_EMI_DRAMCTRL + 0x8)
#define HWT_EMI_DRAMCTRL_CLR HWIO_32_WO
#define HWN_EMI_DRAMCTRL_CLR EMI_DRAMCTRL
#define HWI_EMI_DRAMCTRL_CLR
#define HW_EMI_DRAMCTRL_TOG HW(EMI_DRAMCTRL_TOG)
#define HWA_EMI_DRAMCTRL_TOG (HWA_EMI_DRAMCTRL + 0xc)
#define HWT_EMI_DRAMCTRL_TOG HWIO_32_WO
#define HWN_EMI_DRAMCTRL_TOG EMI_DRAMCTRL
#define HWI_EMI_DRAMCTRL_TOG
#define BP_EMI_DRAMCTRL_EMICLK_DIVIDE 24
#define BM_EMI_DRAMCTRL_EMICLK_DIVIDE 0x7000000
#define BF_EMI_DRAMCTRL_EMICLK_DIVIDE(v) (((v) & 0x7) << 24)
#define BFM_EMI_DRAMCTRL_EMICLK_DIVIDE(v) BM_EMI_DRAMCTRL_EMICLK_DIVIDE
#define BF_EMI_DRAMCTRL_EMICLK_DIVIDE_V(e) BF_EMI_DRAMCTRL_EMICLK_DIVIDE(BV_EMI_DRAMCTRL_EMICLK_DIVIDE__##e)
#define BFM_EMI_DRAMCTRL_EMICLK_DIVIDE_V(v) BM_EMI_DRAMCTRL_EMICLK_DIVIDE
#define BP_EMI_DRAMCTRL_AUTO_EMICLK_GATE 23
#define BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE 0x800000
#define BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE(v) (((v) & 0x1) << 23)
#define BFM_EMI_DRAMCTRL_AUTO_EMICLK_GATE(v) BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE
#define BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE_V(e) BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE(BV_EMI_DRAMCTRL_AUTO_EMICLK_GATE__##e)
#define BFM_EMI_DRAMCTRL_AUTO_EMICLK_GATE_V(v) BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE
#define BP_EMI_DRAMCTRL_EMICLK_ENABLE 21
#define BM_EMI_DRAMCTRL_EMICLK_ENABLE 0x200000
#define BF_EMI_DRAMCTRL_EMICLK_ENABLE(v) (((v) & 0x1) << 21)
#define BFM_EMI_DRAMCTRL_EMICLK_ENABLE(v) BM_EMI_DRAMCTRL_EMICLK_ENABLE
#define BF_EMI_DRAMCTRL_EMICLK_ENABLE_V(e) BF_EMI_DRAMCTRL_EMICLK_ENABLE(BV_EMI_DRAMCTRL_EMICLK_ENABLE__##e)
#define BFM_EMI_DRAMCTRL_EMICLK_ENABLE_V(v) BM_EMI_DRAMCTRL_EMICLK_ENABLE
#define BP_EMI_DRAMCTRL_EMICLKEN_ENABLE 20
#define BM_EMI_DRAMCTRL_EMICLKEN_ENABLE 0x100000
#define BF_EMI_DRAMCTRL_EMICLKEN_ENABLE(v) (((v) & 0x1) << 20)
#define BFM_EMI_DRAMCTRL_EMICLKEN_ENABLE(v) BM_EMI_DRAMCTRL_EMICLKEN_ENABLE
#define BF_EMI_DRAMCTRL_EMICLKEN_ENABLE_V(e) BF_EMI_DRAMCTRL_EMICLKEN_ENABLE(BV_EMI_DRAMCTRL_EMICLKEN_ENABLE__##e)
#define BFM_EMI_DRAMCTRL_EMICLKEN_ENABLE_V(v) BM_EMI_DRAMCTRL_EMICLKEN_ENABLE
#define BP_EMI_DRAMCTRL_DRAM_TYPE 16
#define BM_EMI_DRAMCTRL_DRAM_TYPE 0xf0000
#define BF_EMI_DRAMCTRL_DRAM_TYPE(v) (((v) & 0xf) << 16)
#define BFM_EMI_DRAMCTRL_DRAM_TYPE(v) BM_EMI_DRAMCTRL_DRAM_TYPE
#define BF_EMI_DRAMCTRL_DRAM_TYPE_V(e) BF_EMI_DRAMCTRL_DRAM_TYPE(BV_EMI_DRAMCTRL_DRAM_TYPE__##e)
#define BFM_EMI_DRAMCTRL_DRAM_TYPE_V(v) BM_EMI_DRAMCTRL_DRAM_TYPE
#define BP_EMI_DRAMCTRL_PRECHARGE 2
#define BM_EMI_DRAMCTRL_PRECHARGE 0x4
#define BF_EMI_DRAMCTRL_PRECHARGE(v) (((v) & 0x1) << 2)
#define BFM_EMI_DRAMCTRL_PRECHARGE(v) BM_EMI_DRAMCTRL_PRECHARGE
#define BF_EMI_DRAMCTRL_PRECHARGE_V(e) BF_EMI_DRAMCTRL_PRECHARGE(BV_EMI_DRAMCTRL_PRECHARGE__##e)
#define BFM_EMI_DRAMCTRL_PRECHARGE_V(v) BM_EMI_DRAMCTRL_PRECHARGE
#define BP_EMI_DRAMCTRL_SELF_REFRESH 1
#define BM_EMI_DRAMCTRL_SELF_REFRESH 0x2
#define BF_EMI_DRAMCTRL_SELF_REFRESH(v) (((v) & 0x1) << 1)
#define BFM_EMI_DRAMCTRL_SELF_REFRESH(v) BM_EMI_DRAMCTRL_SELF_REFRESH
#define BF_EMI_DRAMCTRL_SELF_REFRESH_V(e) BF_EMI_DRAMCTRL_SELF_REFRESH(BV_EMI_DRAMCTRL_SELF_REFRESH__##e)
#define BFM_EMI_DRAMCTRL_SELF_REFRESH_V(v) BM_EMI_DRAMCTRL_SELF_REFRESH
#define HW_EMI_DRAMADDR HW(EMI_DRAMADDR)
#define HWA_EMI_DRAMADDR (0x80020000 + 0xa0)
#define HWT_EMI_DRAMADDR HWIO_32_RW
#define HWN_EMI_DRAMADDR EMI_DRAMADDR
#define HWI_EMI_DRAMADDR
#define HW_EMI_DRAMADDR_SET HW(EMI_DRAMADDR_SET)
#define HWA_EMI_DRAMADDR_SET (HWA_EMI_DRAMADDR + 0x4)
#define HWT_EMI_DRAMADDR_SET HWIO_32_WO
#define HWN_EMI_DRAMADDR_SET EMI_DRAMADDR
#define HWI_EMI_DRAMADDR_SET
#define HW_EMI_DRAMADDR_CLR HW(EMI_DRAMADDR_CLR)
#define HWA_EMI_DRAMADDR_CLR (HWA_EMI_DRAMADDR + 0x8)
#define HWT_EMI_DRAMADDR_CLR HWIO_32_WO
#define HWN_EMI_DRAMADDR_CLR EMI_DRAMADDR
#define HWI_EMI_DRAMADDR_CLR
#define HW_EMI_DRAMADDR_TOG HW(EMI_DRAMADDR_TOG)
#define HWA_EMI_DRAMADDR_TOG (HWA_EMI_DRAMADDR + 0xc)
#define HWT_EMI_DRAMADDR_TOG HWIO_32_WO
#define HWN_EMI_DRAMADDR_TOG EMI_DRAMADDR
#define HWI_EMI_DRAMADDR_TOG
#define BP_EMI_DRAMADDR_MODE 8
#define BM_EMI_DRAMADDR_MODE 0x100
#define BV_EMI_DRAMADDR_MODE__RBC 0x0
#define BV_EMI_DRAMADDR_MODE__BRC 0x1
#define BF_EMI_DRAMADDR_MODE(v) (((v) & 0x1) << 8)
#define BFM_EMI_DRAMADDR_MODE(v) BM_EMI_DRAMADDR_MODE
#define BF_EMI_DRAMADDR_MODE_V(e) BF_EMI_DRAMADDR_MODE(BV_EMI_DRAMADDR_MODE__##e)
#define BFM_EMI_DRAMADDR_MODE_V(v) BM_EMI_DRAMADDR_MODE
#define BP_EMI_DRAMADDR_ROW_BITS 4
#define BM_EMI_DRAMADDR_ROW_BITS 0xf0
#define BF_EMI_DRAMADDR_ROW_BITS(v) (((v) & 0xf) << 4)
#define BFM_EMI_DRAMADDR_ROW_BITS(v) BM_EMI_DRAMADDR_ROW_BITS
#define BF_EMI_DRAMADDR_ROW_BITS_V(e) BF_EMI_DRAMADDR_ROW_BITS(BV_EMI_DRAMADDR_ROW_BITS__##e)
#define BFM_EMI_DRAMADDR_ROW_BITS_V(v) BM_EMI_DRAMADDR_ROW_BITS
#define BP_EMI_DRAMADDR_COLUMN_BITS 0
#define BM_EMI_DRAMADDR_COLUMN_BITS 0xf
#define BF_EMI_DRAMADDR_COLUMN_BITS(v) (((v) & 0xf) << 0)
#define BFM_EMI_DRAMADDR_COLUMN_BITS(v) BM_EMI_DRAMADDR_COLUMN_BITS
#define BF_EMI_DRAMADDR_COLUMN_BITS_V(e) BF_EMI_DRAMADDR_COLUMN_BITS(BV_EMI_DRAMADDR_COLUMN_BITS__##e)
#define BFM_EMI_DRAMADDR_COLUMN_BITS_V(v) BM_EMI_DRAMADDR_COLUMN_BITS
#define HW_EMI_DRAMMODE HW(EMI_DRAMMODE)
#define HWA_EMI_DRAMMODE (0x80020000 + 0xb0)
#define HWT_EMI_DRAMMODE HWIO_32_RW
#define HWN_EMI_DRAMMODE EMI_DRAMMODE
#define HWI_EMI_DRAMMODE
#define BP_EMI_DRAMMODE_CAS_LATENCY 4
#define BM_EMI_DRAMMODE_CAS_LATENCY 0x70
#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED0 0x0
#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED1 0x1
#define BV_EMI_DRAMMODE_CAS_LATENCY__CAS2 0x2
#define BV_EMI_DRAMMODE_CAS_LATENCY__CAS3 0x3
#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED4 0x4
#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED5 0x5
#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED6 0x6
#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED7 0x7
#define BF_EMI_DRAMMODE_CAS_LATENCY(v) (((v) & 0x7) << 4)
#define BFM_EMI_DRAMMODE_CAS_LATENCY(v) BM_EMI_DRAMMODE_CAS_LATENCY
#define BF_EMI_DRAMMODE_CAS_LATENCY_V(e) BF_EMI_DRAMMODE_CAS_LATENCY(BV_EMI_DRAMMODE_CAS_LATENCY__##e)
#define BFM_EMI_DRAMMODE_CAS_LATENCY_V(v) BM_EMI_DRAMMODE_CAS_LATENCY
#define HW_EMI_DRAMTIME HW(EMI_DRAMTIME)
#define HWA_EMI_DRAMTIME (0x80020000 + 0xc0)
#define HWT_EMI_DRAMTIME HWIO_32_RW
#define HWN_EMI_DRAMTIME EMI_DRAMTIME
#define HWI_EMI_DRAMTIME
#define HW_EMI_DRAMTIME_SET HW(EMI_DRAMTIME_SET)
#define HWA_EMI_DRAMTIME_SET (HWA_EMI_DRAMTIME + 0x4)
#define HWT_EMI_DRAMTIME_SET HWIO_32_WO
#define HWN_EMI_DRAMTIME_SET EMI_DRAMTIME
#define HWI_EMI_DRAMTIME_SET
#define HW_EMI_DRAMTIME_CLR HW(EMI_DRAMTIME_CLR)
#define HWA_EMI_DRAMTIME_CLR (HWA_EMI_DRAMTIME + 0x8)
#define HWT_EMI_DRAMTIME_CLR HWIO_32_WO
#define HWN_EMI_DRAMTIME_CLR EMI_DRAMTIME
#define HWI_EMI_DRAMTIME_CLR
#define HW_EMI_DRAMTIME_TOG HW(EMI_DRAMTIME_TOG)
#define HWA_EMI_DRAMTIME_TOG (HWA_EMI_DRAMTIME + 0xc)
#define HWT_EMI_DRAMTIME_TOG HWIO_32_WO
#define HWN_EMI_DRAMTIME_TOG EMI_DRAMTIME
#define HWI_EMI_DRAMTIME_TOG
#define BP_EMI_DRAMTIME_TRFC 24
#define BM_EMI_DRAMTIME_TRFC 0xf000000
#define BF_EMI_DRAMTIME_TRFC(v) (((v) & 0xf) << 24)
#define BFM_EMI_DRAMTIME_TRFC(v) BM_EMI_DRAMTIME_TRFC
#define BF_EMI_DRAMTIME_TRFC_V(e) BF_EMI_DRAMTIME_TRFC(BV_EMI_DRAMTIME_TRFC__##e)
#define BFM_EMI_DRAMTIME_TRFC_V(v) BM_EMI_DRAMTIME_TRFC
#define BP_EMI_DRAMTIME_TRC 20
#define BM_EMI_DRAMTIME_TRC 0xf00000
#define BF_EMI_DRAMTIME_TRC(v) (((v) & 0xf) << 20)
#define BFM_EMI_DRAMTIME_TRC(v) BM_EMI_DRAMTIME_TRC
#define BF_EMI_DRAMTIME_TRC_V(e) BF_EMI_DRAMTIME_TRC(BV_EMI_DRAMTIME_TRC__##e)
#define BFM_EMI_DRAMTIME_TRC_V(v) BM_EMI_DRAMTIME_TRC
#define BP_EMI_DRAMTIME_TRAS 16
#define BM_EMI_DRAMTIME_TRAS 0xf0000
#define BF_EMI_DRAMTIME_TRAS(v) (((v) & 0xf) << 16)
#define BFM_EMI_DRAMTIME_TRAS(v) BM_EMI_DRAMTIME_TRAS
#define BF_EMI_DRAMTIME_TRAS_V(e) BF_EMI_DRAMTIME_TRAS(BV_EMI_DRAMTIME_TRAS__##e)
#define BFM_EMI_DRAMTIME_TRAS_V(v) BM_EMI_DRAMTIME_TRAS
#define BP_EMI_DRAMTIME_TRCD 12
#define BM_EMI_DRAMTIME_TRCD 0xf000
#define BF_EMI_DRAMTIME_TRCD(v) (((v) & 0xf) << 12)
#define BFM_EMI_DRAMTIME_TRCD(v) BM_EMI_DRAMTIME_TRCD
#define BF_EMI_DRAMTIME_TRCD_V(e) BF_EMI_DRAMTIME_TRCD(BV_EMI_DRAMTIME_TRCD__##e)
#define BFM_EMI_DRAMTIME_TRCD_V(v) BM_EMI_DRAMTIME_TRCD
#define BP_EMI_DRAMTIME_TRP 8
#define BM_EMI_DRAMTIME_TRP 0x300
#define BF_EMI_DRAMTIME_TRP(v) (((v) & 0x3) << 8)
#define BFM_EMI_DRAMTIME_TRP(v) BM_EMI_DRAMTIME_TRP
#define BF_EMI_DRAMTIME_TRP_V(e) BF_EMI_DRAMTIME_TRP(BV_EMI_DRAMTIME_TRP__##e)
#define BFM_EMI_DRAMTIME_TRP_V(v) BM_EMI_DRAMTIME_TRP
#define BP_EMI_DRAMTIME_TXSR 4
#define BM_EMI_DRAMTIME_TXSR 0xf0
#define BF_EMI_DRAMTIME_TXSR(v) (((v) & 0xf) << 4)
#define BFM_EMI_DRAMTIME_TXSR(v) BM_EMI_DRAMTIME_TXSR
#define BF_EMI_DRAMTIME_TXSR_V(e) BF_EMI_DRAMTIME_TXSR(BV_EMI_DRAMTIME_TXSR__##e)
#define BFM_EMI_DRAMTIME_TXSR_V(v) BM_EMI_DRAMTIME_TXSR
#define BP_EMI_DRAMTIME_REFRESH_COUNTER 0
#define BM_EMI_DRAMTIME_REFRESH_COUNTER 0xf
#define BF_EMI_DRAMTIME_REFRESH_COUNTER(v) (((v) & 0xf) << 0)
#define BFM_EMI_DRAMTIME_REFRESH_COUNTER(v) BM_EMI_DRAMTIME_REFRESH_COUNTER
#define BF_EMI_DRAMTIME_REFRESH_COUNTER_V(e) BF_EMI_DRAMTIME_REFRESH_COUNTER(BV_EMI_DRAMTIME_REFRESH_COUNTER__##e)
#define BFM_EMI_DRAMTIME_REFRESH_COUNTER_V(v) BM_EMI_DRAMTIME_REFRESH_COUNTER
#define HW_EMI_DRAMTIME2 HW(EMI_DRAMTIME2)
#define HWA_EMI_DRAMTIME2 (0x80020000 + 0xd0)
#define HWT_EMI_DRAMTIME2 HWIO_32_RW
#define HWN_EMI_DRAMTIME2 EMI_DRAMTIME2
#define HWI_EMI_DRAMTIME2
#define HW_EMI_DRAMTIME2_SET HW(EMI_DRAMTIME2_SET)
#define HWA_EMI_DRAMTIME2_SET (HWA_EMI_DRAMTIME2 + 0x4)
#define HWT_EMI_DRAMTIME2_SET HWIO_32_WO
#define HWN_EMI_DRAMTIME2_SET EMI_DRAMTIME2
#define HWI_EMI_DRAMTIME2_SET
#define HW_EMI_DRAMTIME2_CLR HW(EMI_DRAMTIME2_CLR)
#define HWA_EMI_DRAMTIME2_CLR (HWA_EMI_DRAMTIME2 + 0x8)
#define HWT_EMI_DRAMTIME2_CLR HWIO_32_WO
#define HWN_EMI_DRAMTIME2_CLR EMI_DRAMTIME2
#define HWI_EMI_DRAMTIME2_CLR
#define HW_EMI_DRAMTIME2_TOG HW(EMI_DRAMTIME2_TOG)
#define HWA_EMI_DRAMTIME2_TOG (HWA_EMI_DRAMTIME2 + 0xc)
#define HWT_EMI_DRAMTIME2_TOG HWIO_32_WO
#define HWN_EMI_DRAMTIME2_TOG EMI_DRAMTIME2
#define HWI_EMI_DRAMTIME2_TOG
#define BP_EMI_DRAMTIME2_PRECHARGE_COUNT 0
#define BM_EMI_DRAMTIME2_PRECHARGE_COUNT 0xffff
#define BF_EMI_DRAMTIME2_PRECHARGE_COUNT(v) (((v) & 0xffff) << 0)
#define BFM_EMI_DRAMTIME2_PRECHARGE_COUNT(v) BM_EMI_DRAMTIME2_PRECHARGE_COUNT
#define BF_EMI_DRAMTIME2_PRECHARGE_COUNT_V(e) BF_EMI_DRAMTIME2_PRECHARGE_COUNT(BV_EMI_DRAMTIME2_PRECHARGE_COUNT__##e)
#define BFM_EMI_DRAMTIME2_PRECHARGE_COUNT_V(v) BM_EMI_DRAMTIME2_PRECHARGE_COUNT
#define HW_EMI_STATICCTRL HW(EMI_STATICCTRL)
#define HWA_EMI_STATICCTRL (0x80020000 + 0x100)
#define HWT_EMI_STATICCTRL HWIO_32_RW
#define HWN_EMI_STATICCTRL EMI_STATICCTRL
#define HWI_EMI_STATICCTRL
#define HW_EMI_STATICCTRL_SET HW(EMI_STATICCTRL_SET)
#define HWA_EMI_STATICCTRL_SET (HWA_EMI_STATICCTRL + 0x4)
#define HWT_EMI_STATICCTRL_SET HWIO_32_WO
#define HWN_EMI_STATICCTRL_SET EMI_STATICCTRL
#define HWI_EMI_STATICCTRL_SET
#define HW_EMI_STATICCTRL_CLR HW(EMI_STATICCTRL_CLR)
#define HWA_EMI_STATICCTRL_CLR (HWA_EMI_STATICCTRL + 0x8)
#define HWT_EMI_STATICCTRL_CLR HWIO_32_WO
#define HWN_EMI_STATICCTRL_CLR EMI_STATICCTRL
#define HWI_EMI_STATICCTRL_CLR
#define HW_EMI_STATICCTRL_TOG HW(EMI_STATICCTRL_TOG)
#define HWA_EMI_STATICCTRL_TOG (HWA_EMI_STATICCTRL + 0xc)
#define HWT_EMI_STATICCTRL_TOG HWIO_32_WO
#define HWN_EMI_STATICCTRL_TOG EMI_STATICCTRL
#define HWI_EMI_STATICCTRL_TOG
#define BP_EMI_STATICCTRL_MEM_WIDTH 2
#define BM_EMI_STATICCTRL_MEM_WIDTH 0x4
#define BF_EMI_STATICCTRL_MEM_WIDTH(v) (((v) & 0x1) << 2)
#define BFM_EMI_STATICCTRL_MEM_WIDTH(v) BM_EMI_STATICCTRL_MEM_WIDTH
#define BF_EMI_STATICCTRL_MEM_WIDTH_V(e) BF_EMI_STATICCTRL_MEM_WIDTH(BV_EMI_STATICCTRL_MEM_WIDTH__##e)
#define BFM_EMI_STATICCTRL_MEM_WIDTH_V(v) BM_EMI_STATICCTRL_MEM_WIDTH
#define BP_EMI_STATICCTRL_WRITE_PROTECT 1
#define BM_EMI_STATICCTRL_WRITE_PROTECT 0x2
#define BF_EMI_STATICCTRL_WRITE_PROTECT(v) (((v) & 0x1) << 1)
#define BFM_EMI_STATICCTRL_WRITE_PROTECT(v) BM_EMI_STATICCTRL_WRITE_PROTECT
#define BF_EMI_STATICCTRL_WRITE_PROTECT_V(e) BF_EMI_STATICCTRL_WRITE_PROTECT(BV_EMI_STATICCTRL_WRITE_PROTECT__##e)
#define BFM_EMI_STATICCTRL_WRITE_PROTECT_V(v) BM_EMI_STATICCTRL_WRITE_PROTECT
#define BP_EMI_STATICCTRL_RESET_OUT 0
#define BM_EMI_STATICCTRL_RESET_OUT 0x1
#define BF_EMI_STATICCTRL_RESET_OUT(v) (((v) & 0x1) << 0)
#define BFM_EMI_STATICCTRL_RESET_OUT(v) BM_EMI_STATICCTRL_RESET_OUT
#define BF_EMI_STATICCTRL_RESET_OUT_V(e) BF_EMI_STATICCTRL_RESET_OUT(BV_EMI_STATICCTRL_RESET_OUT__##e)
#define BFM_EMI_STATICCTRL_RESET_OUT_V(v) BM_EMI_STATICCTRL_RESET_OUT
#define HW_EMI_STATICTIME HW(EMI_STATICTIME)
#define HWA_EMI_STATICTIME (0x80020000 + 0x110)
#define HWT_EMI_STATICTIME HWIO_32_RW
#define HWN_EMI_STATICTIME EMI_STATICTIME
#define HWI_EMI_STATICTIME
#define HW_EMI_STATICTIME_SET HW(EMI_STATICTIME_SET)
#define HWA_EMI_STATICTIME_SET (HWA_EMI_STATICTIME + 0x4)
#define HWT_EMI_STATICTIME_SET HWIO_32_WO
#define HWN_EMI_STATICTIME_SET EMI_STATICTIME
#define HWI_EMI_STATICTIME_SET
#define HW_EMI_STATICTIME_CLR HW(EMI_STATICTIME_CLR)
#define HWA_EMI_STATICTIME_CLR (HWA_EMI_STATICTIME + 0x8)
#define HWT_EMI_STATICTIME_CLR HWIO_32_WO
#define HWN_EMI_STATICTIME_CLR EMI_STATICTIME
#define HWI_EMI_STATICTIME_CLR
#define HW_EMI_STATICTIME_TOG HW(EMI_STATICTIME_TOG)
#define HWA_EMI_STATICTIME_TOG (HWA_EMI_STATICTIME + 0xc)
#define HWT_EMI_STATICTIME_TOG HWIO_32_WO
#define HWN_EMI_STATICTIME_TOG EMI_STATICTIME
#define HWI_EMI_STATICTIME_TOG
#define BP_EMI_STATICTIME_THZ 24
#define BM_EMI_STATICTIME_THZ 0xf000000
#define BF_EMI_STATICTIME_THZ(v) (((v) & 0xf) << 24)
#define BFM_EMI_STATICTIME_THZ(v) BM_EMI_STATICTIME_THZ
#define BF_EMI_STATICTIME_THZ_V(e) BF_EMI_STATICTIME_THZ(BV_EMI_STATICTIME_THZ__##e)
#define BFM_EMI_STATICTIME_THZ_V(v) BM_EMI_STATICTIME_THZ
#define BP_EMI_STATICTIME_TDH 16
#define BM_EMI_STATICTIME_TDH 0xf0000
#define BF_EMI_STATICTIME_TDH(v) (((v) & 0xf) << 16)
#define BFM_EMI_STATICTIME_TDH(v) BM_EMI_STATICTIME_TDH
#define BF_EMI_STATICTIME_TDH_V(e) BF_EMI_STATICTIME_TDH(BV_EMI_STATICTIME_TDH__##e)
#define BFM_EMI_STATICTIME_TDH_V(v) BM_EMI_STATICTIME_TDH
#define BP_EMI_STATICTIME_TDS 8
#define BM_EMI_STATICTIME_TDS 0xf00
#define BF_EMI_STATICTIME_TDS(v) (((v) & 0xf) << 8)
#define BFM_EMI_STATICTIME_TDS(v) BM_EMI_STATICTIME_TDS
#define BF_EMI_STATICTIME_TDS_V(e) BF_EMI_STATICTIME_TDS(BV_EMI_STATICTIME_TDS__##e)
#define BFM_EMI_STATICTIME_TDS_V(v) BM_EMI_STATICTIME_TDS
#define BP_EMI_STATICTIME_TAS 0
#define BM_EMI_STATICTIME_TAS 0xf
#define BF_EMI_STATICTIME_TAS(v) (((v) & 0xf) << 0)
#define BFM_EMI_STATICTIME_TAS(v) BM_EMI_STATICTIME_TAS
#define BF_EMI_STATICTIME_TAS_V(e) BF_EMI_STATICTIME_TAS(BV_EMI_STATICTIME_TAS__##e)
#define BFM_EMI_STATICTIME_TAS_V(v) BM_EMI_STATICTIME_TAS
#endif /* __HEADERGEN_STMP3600_EMI_H__*/
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