eac1ca22bd
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
855 lines
56 KiB
C
855 lines
56 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* stmp3600 version: 2.4.0
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* stmp3600 authors: Amaury Pouly
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_STMP3600_DIGCTL_H__
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#define __HEADERGEN_STMP3600_DIGCTL_H__
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#define HW_DIGCTL_CTRL HW(DIGCTL_CTRL)
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#define HWA_DIGCTL_CTRL (0x8001c000 + 0x0)
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#define HWT_DIGCTL_CTRL HWIO_32_RW
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#define HWN_DIGCTL_CTRL DIGCTL_CTRL
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#define HWI_DIGCTL_CTRL
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#define HW_DIGCTL_CTRL_SET HW(DIGCTL_CTRL_SET)
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#define HWA_DIGCTL_CTRL_SET (HWA_DIGCTL_CTRL + 0x4)
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#define HWT_DIGCTL_CTRL_SET HWIO_32_WO
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#define HWN_DIGCTL_CTRL_SET DIGCTL_CTRL
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#define HWI_DIGCTL_CTRL_SET
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#define HW_DIGCTL_CTRL_CLR HW(DIGCTL_CTRL_CLR)
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#define HWA_DIGCTL_CTRL_CLR (HWA_DIGCTL_CTRL + 0x8)
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#define HWT_DIGCTL_CTRL_CLR HWIO_32_WO
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#define HWN_DIGCTL_CTRL_CLR DIGCTL_CTRL
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#define HWI_DIGCTL_CTRL_CLR
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#define HW_DIGCTL_CTRL_TOG HW(DIGCTL_CTRL_TOG)
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#define HWA_DIGCTL_CTRL_TOG (HWA_DIGCTL_CTRL + 0xc)
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#define HWT_DIGCTL_CTRL_TOG HWIO_32_WO
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#define HWN_DIGCTL_CTRL_TOG DIGCTL_CTRL
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#define HWI_DIGCTL_CTRL_TOG
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#define BP_DIGCTL_CTRL_MASTER_SELECT 24
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#define BM_DIGCTL_CTRL_MASTER_SELECT 0x1f000000
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#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_I 0x1
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#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_D 0x2
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#define BV_DIGCTL_CTRL_MASTER_SELECT__USB 0x4
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#define BV_DIGCTL_CTRL_MASTER_SELECT__APBH 0x8
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#define BV_DIGCTL_CTRL_MASTER_SELECT__APBX 0x10
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#define BF_DIGCTL_CTRL_MASTER_SELECT(v) (((v) & 0x1f) << 24)
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#define BFM_DIGCTL_CTRL_MASTER_SELECT(v) BM_DIGCTL_CTRL_MASTER_SELECT
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#define BF_DIGCTL_CTRL_MASTER_SELECT_V(e) BF_DIGCTL_CTRL_MASTER_SELECT(BV_DIGCTL_CTRL_MASTER_SELECT__##e)
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#define BFM_DIGCTL_CTRL_MASTER_SELECT_V(v) BM_DIGCTL_CTRL_MASTER_SELECT
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#define BP_DIGCTL_CTRL_USB_TESTMODE 20
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#define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000
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#define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) & 0x1) << 20)
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#define BFM_DIGCTL_CTRL_USB_TESTMODE(v) BM_DIGCTL_CTRL_USB_TESTMODE
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#define BF_DIGCTL_CTRL_USB_TESTMODE_V(e) BF_DIGCTL_CTRL_USB_TESTMODE(BV_DIGCTL_CTRL_USB_TESTMODE__##e)
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#define BFM_DIGCTL_CTRL_USB_TESTMODE_V(v) BM_DIGCTL_CTRL_USB_TESTMODE
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#define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19
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#define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000
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#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) & 0x1) << 19)
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#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE(v) BM_DIGCTL_CTRL_ANALOG_TESTMODE
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#define BF_DIGCTL_CTRL_ANALOG_TESTMODE_V(e) BF_DIGCTL_CTRL_ANALOG_TESTMODE(BV_DIGCTL_CTRL_ANALOG_TESTMODE__##e)
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#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE_V(v) BM_DIGCTL_CTRL_ANALOG_TESTMODE
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#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18
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#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000
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#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) & 0x1) << 18)
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#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE(v) BM_DIGCTL_CTRL_DIGITAL_TESTMODE
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#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE_V(e) BF_DIGCTL_CTRL_DIGITAL_TESTMODE(BV_DIGCTL_CTRL_DIGITAL_TESTMODE__##e)
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#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE_V(v) BM_DIGCTL_CTRL_DIGITAL_TESTMODE
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#define BP_DIGCTL_CTRL_UTMI_TESTMODE 17
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#define BM_DIGCTL_CTRL_UTMI_TESTMODE 0x20000
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#define BF_DIGCTL_CTRL_UTMI_TESTMODE(v) (((v) & 0x1) << 17)
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#define BFM_DIGCTL_CTRL_UTMI_TESTMODE(v) BM_DIGCTL_CTRL_UTMI_TESTMODE
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#define BF_DIGCTL_CTRL_UTMI_TESTMODE_V(e) BF_DIGCTL_CTRL_UTMI_TESTMODE(BV_DIGCTL_CTRL_UTMI_TESTMODE__##e)
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#define BFM_DIGCTL_CTRL_UTMI_TESTMODE_V(v) BM_DIGCTL_CTRL_UTMI_TESTMODE
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#define BP_DIGCTL_CTRL_UART_LOOPBACK 16
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#define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000
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#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0
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#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1
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#define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) & 0x1) << 16)
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#define BFM_DIGCTL_CTRL_UART_LOOPBACK(v) BM_DIGCTL_CTRL_UART_LOOPBACK
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#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(e) BF_DIGCTL_CTRL_UART_LOOPBACK(BV_DIGCTL_CTRL_UART_LOOPBACK__##e)
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#define BFM_DIGCTL_CTRL_UART_LOOPBACK_V(v) BM_DIGCTL_CTRL_UART_LOOPBACK
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#define BP_DIGCTL_CTRL_DEBUG_DISABLE 3
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#define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8
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#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) & 0x1) << 3)
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#define BFM_DIGCTL_CTRL_DEBUG_DISABLE(v) BM_DIGCTL_CTRL_DEBUG_DISABLE
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#define BF_DIGCTL_CTRL_DEBUG_DISABLE_V(e) BF_DIGCTL_CTRL_DEBUG_DISABLE(BV_DIGCTL_CTRL_DEBUG_DISABLE__##e)
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#define BFM_DIGCTL_CTRL_DEBUG_DISABLE_V(v) BM_DIGCTL_CTRL_DEBUG_DISABLE
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#define BP_DIGCTL_CTRL_USB_CLKGATE 2
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#define BM_DIGCTL_CTRL_USB_CLKGATE 0x4
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#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0
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#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1
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#define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) & 0x1) << 2)
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#define BFM_DIGCTL_CTRL_USB_CLKGATE(v) BM_DIGCTL_CTRL_USB_CLKGATE
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#define BF_DIGCTL_CTRL_USB_CLKGATE_V(e) BF_DIGCTL_CTRL_USB_CLKGATE(BV_DIGCTL_CTRL_USB_CLKGATE__##e)
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#define BFM_DIGCTL_CTRL_USB_CLKGATE_V(v) BM_DIGCTL_CTRL_USB_CLKGATE
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#define BP_DIGCTL_CTRL_JTAG_SHIELD 1
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#define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2
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#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0
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#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1
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#define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) & 0x1) << 1)
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#define BFM_DIGCTL_CTRL_JTAG_SHIELD(v) BM_DIGCTL_CTRL_JTAG_SHIELD
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#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(e) BF_DIGCTL_CTRL_JTAG_SHIELD(BV_DIGCTL_CTRL_JTAG_SHIELD__##e)
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#define BFM_DIGCTL_CTRL_JTAG_SHIELD_V(v) BM_DIGCTL_CTRL_JTAG_SHIELD
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#define BP_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0
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#define BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0x1
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#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__DISABLE 0x0
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#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__ENABLE 0x1
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#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v) (((v) & 0x1) << 0)
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#define BFM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v) BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE
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#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(e) BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__##e)
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#define BFM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(v) BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE
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#define HW_DIGCTL_STATUS HW(DIGCTL_STATUS)
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#define HWA_DIGCTL_STATUS (0x8001c000 + 0x10)
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#define HWT_DIGCTL_STATUS HWIO_32_RW
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#define HWN_DIGCTL_STATUS DIGCTL_STATUS
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#define HWI_DIGCTL_STATUS
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#define BP_DIGCTL_STATUS_ROM_KEYS_PRESENT 31
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#define BM_DIGCTL_STATUS_ROM_KEYS_PRESENT 0x80000000
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#define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(v) (((v) & 0x1) << 31)
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#define BFM_DIGCTL_STATUS_ROM_KEYS_PRESENT(v) BM_DIGCTL_STATUS_ROM_KEYS_PRESENT
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#define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT_V(e) BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(BV_DIGCTL_STATUS_ROM_KEYS_PRESENT__##e)
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#define BFM_DIGCTL_STATUS_ROM_KEYS_PRESENT_V(v) BM_DIGCTL_STATUS_ROM_KEYS_PRESENT
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#define BP_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 6
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#define BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 0x40
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#define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) (((v) & 0x1) << 6)
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#define BFM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT
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#define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT_V(e) BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(BV_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT__##e)
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#define BFM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT_V(v) BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT
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#define BP_DIGCTL_STATUS_ROM_SHIELDED 5
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#define BM_DIGCTL_STATUS_ROM_SHIELDED 0x20
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#define BF_DIGCTL_STATUS_ROM_SHIELDED(v) (((v) & 0x1) << 5)
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#define BFM_DIGCTL_STATUS_ROM_SHIELDED(v) BM_DIGCTL_STATUS_ROM_SHIELDED
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#define BF_DIGCTL_STATUS_ROM_SHIELDED_V(e) BF_DIGCTL_STATUS_ROM_SHIELDED(BV_DIGCTL_STATUS_ROM_SHIELDED__##e)
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#define BFM_DIGCTL_STATUS_ROM_SHIELDED_V(v) BM_DIGCTL_STATUS_ROM_SHIELDED
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#define BP_DIGCTL_STATUS_JTAG_IN_USE 4
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#define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10
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#define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) & 0x1) << 4)
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#define BFM_DIGCTL_STATUS_JTAG_IN_USE(v) BM_DIGCTL_STATUS_JTAG_IN_USE
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#define BF_DIGCTL_STATUS_JTAG_IN_USE_V(e) BF_DIGCTL_STATUS_JTAG_IN_USE(BV_DIGCTL_STATUS_JTAG_IN_USE__##e)
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#define BFM_DIGCTL_STATUS_JTAG_IN_USE_V(v) BM_DIGCTL_STATUS_JTAG_IN_USE
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#define BP_DIGCTL_STATUS_PSWITCH 2
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#define BM_DIGCTL_STATUS_PSWITCH 0xc
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#define BF_DIGCTL_STATUS_PSWITCH(v) (((v) & 0x3) << 2)
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#define BFM_DIGCTL_STATUS_PSWITCH(v) BM_DIGCTL_STATUS_PSWITCH
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#define BF_DIGCTL_STATUS_PSWITCH_V(e) BF_DIGCTL_STATUS_PSWITCH(BV_DIGCTL_STATUS_PSWITCH__##e)
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#define BFM_DIGCTL_STATUS_PSWITCH_V(v) BM_DIGCTL_STATUS_PSWITCH
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#define BP_DIGCTL_STATUS_PACKAGE_TYPE 1
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#define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x2
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#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) & 0x1) << 1)
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#define BFM_DIGCTL_STATUS_PACKAGE_TYPE(v) BM_DIGCTL_STATUS_PACKAGE_TYPE
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#define BF_DIGCTL_STATUS_PACKAGE_TYPE_V(e) BF_DIGCTL_STATUS_PACKAGE_TYPE(BV_DIGCTL_STATUS_PACKAGE_TYPE__##e)
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#define BFM_DIGCTL_STATUS_PACKAGE_TYPE_V(v) BM_DIGCTL_STATUS_PACKAGE_TYPE
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#define BP_DIGCTL_STATUS_WRITTEN 0
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#define BM_DIGCTL_STATUS_WRITTEN 0x1
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#define BF_DIGCTL_STATUS_WRITTEN(v) (((v) & 0x1) << 0)
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#define BFM_DIGCTL_STATUS_WRITTEN(v) BM_DIGCTL_STATUS_WRITTEN
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#define BF_DIGCTL_STATUS_WRITTEN_V(e) BF_DIGCTL_STATUS_WRITTEN(BV_DIGCTL_STATUS_WRITTEN__##e)
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#define BFM_DIGCTL_STATUS_WRITTEN_V(v) BM_DIGCTL_STATUS_WRITTEN
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#define HW_DIGCTL_HCLKCOUNT HW(DIGCTL_HCLKCOUNT)
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#define HWA_DIGCTL_HCLKCOUNT (0x8001c000 + 0x20)
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#define HWT_DIGCTL_HCLKCOUNT HWIO_32_RW
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#define HWN_DIGCTL_HCLKCOUNT DIGCTL_HCLKCOUNT
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#define HWI_DIGCTL_HCLKCOUNT
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#define BP_DIGCTL_HCLKCOUNT_COUNT 0
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#define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff
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#define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_HCLKCOUNT_COUNT(v) BM_DIGCTL_HCLKCOUNT_COUNT
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#define BF_DIGCTL_HCLKCOUNT_COUNT_V(e) BF_DIGCTL_HCLKCOUNT_COUNT(BV_DIGCTL_HCLKCOUNT_COUNT__##e)
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#define BFM_DIGCTL_HCLKCOUNT_COUNT_V(v) BM_DIGCTL_HCLKCOUNT_COUNT
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#define HW_DIGCTL_RAMCTRL HW(DIGCTL_RAMCTRL)
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#define HWA_DIGCTL_RAMCTRL (0x8001c000 + 0x30)
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#define HWT_DIGCTL_RAMCTRL HWIO_32_RW
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#define HWN_DIGCTL_RAMCTRL DIGCTL_RAMCTRL
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#define HWI_DIGCTL_RAMCTRL
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#define HW_DIGCTL_RAMCTRL_SET HW(DIGCTL_RAMCTRL_SET)
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#define HWA_DIGCTL_RAMCTRL_SET (HWA_DIGCTL_RAMCTRL + 0x4)
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#define HWT_DIGCTL_RAMCTRL_SET HWIO_32_WO
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#define HWN_DIGCTL_RAMCTRL_SET DIGCTL_RAMCTRL
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#define HWI_DIGCTL_RAMCTRL_SET
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#define HW_DIGCTL_RAMCTRL_CLR HW(DIGCTL_RAMCTRL_CLR)
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#define HWA_DIGCTL_RAMCTRL_CLR (HWA_DIGCTL_RAMCTRL + 0x8)
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#define HWT_DIGCTL_RAMCTRL_CLR HWIO_32_WO
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#define HWN_DIGCTL_RAMCTRL_CLR DIGCTL_RAMCTRL
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#define HWI_DIGCTL_RAMCTRL_CLR
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#define HW_DIGCTL_RAMCTRL_TOG HW(DIGCTL_RAMCTRL_TOG)
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#define HWA_DIGCTL_RAMCTRL_TOG (HWA_DIGCTL_RAMCTRL + 0xc)
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#define HWT_DIGCTL_RAMCTRL_TOG HWIO_32_WO
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#define HWN_DIGCTL_RAMCTRL_TOG DIGCTL_RAMCTRL
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#define HWI_DIGCTL_RAMCTRL_TOG
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#define BP_DIGCTL_RAMCTRL_TEST_MARGIN 28
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#define BM_DIGCTL_RAMCTRL_TEST_MARGIN 0x70000000
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#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__NORMAL 0x0
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#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL1 0x1
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#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL2 0x2
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#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL3 0x3
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#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL4 0x4
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#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL5 0x5
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#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL6 0x6
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#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL7 0x7
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#define BF_DIGCTL_RAMCTRL_TEST_MARGIN(v) (((v) & 0x7) << 28)
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#define BFM_DIGCTL_RAMCTRL_TEST_MARGIN(v) BM_DIGCTL_RAMCTRL_TEST_MARGIN
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#define BF_DIGCTL_RAMCTRL_TEST_MARGIN_V(e) BF_DIGCTL_RAMCTRL_TEST_MARGIN(BV_DIGCTL_RAMCTRL_TEST_MARGIN__##e)
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#define BFM_DIGCTL_RAMCTRL_TEST_MARGIN_V(v) BM_DIGCTL_RAMCTRL_TEST_MARGIN
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#define BP_DIGCTL_RAMCTRL_PWDN_BANKS 24
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#define BM_DIGCTL_RAMCTRL_PWDN_BANKS 0xf000000
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#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK3 0x8
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#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK2 0x4
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#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK1 0x2
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#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK0 0x1
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#define BF_DIGCTL_RAMCTRL_PWDN_BANKS(v) (((v) & 0xf) << 24)
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#define BFM_DIGCTL_RAMCTRL_PWDN_BANKS(v) BM_DIGCTL_RAMCTRL_PWDN_BANKS
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#define BF_DIGCTL_RAMCTRL_PWDN_BANKS_V(e) BF_DIGCTL_RAMCTRL_PWDN_BANKS(BV_DIGCTL_RAMCTRL_PWDN_BANKS__##e)
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#define BFM_DIGCTL_RAMCTRL_PWDN_BANKS_V(v) BM_DIGCTL_RAMCTRL_PWDN_BANKS
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#define BP_DIGCTL_RAMCTRL_TEMP_SENSOR 20
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#define BM_DIGCTL_RAMCTRL_TEMP_SENSOR 0x700000
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#define BF_DIGCTL_RAMCTRL_TEMP_SENSOR(v) (((v) & 0x7) << 20)
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#define BFM_DIGCTL_RAMCTRL_TEMP_SENSOR(v) BM_DIGCTL_RAMCTRL_TEMP_SENSOR
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#define BF_DIGCTL_RAMCTRL_TEMP_SENSOR_V(e) BF_DIGCTL_RAMCTRL_TEMP_SENSOR(BV_DIGCTL_RAMCTRL_TEMP_SENSOR__##e)
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#define BFM_DIGCTL_RAMCTRL_TEMP_SENSOR_V(v) BM_DIGCTL_RAMCTRL_TEMP_SENSOR
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#define BP_DIGCTL_RAMCTRL_TEST_TEMP_COMP 16
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#define BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP 0x70000
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#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__LOW_TEMP 0x1
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#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_A 0x2
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#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_B 0x3
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#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_C 0x4
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#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_D 0x5
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#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_E 0x6
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#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_F 0x7
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#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v) (((v) & 0x7) << 16)
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#define BFM_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v) BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP
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#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(e) BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__##e)
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#define BFM_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(v) BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP
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#define BP_DIGCTL_RAMCTRL_SHIFT_COUNT 8
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#define BM_DIGCTL_RAMCTRL_SHIFT_COUNT 0x7f00
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#define BF_DIGCTL_RAMCTRL_SHIFT_COUNT(v) (((v) & 0x7f) << 8)
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#define BFM_DIGCTL_RAMCTRL_SHIFT_COUNT(v) BM_DIGCTL_RAMCTRL_SHIFT_COUNT
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#define BF_DIGCTL_RAMCTRL_SHIFT_COUNT_V(e) BF_DIGCTL_RAMCTRL_SHIFT_COUNT(BV_DIGCTL_RAMCTRL_SHIFT_COUNT__##e)
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#define BFM_DIGCTL_RAMCTRL_SHIFT_COUNT_V(v) BM_DIGCTL_RAMCTRL_SHIFT_COUNT
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#define BP_DIGCTL_RAMCTRL_FLIP_CLK 7
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#define BM_DIGCTL_RAMCTRL_FLIP_CLK 0x80
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#define BV_DIGCTL_RAMCTRL_FLIP_CLK__NORMAL 0x0
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#define BV_DIGCTL_RAMCTRL_FLIP_CLK__INVERT 0x1
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#define BF_DIGCTL_RAMCTRL_FLIP_CLK(v) (((v) & 0x1) << 7)
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#define BFM_DIGCTL_RAMCTRL_FLIP_CLK(v) BM_DIGCTL_RAMCTRL_FLIP_CLK
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#define BF_DIGCTL_RAMCTRL_FLIP_CLK_V(e) BF_DIGCTL_RAMCTRL_FLIP_CLK(BV_DIGCTL_RAMCTRL_FLIP_CLK__##e)
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#define BFM_DIGCTL_RAMCTRL_FLIP_CLK_V(v) BM_DIGCTL_RAMCTRL_FLIP_CLK
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#define BP_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 3
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#define BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 0x8
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#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__NORMAL 0x0
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#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__OVER_RIDE 0x1
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#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v) (((v) & 0x1) << 3)
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#define BFM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v) BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP
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#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(e) BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__##e)
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#define BFM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(v) BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP
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#define BP_DIGCTL_RAMCTRL_REF_CLK_GATE 2
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#define BM_DIGCTL_RAMCTRL_REF_CLK_GATE 0x4
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#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__NORMAL 0x0
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#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__OFF 0x1
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#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE(v) (((v) & 0x1) << 2)
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#define BFM_DIGCTL_RAMCTRL_REF_CLK_GATE(v) BM_DIGCTL_RAMCTRL_REF_CLK_GATE
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#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE_V(e) BF_DIGCTL_RAMCTRL_REF_CLK_GATE(BV_DIGCTL_RAMCTRL_REF_CLK_GATE__##e)
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#define BFM_DIGCTL_RAMCTRL_REF_CLK_GATE_V(v) BM_DIGCTL_RAMCTRL_REF_CLK_GATE
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#define BP_DIGCTL_RAMCTRL_REPAIR_STATUS 1
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#define BM_DIGCTL_RAMCTRL_REPAIR_STATUS 0x2
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#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__IDLE 0x0
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#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__BUSY 0x1
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#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS(v) (((v) & 0x1) << 1)
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#define BFM_DIGCTL_RAMCTRL_REPAIR_STATUS(v) BM_DIGCTL_RAMCTRL_REPAIR_STATUS
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#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS_V(e) BF_DIGCTL_RAMCTRL_REPAIR_STATUS(BV_DIGCTL_RAMCTRL_REPAIR_STATUS__##e)
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#define BFM_DIGCTL_RAMCTRL_REPAIR_STATUS_V(v) BM_DIGCTL_RAMCTRL_REPAIR_STATUS
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#define BP_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0
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#define BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0x1
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#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__IDLE 0x0
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#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__SEND 0x1
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#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v) (((v) & 0x1) << 0)
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#define BFM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v) BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT
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#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(e) BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__##e)
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#define BFM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(v) BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT
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#define HW_DIGCTL_RAMREPAIR0 HW(DIGCTL_RAMREPAIR0)
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#define HWA_DIGCTL_RAMREPAIR0 (0x8001c000 + 0x40)
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#define HWT_DIGCTL_RAMREPAIR0 HWIO_32_RW
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#define HWN_DIGCTL_RAMREPAIR0 DIGCTL_RAMREPAIR0
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#define HWI_DIGCTL_RAMREPAIR0
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#define HW_DIGCTL_RAMREPAIR0_SET HW(DIGCTL_RAMREPAIR0_SET)
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#define HWA_DIGCTL_RAMREPAIR0_SET (HWA_DIGCTL_RAMREPAIR0 + 0x4)
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#define HWT_DIGCTL_RAMREPAIR0_SET HWIO_32_WO
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#define HWN_DIGCTL_RAMREPAIR0_SET DIGCTL_RAMREPAIR0
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#define HWI_DIGCTL_RAMREPAIR0_SET
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#define HW_DIGCTL_RAMREPAIR0_CLR HW(DIGCTL_RAMREPAIR0_CLR)
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#define HWA_DIGCTL_RAMREPAIR0_CLR (HWA_DIGCTL_RAMREPAIR0 + 0x8)
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#define HWT_DIGCTL_RAMREPAIR0_CLR HWIO_32_WO
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#define HWN_DIGCTL_RAMREPAIR0_CLR DIGCTL_RAMREPAIR0
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#define HWI_DIGCTL_RAMREPAIR0_CLR
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#define HW_DIGCTL_RAMREPAIR0_TOG HW(DIGCTL_RAMREPAIR0_TOG)
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#define HWA_DIGCTL_RAMREPAIR0_TOG (HWA_DIGCTL_RAMREPAIR0 + 0xc)
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#define HWT_DIGCTL_RAMREPAIR0_TOG HWIO_32_WO
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#define HWN_DIGCTL_RAMREPAIR0_TOG DIGCTL_RAMREPAIR0
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#define HWI_DIGCTL_RAMREPAIR0_TOG
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#define BP_DIGCTL_RAMREPAIR0_EFUSE3 24
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#define BM_DIGCTL_RAMREPAIR0_EFUSE3 0x7f000000
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#define BF_DIGCTL_RAMREPAIR0_EFUSE3(v) (((v) & 0x7f) << 24)
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#define BFM_DIGCTL_RAMREPAIR0_EFUSE3(v) BM_DIGCTL_RAMREPAIR0_EFUSE3
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#define BF_DIGCTL_RAMREPAIR0_EFUSE3_V(e) BF_DIGCTL_RAMREPAIR0_EFUSE3(BV_DIGCTL_RAMREPAIR0_EFUSE3__##e)
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#define BFM_DIGCTL_RAMREPAIR0_EFUSE3_V(v) BM_DIGCTL_RAMREPAIR0_EFUSE3
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#define BP_DIGCTL_RAMREPAIR0_EFUSE2 16
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#define BM_DIGCTL_RAMREPAIR0_EFUSE2 0x7f0000
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#define BF_DIGCTL_RAMREPAIR0_EFUSE2(v) (((v) & 0x7f) << 16)
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#define BFM_DIGCTL_RAMREPAIR0_EFUSE2(v) BM_DIGCTL_RAMREPAIR0_EFUSE2
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#define BF_DIGCTL_RAMREPAIR0_EFUSE2_V(e) BF_DIGCTL_RAMREPAIR0_EFUSE2(BV_DIGCTL_RAMREPAIR0_EFUSE2__##e)
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#define BFM_DIGCTL_RAMREPAIR0_EFUSE2_V(v) BM_DIGCTL_RAMREPAIR0_EFUSE2
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#define BP_DIGCTL_RAMREPAIR0_EFUSE1 8
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#define BM_DIGCTL_RAMREPAIR0_EFUSE1 0x7f00
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#define BF_DIGCTL_RAMREPAIR0_EFUSE1(v) (((v) & 0x7f) << 8)
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#define BFM_DIGCTL_RAMREPAIR0_EFUSE1(v) BM_DIGCTL_RAMREPAIR0_EFUSE1
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#define BF_DIGCTL_RAMREPAIR0_EFUSE1_V(e) BF_DIGCTL_RAMREPAIR0_EFUSE1(BV_DIGCTL_RAMREPAIR0_EFUSE1__##e)
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#define BFM_DIGCTL_RAMREPAIR0_EFUSE1_V(v) BM_DIGCTL_RAMREPAIR0_EFUSE1
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#define BP_DIGCTL_RAMREPAIR0_EFUSE0 0
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#define BM_DIGCTL_RAMREPAIR0_EFUSE0 0x7f
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#define BF_DIGCTL_RAMREPAIR0_EFUSE0(v) (((v) & 0x7f) << 0)
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#define BFM_DIGCTL_RAMREPAIR0_EFUSE0(v) BM_DIGCTL_RAMREPAIR0_EFUSE0
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#define BF_DIGCTL_RAMREPAIR0_EFUSE0_V(e) BF_DIGCTL_RAMREPAIR0_EFUSE0(BV_DIGCTL_RAMREPAIR0_EFUSE0__##e)
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#define BFM_DIGCTL_RAMREPAIR0_EFUSE0_V(v) BM_DIGCTL_RAMREPAIR0_EFUSE0
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#define HW_DIGCTL_RAMREPAIR1 HW(DIGCTL_RAMREPAIR1)
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#define HWA_DIGCTL_RAMREPAIR1 (0x8001c000 + 0x50)
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#define HWT_DIGCTL_RAMREPAIR1 HWIO_32_RW
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#define HWN_DIGCTL_RAMREPAIR1 DIGCTL_RAMREPAIR1
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#define HWI_DIGCTL_RAMREPAIR1
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#define HW_DIGCTL_RAMREPAIR1_SET HW(DIGCTL_RAMREPAIR1_SET)
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#define HWA_DIGCTL_RAMREPAIR1_SET (HWA_DIGCTL_RAMREPAIR1 + 0x4)
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#define HWT_DIGCTL_RAMREPAIR1_SET HWIO_32_WO
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#define HWN_DIGCTL_RAMREPAIR1_SET DIGCTL_RAMREPAIR1
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#define HWI_DIGCTL_RAMREPAIR1_SET
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#define HW_DIGCTL_RAMREPAIR1_CLR HW(DIGCTL_RAMREPAIR1_CLR)
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#define HWA_DIGCTL_RAMREPAIR1_CLR (HWA_DIGCTL_RAMREPAIR1 + 0x8)
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#define HWT_DIGCTL_RAMREPAIR1_CLR HWIO_32_WO
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#define HWN_DIGCTL_RAMREPAIR1_CLR DIGCTL_RAMREPAIR1
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#define HWI_DIGCTL_RAMREPAIR1_CLR
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#define HW_DIGCTL_RAMREPAIR1_TOG HW(DIGCTL_RAMREPAIR1_TOG)
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#define HWA_DIGCTL_RAMREPAIR1_TOG (HWA_DIGCTL_RAMREPAIR1 + 0xc)
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#define HWT_DIGCTL_RAMREPAIR1_TOG HWIO_32_WO
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#define HWN_DIGCTL_RAMREPAIR1_TOG DIGCTL_RAMREPAIR1
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#define HWI_DIGCTL_RAMREPAIR1_TOG
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#define BP_DIGCTL_RAMREPAIR1_EFUSE3 24
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#define BM_DIGCTL_RAMREPAIR1_EFUSE3 0x7f000000
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#define BF_DIGCTL_RAMREPAIR1_EFUSE3(v) (((v) & 0x7f) << 24)
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#define BFM_DIGCTL_RAMREPAIR1_EFUSE3(v) BM_DIGCTL_RAMREPAIR1_EFUSE3
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#define BF_DIGCTL_RAMREPAIR1_EFUSE3_V(e) BF_DIGCTL_RAMREPAIR1_EFUSE3(BV_DIGCTL_RAMREPAIR1_EFUSE3__##e)
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#define BFM_DIGCTL_RAMREPAIR1_EFUSE3_V(v) BM_DIGCTL_RAMREPAIR1_EFUSE3
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#define BP_DIGCTL_RAMREPAIR1_EFUSE2 16
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#define BM_DIGCTL_RAMREPAIR1_EFUSE2 0x7f0000
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#define BF_DIGCTL_RAMREPAIR1_EFUSE2(v) (((v) & 0x7f) << 16)
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#define BFM_DIGCTL_RAMREPAIR1_EFUSE2(v) BM_DIGCTL_RAMREPAIR1_EFUSE2
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#define BF_DIGCTL_RAMREPAIR1_EFUSE2_V(e) BF_DIGCTL_RAMREPAIR1_EFUSE2(BV_DIGCTL_RAMREPAIR1_EFUSE2__##e)
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#define BFM_DIGCTL_RAMREPAIR1_EFUSE2_V(v) BM_DIGCTL_RAMREPAIR1_EFUSE2
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#define BP_DIGCTL_RAMREPAIR1_EFUSE1 8
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#define BM_DIGCTL_RAMREPAIR1_EFUSE1 0x7f00
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#define BF_DIGCTL_RAMREPAIR1_EFUSE1(v) (((v) & 0x7f) << 8)
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#define BFM_DIGCTL_RAMREPAIR1_EFUSE1(v) BM_DIGCTL_RAMREPAIR1_EFUSE1
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#define BF_DIGCTL_RAMREPAIR1_EFUSE1_V(e) BF_DIGCTL_RAMREPAIR1_EFUSE1(BV_DIGCTL_RAMREPAIR1_EFUSE1__##e)
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#define BFM_DIGCTL_RAMREPAIR1_EFUSE1_V(v) BM_DIGCTL_RAMREPAIR1_EFUSE1
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#define BP_DIGCTL_RAMREPAIR1_EFUSE0 0
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#define BM_DIGCTL_RAMREPAIR1_EFUSE0 0x7f
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#define BF_DIGCTL_RAMREPAIR1_EFUSE0(v) (((v) & 0x7f) << 0)
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#define BFM_DIGCTL_RAMREPAIR1_EFUSE0(v) BM_DIGCTL_RAMREPAIR1_EFUSE0
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#define BF_DIGCTL_RAMREPAIR1_EFUSE0_V(e) BF_DIGCTL_RAMREPAIR1_EFUSE0(BV_DIGCTL_RAMREPAIR1_EFUSE0__##e)
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#define BFM_DIGCTL_RAMREPAIR1_EFUSE0_V(v) BM_DIGCTL_RAMREPAIR1_EFUSE0
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#define HW_DIGCTL_WRITEONCE HW(DIGCTL_WRITEONCE)
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#define HWA_DIGCTL_WRITEONCE (0x8001c000 + 0x60)
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#define HWT_DIGCTL_WRITEONCE HWIO_32_RW
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#define HWN_DIGCTL_WRITEONCE DIGCTL_WRITEONCE
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#define HWI_DIGCTL_WRITEONCE
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#define BP_DIGCTL_WRITEONCE_BITS 0
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#define BM_DIGCTL_WRITEONCE_BITS 0xffffffff
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#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_WRITEONCE_BITS(v) BM_DIGCTL_WRITEONCE_BITS
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#define BF_DIGCTL_WRITEONCE_BITS_V(e) BF_DIGCTL_WRITEONCE_BITS(BV_DIGCTL_WRITEONCE_BITS__##e)
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#define BFM_DIGCTL_WRITEONCE_BITS_V(v) BM_DIGCTL_WRITEONCE_BITS
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#define HW_DIGCTL_AHBCYCLES HW(DIGCTL_AHBCYCLES)
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#define HWA_DIGCTL_AHBCYCLES (0x8001c000 + 0x70)
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#define HWT_DIGCTL_AHBCYCLES HWIO_32_RW
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#define HWN_DIGCTL_AHBCYCLES DIGCTL_AHBCYCLES
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#define HWI_DIGCTL_AHBCYCLES
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#define BP_DIGCTL_AHBCYCLES_COUNT 0
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#define BM_DIGCTL_AHBCYCLES_COUNT 0xffffffff
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#define BF_DIGCTL_AHBCYCLES_COUNT(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_AHBCYCLES_COUNT(v) BM_DIGCTL_AHBCYCLES_COUNT
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#define BF_DIGCTL_AHBCYCLES_COUNT_V(e) BF_DIGCTL_AHBCYCLES_COUNT(BV_DIGCTL_AHBCYCLES_COUNT__##e)
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#define BFM_DIGCTL_AHBCYCLES_COUNT_V(v) BM_DIGCTL_AHBCYCLES_COUNT
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#define HW_DIGCTL_AHBSTALLED HW(DIGCTL_AHBSTALLED)
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#define HWA_DIGCTL_AHBSTALLED (0x8001c000 + 0x80)
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#define HWT_DIGCTL_AHBSTALLED HWIO_32_RW
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#define HWN_DIGCTL_AHBSTALLED DIGCTL_AHBSTALLED
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#define HWI_DIGCTL_AHBSTALLED
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#define BP_DIGCTL_AHBSTALLED_COUNT 0
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#define BM_DIGCTL_AHBSTALLED_COUNT 0xffffffff
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#define BF_DIGCTL_AHBSTALLED_COUNT(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_AHBSTALLED_COUNT(v) BM_DIGCTL_AHBSTALLED_COUNT
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#define BF_DIGCTL_AHBSTALLED_COUNT_V(e) BF_DIGCTL_AHBSTALLED_COUNT(BV_DIGCTL_AHBSTALLED_COUNT__##e)
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#define BFM_DIGCTL_AHBSTALLED_COUNT_V(v) BM_DIGCTL_AHBSTALLED_COUNT
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#define HW_DIGCTL_ENTROPY HW(DIGCTL_ENTROPY)
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#define HWA_DIGCTL_ENTROPY (0x8001c000 + 0x90)
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#define HWT_DIGCTL_ENTROPY HWIO_32_RW
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#define HWN_DIGCTL_ENTROPY DIGCTL_ENTROPY
|
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#define HWI_DIGCTL_ENTROPY
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#define BP_DIGCTL_ENTROPY_VALUE 0
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#define BM_DIGCTL_ENTROPY_VALUE 0xffffffff
|
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#define BF_DIGCTL_ENTROPY_VALUE(v) (((v) & 0xffffffff) << 0)
|
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#define BFM_DIGCTL_ENTROPY_VALUE(v) BM_DIGCTL_ENTROPY_VALUE
|
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#define BF_DIGCTL_ENTROPY_VALUE_V(e) BF_DIGCTL_ENTROPY_VALUE(BV_DIGCTL_ENTROPY_VALUE__##e)
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#define BFM_DIGCTL_ENTROPY_VALUE_V(v) BM_DIGCTL_ENTROPY_VALUE
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#define HW_DIGCTL_ROMSHIELD HW(DIGCTL_ROMSHIELD)
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#define HWA_DIGCTL_ROMSHIELD (0x8001c000 + 0xa0)
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#define HWT_DIGCTL_ROMSHIELD HWIO_32_RW
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#define HWN_DIGCTL_ROMSHIELD DIGCTL_ROMSHIELD
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#define HWI_DIGCTL_ROMSHIELD
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#define BP_DIGCTL_ROMSHIELD_WRITE_ONCE 0
|
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#define BM_DIGCTL_ROMSHIELD_WRITE_ONCE 0x1
|
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#define BF_DIGCTL_ROMSHIELD_WRITE_ONCE(v) (((v) & 0x1) << 0)
|
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#define BFM_DIGCTL_ROMSHIELD_WRITE_ONCE(v) BM_DIGCTL_ROMSHIELD_WRITE_ONCE
|
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#define BF_DIGCTL_ROMSHIELD_WRITE_ONCE_V(e) BF_DIGCTL_ROMSHIELD_WRITE_ONCE(BV_DIGCTL_ROMSHIELD_WRITE_ONCE__##e)
|
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#define BFM_DIGCTL_ROMSHIELD_WRITE_ONCE_V(v) BM_DIGCTL_ROMSHIELD_WRITE_ONCE
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#define HW_DIGCTL_MICROSECONDS HW(DIGCTL_MICROSECONDS)
|
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#define HWA_DIGCTL_MICROSECONDS (0x8001c000 + 0xb0)
|
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#define HWT_DIGCTL_MICROSECONDS HWIO_32_RW
|
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#define HWN_DIGCTL_MICROSECONDS DIGCTL_MICROSECONDS
|
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#define HWI_DIGCTL_MICROSECONDS
|
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#define HW_DIGCTL_MICROSECONDS_SET HW(DIGCTL_MICROSECONDS_SET)
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#define HWA_DIGCTL_MICROSECONDS_SET (HWA_DIGCTL_MICROSECONDS + 0x4)
|
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#define HWT_DIGCTL_MICROSECONDS_SET HWIO_32_WO
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#define HWN_DIGCTL_MICROSECONDS_SET DIGCTL_MICROSECONDS
|
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#define HWI_DIGCTL_MICROSECONDS_SET
|
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#define HW_DIGCTL_MICROSECONDS_CLR HW(DIGCTL_MICROSECONDS_CLR)
|
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#define HWA_DIGCTL_MICROSECONDS_CLR (HWA_DIGCTL_MICROSECONDS + 0x8)
|
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#define HWT_DIGCTL_MICROSECONDS_CLR HWIO_32_WO
|
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#define HWN_DIGCTL_MICROSECONDS_CLR DIGCTL_MICROSECONDS
|
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#define HWI_DIGCTL_MICROSECONDS_CLR
|
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#define HW_DIGCTL_MICROSECONDS_TOG HW(DIGCTL_MICROSECONDS_TOG)
|
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#define HWA_DIGCTL_MICROSECONDS_TOG (HWA_DIGCTL_MICROSECONDS + 0xc)
|
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#define HWT_DIGCTL_MICROSECONDS_TOG HWIO_32_WO
|
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#define HWN_DIGCTL_MICROSECONDS_TOG DIGCTL_MICROSECONDS
|
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#define HWI_DIGCTL_MICROSECONDS_TOG
|
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#define BP_DIGCTL_MICROSECONDS_VALUE 0
|
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#define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff
|
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#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) & 0xffffffff) << 0)
|
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#define BFM_DIGCTL_MICROSECONDS_VALUE(v) BM_DIGCTL_MICROSECONDS_VALUE
|
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#define BF_DIGCTL_MICROSECONDS_VALUE_V(e) BF_DIGCTL_MICROSECONDS_VALUE(BV_DIGCTL_MICROSECONDS_VALUE__##e)
|
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#define BFM_DIGCTL_MICROSECONDS_VALUE_V(v) BM_DIGCTL_MICROSECONDS_VALUE
|
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#define HW_DIGCTL_DBGRD HW(DIGCTL_DBGRD)
|
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#define HWA_DIGCTL_DBGRD (0x8001c000 + 0xc0)
|
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#define HWT_DIGCTL_DBGRD HWIO_32_RW
|
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#define HWN_DIGCTL_DBGRD DIGCTL_DBGRD
|
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#define HWI_DIGCTL_DBGRD
|
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#define BP_DIGCTL_DBGRD_COMPLEMENT 0
|
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#define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff
|
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#define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) & 0xffffffff) << 0)
|
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#define BFM_DIGCTL_DBGRD_COMPLEMENT(v) BM_DIGCTL_DBGRD_COMPLEMENT
|
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#define BF_DIGCTL_DBGRD_COMPLEMENT_V(e) BF_DIGCTL_DBGRD_COMPLEMENT(BV_DIGCTL_DBGRD_COMPLEMENT__##e)
|
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#define BFM_DIGCTL_DBGRD_COMPLEMENT_V(v) BM_DIGCTL_DBGRD_COMPLEMENT
|
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|
|
#define HW_DIGCTL_DBG HW(DIGCTL_DBG)
|
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#define HWA_DIGCTL_DBG (0x8001c000 + 0xd0)
|
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#define HWT_DIGCTL_DBG HWIO_32_RW
|
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#define HWN_DIGCTL_DBG DIGCTL_DBG
|
|
#define HWI_DIGCTL_DBG
|
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#define BP_DIGCTL_DBG_VALUE 0
|
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#define BM_DIGCTL_DBG_VALUE 0xffffffff
|
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#define BF_DIGCTL_DBG_VALUE(v) (((v) & 0xffffffff) << 0)
|
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#define BFM_DIGCTL_DBG_VALUE(v) BM_DIGCTL_DBG_VALUE
|
|
#define BF_DIGCTL_DBG_VALUE_V(e) BF_DIGCTL_DBG_VALUE(BV_DIGCTL_DBG_VALUE__##e)
|
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#define BFM_DIGCTL_DBG_VALUE_V(v) BM_DIGCTL_DBG_VALUE
|
|
|
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#define HW_DIGCTL_1TRAM_BIST_CSR HW(DIGCTL_1TRAM_BIST_CSR)
|
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#define HWA_DIGCTL_1TRAM_BIST_CSR (0x8001c000 + 0xe0)
|
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#define HWT_DIGCTL_1TRAM_BIST_CSR HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_BIST_CSR DIGCTL_1TRAM_BIST_CSR
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#define HWI_DIGCTL_1TRAM_BIST_CSR
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#define HW_DIGCTL_1TRAM_BIST_CSR_SET HW(DIGCTL_1TRAM_BIST_CSR_SET)
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#define HWA_DIGCTL_1TRAM_BIST_CSR_SET (HWA_DIGCTL_1TRAM_BIST_CSR + 0x4)
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#define HWT_DIGCTL_1TRAM_BIST_CSR_SET HWIO_32_WO
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#define HWN_DIGCTL_1TRAM_BIST_CSR_SET DIGCTL_1TRAM_BIST_CSR
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#define HWI_DIGCTL_1TRAM_BIST_CSR_SET
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#define HW_DIGCTL_1TRAM_BIST_CSR_CLR HW(DIGCTL_1TRAM_BIST_CSR_CLR)
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#define HWA_DIGCTL_1TRAM_BIST_CSR_CLR (HWA_DIGCTL_1TRAM_BIST_CSR + 0x8)
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#define HWT_DIGCTL_1TRAM_BIST_CSR_CLR HWIO_32_WO
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#define HWN_DIGCTL_1TRAM_BIST_CSR_CLR DIGCTL_1TRAM_BIST_CSR
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#define HWI_DIGCTL_1TRAM_BIST_CSR_CLR
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#define HW_DIGCTL_1TRAM_BIST_CSR_TOG HW(DIGCTL_1TRAM_BIST_CSR_TOG)
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#define HWA_DIGCTL_1TRAM_BIST_CSR_TOG (HWA_DIGCTL_1TRAM_BIST_CSR + 0xc)
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#define HWT_DIGCTL_1TRAM_BIST_CSR_TOG HWIO_32_WO
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#define HWN_DIGCTL_1TRAM_BIST_CSR_TOG DIGCTL_1TRAM_BIST_CSR
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#define HWI_DIGCTL_1TRAM_BIST_CSR_TOG
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#define BP_DIGCTL_1TRAM_BIST_CSR_FAIL 3
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#define BM_DIGCTL_1TRAM_BIST_CSR_FAIL 0x8
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#define BF_DIGCTL_1TRAM_BIST_CSR_FAIL(v) (((v) & 0x1) << 3)
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#define BFM_DIGCTL_1TRAM_BIST_CSR_FAIL(v) BM_DIGCTL_1TRAM_BIST_CSR_FAIL
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#define BF_DIGCTL_1TRAM_BIST_CSR_FAIL_V(e) BF_DIGCTL_1TRAM_BIST_CSR_FAIL(BV_DIGCTL_1TRAM_BIST_CSR_FAIL__##e)
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#define BFM_DIGCTL_1TRAM_BIST_CSR_FAIL_V(v) BM_DIGCTL_1TRAM_BIST_CSR_FAIL
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#define BP_DIGCTL_1TRAM_BIST_CSR_PASS 2
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#define BM_DIGCTL_1TRAM_BIST_CSR_PASS 0x4
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#define BF_DIGCTL_1TRAM_BIST_CSR_PASS(v) (((v) & 0x1) << 2)
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#define BFM_DIGCTL_1TRAM_BIST_CSR_PASS(v) BM_DIGCTL_1TRAM_BIST_CSR_PASS
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#define BF_DIGCTL_1TRAM_BIST_CSR_PASS_V(e) BF_DIGCTL_1TRAM_BIST_CSR_PASS(BV_DIGCTL_1TRAM_BIST_CSR_PASS__##e)
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#define BFM_DIGCTL_1TRAM_BIST_CSR_PASS_V(v) BM_DIGCTL_1TRAM_BIST_CSR_PASS
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#define BP_DIGCTL_1TRAM_BIST_CSR_DONE 1
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#define BM_DIGCTL_1TRAM_BIST_CSR_DONE 0x2
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#define BF_DIGCTL_1TRAM_BIST_CSR_DONE(v) (((v) & 0x1) << 1)
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#define BFM_DIGCTL_1TRAM_BIST_CSR_DONE(v) BM_DIGCTL_1TRAM_BIST_CSR_DONE
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#define BF_DIGCTL_1TRAM_BIST_CSR_DONE_V(e) BF_DIGCTL_1TRAM_BIST_CSR_DONE(BV_DIGCTL_1TRAM_BIST_CSR_DONE__##e)
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#define BFM_DIGCTL_1TRAM_BIST_CSR_DONE_V(v) BM_DIGCTL_1TRAM_BIST_CSR_DONE
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#define BP_DIGCTL_1TRAM_BIST_CSR_START 0
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#define BM_DIGCTL_1TRAM_BIST_CSR_START 0x1
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#define BF_DIGCTL_1TRAM_BIST_CSR_START(v) (((v) & 0x1) << 0)
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#define BFM_DIGCTL_1TRAM_BIST_CSR_START(v) BM_DIGCTL_1TRAM_BIST_CSR_START
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#define BF_DIGCTL_1TRAM_BIST_CSR_START_V(e) BF_DIGCTL_1TRAM_BIST_CSR_START(BV_DIGCTL_1TRAM_BIST_CSR_START__##e)
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#define BFM_DIGCTL_1TRAM_BIST_CSR_START_V(v) BM_DIGCTL_1TRAM_BIST_CSR_START
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#define HW_DIGCTL_1TRAM_BIST_REPAIR0 HW(DIGCTL_1TRAM_BIST_REPAIR0)
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#define HWA_DIGCTL_1TRAM_BIST_REPAIR0 (0x8001c000 + 0xf0)
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#define HWT_DIGCTL_1TRAM_BIST_REPAIR0 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_BIST_REPAIR0 DIGCTL_1TRAM_BIST_REPAIR0
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#define HWI_DIGCTL_1TRAM_BIST_REPAIR0
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#define HW_DIGCTL_1TRAM_BIST_REPAIR1 HW(DIGCTL_1TRAM_BIST_REPAIR1)
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#define HWA_DIGCTL_1TRAM_BIST_REPAIR1 (0x8001c000 + 0x100)
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#define HWT_DIGCTL_1TRAM_BIST_REPAIR1 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_BIST_REPAIR1 DIGCTL_1TRAM_BIST_REPAIR1
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#define HWI_DIGCTL_1TRAM_BIST_REPAIR1
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#define HW_DIGCTL_1TRAM_STATUS0 HW(DIGCTL_1TRAM_STATUS0)
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#define HWA_DIGCTL_1TRAM_STATUS0 (0x8001c000 + 0x110)
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#define HWT_DIGCTL_1TRAM_STATUS0 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS0 DIGCTL_1TRAM_STATUS0
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#define HWI_DIGCTL_1TRAM_STATUS0
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#define BP_DIGCTL_1TRAM_STATUS0_FAILDATA00 0
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#define BM_DIGCTL_1TRAM_STATUS0_FAILDATA00 0xffffffff
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#define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS0_FAILDATA00(v) BM_DIGCTL_1TRAM_STATUS0_FAILDATA00
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#define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00_V(e) BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(BV_DIGCTL_1TRAM_STATUS0_FAILDATA00__##e)
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#define BFM_DIGCTL_1TRAM_STATUS0_FAILDATA00_V(v) BM_DIGCTL_1TRAM_STATUS0_FAILDATA00
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#define HW_DIGCTL_1TRAM_STATUS1 HW(DIGCTL_1TRAM_STATUS1)
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#define HWA_DIGCTL_1TRAM_STATUS1 (0x8001c000 + 0x120)
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#define HWT_DIGCTL_1TRAM_STATUS1 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS1 DIGCTL_1TRAM_STATUS1
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#define HWI_DIGCTL_1TRAM_STATUS1
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#define BP_DIGCTL_1TRAM_STATUS1_FAILDATA01 0
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#define BM_DIGCTL_1TRAM_STATUS1_FAILDATA01 0xffffffff
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#define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS1_FAILDATA01(v) BM_DIGCTL_1TRAM_STATUS1_FAILDATA01
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#define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01_V(e) BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(BV_DIGCTL_1TRAM_STATUS1_FAILDATA01__##e)
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#define BFM_DIGCTL_1TRAM_STATUS1_FAILDATA01_V(v) BM_DIGCTL_1TRAM_STATUS1_FAILDATA01
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#define HW_DIGCTL_1TRAM_STATUS2 HW(DIGCTL_1TRAM_STATUS2)
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#define HWA_DIGCTL_1TRAM_STATUS2 (0x8001c000 + 0x130)
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#define HWT_DIGCTL_1TRAM_STATUS2 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS2 DIGCTL_1TRAM_STATUS2
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#define HWI_DIGCTL_1TRAM_STATUS2
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#define BP_DIGCTL_1TRAM_STATUS2_FAILDATA10 0
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#define BM_DIGCTL_1TRAM_STATUS2_FAILDATA10 0xffffffff
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#define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS2_FAILDATA10(v) BM_DIGCTL_1TRAM_STATUS2_FAILDATA10
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#define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10_V(e) BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(BV_DIGCTL_1TRAM_STATUS2_FAILDATA10__##e)
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#define BFM_DIGCTL_1TRAM_STATUS2_FAILDATA10_V(v) BM_DIGCTL_1TRAM_STATUS2_FAILDATA10
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#define HW_DIGCTL_1TRAM_STATUS3 HW(DIGCTL_1TRAM_STATUS3)
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#define HWA_DIGCTL_1TRAM_STATUS3 (0x8001c000 + 0x140)
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#define HWT_DIGCTL_1TRAM_STATUS3 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS3 DIGCTL_1TRAM_STATUS3
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#define HWI_DIGCTL_1TRAM_STATUS3
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#define BP_DIGCTL_1TRAM_STATUS3_FAILDATA11 0
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#define BM_DIGCTL_1TRAM_STATUS3_FAILDATA11 0xffffffff
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#define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS3_FAILDATA11(v) BM_DIGCTL_1TRAM_STATUS3_FAILDATA11
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#define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11_V(e) BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(BV_DIGCTL_1TRAM_STATUS3_FAILDATA11__##e)
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#define BFM_DIGCTL_1TRAM_STATUS3_FAILDATA11_V(v) BM_DIGCTL_1TRAM_STATUS3_FAILDATA11
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#define HW_DIGCTL_1TRAM_STATUS4 HW(DIGCTL_1TRAM_STATUS4)
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#define HWA_DIGCTL_1TRAM_STATUS4 (0x8001c000 + 0x150)
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#define HWT_DIGCTL_1TRAM_STATUS4 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS4 DIGCTL_1TRAM_STATUS4
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#define HWI_DIGCTL_1TRAM_STATUS4
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#define BP_DIGCTL_1TRAM_STATUS4_FAILDATA20 0
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#define BM_DIGCTL_1TRAM_STATUS4_FAILDATA20 0xffffffff
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#define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS4_FAILDATA20(v) BM_DIGCTL_1TRAM_STATUS4_FAILDATA20
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#define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20_V(e) BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(BV_DIGCTL_1TRAM_STATUS4_FAILDATA20__##e)
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#define BFM_DIGCTL_1TRAM_STATUS4_FAILDATA20_V(v) BM_DIGCTL_1TRAM_STATUS4_FAILDATA20
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#define HW_DIGCTL_1TRAM_STATUS5 HW(DIGCTL_1TRAM_STATUS5)
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#define HWA_DIGCTL_1TRAM_STATUS5 (0x8001c000 + 0x160)
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#define HWT_DIGCTL_1TRAM_STATUS5 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS5 DIGCTL_1TRAM_STATUS5
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#define HWI_DIGCTL_1TRAM_STATUS5
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#define BP_DIGCTL_1TRAM_STATUS5_FAILDATA21 0
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#define BM_DIGCTL_1TRAM_STATUS5_FAILDATA21 0xffffffff
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#define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS5_FAILDATA21(v) BM_DIGCTL_1TRAM_STATUS5_FAILDATA21
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#define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21_V(e) BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(BV_DIGCTL_1TRAM_STATUS5_FAILDATA21__##e)
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#define BFM_DIGCTL_1TRAM_STATUS5_FAILDATA21_V(v) BM_DIGCTL_1TRAM_STATUS5_FAILDATA21
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#define HW_DIGCTL_1TRAM_STATUS6 HW(DIGCTL_1TRAM_STATUS6)
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#define HWA_DIGCTL_1TRAM_STATUS6 (0x8001c000 + 0x170)
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#define HWT_DIGCTL_1TRAM_STATUS6 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS6 DIGCTL_1TRAM_STATUS6
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#define HWI_DIGCTL_1TRAM_STATUS6
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#define BP_DIGCTL_1TRAM_STATUS6_FAILDATA30 0
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#define BM_DIGCTL_1TRAM_STATUS6_FAILDATA30 0xffffffff
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#define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS6_FAILDATA30(v) BM_DIGCTL_1TRAM_STATUS6_FAILDATA30
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#define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30_V(e) BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(BV_DIGCTL_1TRAM_STATUS6_FAILDATA30__##e)
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#define BFM_DIGCTL_1TRAM_STATUS6_FAILDATA30_V(v) BM_DIGCTL_1TRAM_STATUS6_FAILDATA30
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#define HW_DIGCTL_1TRAM_STATUS7 HW(DIGCTL_1TRAM_STATUS7)
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#define HWA_DIGCTL_1TRAM_STATUS7 (0x8001c000 + 0x180)
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#define HWT_DIGCTL_1TRAM_STATUS7 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS7 DIGCTL_1TRAM_STATUS7
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#define HWI_DIGCTL_1TRAM_STATUS7
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#define BP_DIGCTL_1TRAM_STATUS7_FAILDATA31 0
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#define BM_DIGCTL_1TRAM_STATUS7_FAILDATA31 0xffffffff
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#define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS7_FAILDATA31(v) BM_DIGCTL_1TRAM_STATUS7_FAILDATA31
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#define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31_V(e) BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(BV_DIGCTL_1TRAM_STATUS7_FAILDATA31__##e)
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#define BFM_DIGCTL_1TRAM_STATUS7_FAILDATA31_V(v) BM_DIGCTL_1TRAM_STATUS7_FAILDATA31
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#define HW_DIGCTL_1TRAM_STATUS8 HW(DIGCTL_1TRAM_STATUS8)
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#define HWA_DIGCTL_1TRAM_STATUS8 (0x8001c000 + 0x190)
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#define HWT_DIGCTL_1TRAM_STATUS8 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS8 DIGCTL_1TRAM_STATUS8
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#define HWI_DIGCTL_1TRAM_STATUS8
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#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR01 16
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#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR01 0xffff0000
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#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(v) (((v) & 0xffff) << 16)
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#define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR01(v) BM_DIGCTL_1TRAM_STATUS8_FAILADDR01
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#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01_V(e) BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(BV_DIGCTL_1TRAM_STATUS8_FAILADDR01__##e)
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#define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR01_V(v) BM_DIGCTL_1TRAM_STATUS8_FAILADDR01
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#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR00 0
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#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR00 0xffff
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#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(v) (((v) & 0xffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR00(v) BM_DIGCTL_1TRAM_STATUS8_FAILADDR00
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#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00_V(e) BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(BV_DIGCTL_1TRAM_STATUS8_FAILADDR00__##e)
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#define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR00_V(v) BM_DIGCTL_1TRAM_STATUS8_FAILADDR00
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#define HW_DIGCTL_1TRAM_STATUS9 HW(DIGCTL_1TRAM_STATUS9)
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#define HWA_DIGCTL_1TRAM_STATUS9 (0x8001c000 + 0x1a0)
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#define HWT_DIGCTL_1TRAM_STATUS9 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS9 DIGCTL_1TRAM_STATUS9
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#define HWI_DIGCTL_1TRAM_STATUS9
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#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR11 16
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#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR11 0xffff0000
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#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(v) (((v) & 0xffff) << 16)
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#define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR11(v) BM_DIGCTL_1TRAM_STATUS9_FAILADDR11
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#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11_V(e) BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(BV_DIGCTL_1TRAM_STATUS9_FAILADDR11__##e)
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#define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR11_V(v) BM_DIGCTL_1TRAM_STATUS9_FAILADDR11
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#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR10 0
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#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR10 0xffff
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#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(v) (((v) & 0xffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR10(v) BM_DIGCTL_1TRAM_STATUS9_FAILADDR10
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#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10_V(e) BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(BV_DIGCTL_1TRAM_STATUS9_FAILADDR10__##e)
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#define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR10_V(v) BM_DIGCTL_1TRAM_STATUS9_FAILADDR10
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#define HW_DIGCTL_1TRAM_STATUS10 HW(DIGCTL_1TRAM_STATUS10)
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#define HWA_DIGCTL_1TRAM_STATUS10 (0x8001c000 + 0x1b0)
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#define HWT_DIGCTL_1TRAM_STATUS10 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS10 DIGCTL_1TRAM_STATUS10
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#define HWI_DIGCTL_1TRAM_STATUS10
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#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR21 16
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#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR21 0xffff0000
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#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(v) (((v) & 0xffff) << 16)
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#define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR21(v) BM_DIGCTL_1TRAM_STATUS10_FAILADDR21
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#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21_V(e) BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(BV_DIGCTL_1TRAM_STATUS10_FAILADDR21__##e)
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#define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR21_V(v) BM_DIGCTL_1TRAM_STATUS10_FAILADDR21
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#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR20 0
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#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR20 0xffff
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#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(v) (((v) & 0xffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR20(v) BM_DIGCTL_1TRAM_STATUS10_FAILADDR20
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#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20_V(e) BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(BV_DIGCTL_1TRAM_STATUS10_FAILADDR20__##e)
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#define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR20_V(v) BM_DIGCTL_1TRAM_STATUS10_FAILADDR20
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#define HW_DIGCTL_1TRAM_STATUS11 HW(DIGCTL_1TRAM_STATUS11)
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#define HWA_DIGCTL_1TRAM_STATUS11 (0x8001c000 + 0x1c0)
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#define HWT_DIGCTL_1TRAM_STATUS11 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS11 DIGCTL_1TRAM_STATUS11
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#define HWI_DIGCTL_1TRAM_STATUS11
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#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR31 16
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#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR31 0xffff0000
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#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(v) (((v) & 0xffff) << 16)
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#define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR31(v) BM_DIGCTL_1TRAM_STATUS11_FAILADDR31
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#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31_V(e) BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(BV_DIGCTL_1TRAM_STATUS11_FAILADDR31__##e)
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#define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR31_V(v) BM_DIGCTL_1TRAM_STATUS11_FAILADDR31
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#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR30 0
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#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR30 0xffff
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#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(v) (((v) & 0xffff) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR30(v) BM_DIGCTL_1TRAM_STATUS11_FAILADDR30
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#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30_V(e) BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(BV_DIGCTL_1TRAM_STATUS11_FAILADDR30__##e)
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#define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR30_V(v) BM_DIGCTL_1TRAM_STATUS11_FAILADDR30
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#define HW_DIGCTL_1TRAM_STATUS12 HW(DIGCTL_1TRAM_STATUS12)
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#define HWA_DIGCTL_1TRAM_STATUS12 (0x8001c000 + 0x1d0)
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#define HWT_DIGCTL_1TRAM_STATUS12 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS12 DIGCTL_1TRAM_STATUS12
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#define HWI_DIGCTL_1TRAM_STATUS12
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#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE11 24
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#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11 0x1f000000
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#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) (((v) & 0x1f) << 24)
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#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11
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#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11_V(e) BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE11__##e)
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#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE11_V(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11
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#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE10 16
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#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10 0x1f0000
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#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) (((v) & 0x1f) << 16)
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#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10
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#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10_V(e) BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE10__##e)
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#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE10_V(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10
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#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE01 8
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#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01 0x1f00
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#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) (((v) & 0x1f) << 8)
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#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01
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#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01_V(e) BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE01__##e)
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#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE01_V(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01
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#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0
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#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0x1f
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#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) (((v) & 0x1f) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00
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#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00_V(e) BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE00__##e)
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#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE00_V(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00
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#define HW_DIGCTL_1TRAM_STATUS13 HW(DIGCTL_1TRAM_STATUS13)
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#define HWA_DIGCTL_1TRAM_STATUS13 (0x8001c000 + 0x1e0)
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#define HWT_DIGCTL_1TRAM_STATUS13 HWIO_32_RW
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#define HWN_DIGCTL_1TRAM_STATUS13 DIGCTL_1TRAM_STATUS13
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#define HWI_DIGCTL_1TRAM_STATUS13
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#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE31 24
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#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31 0x1f000000
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#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) (((v) & 0x1f) << 24)
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#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31
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#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31_V(e) BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE31__##e)
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#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE31_V(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31
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#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE30 16
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#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30 0x1f0000
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#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) (((v) & 0x1f) << 16)
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#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30
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#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30_V(e) BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE30__##e)
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#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE30_V(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30
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#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE21 8
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#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21 0x1f00
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#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) (((v) & 0x1f) << 8)
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#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21
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#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21_V(e) BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE21__##e)
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#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE21_V(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21
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#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0
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#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0x1f
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#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) (((v) & 0x1f) << 0)
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#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20
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#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20_V(e) BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE20__##e)
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#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE20_V(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20
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#define HW_DIGCTL_SCRATCH0 HW(DIGCTL_SCRATCH0)
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#define HWA_DIGCTL_SCRATCH0 (0x8001c000 + 0x290)
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#define HWT_DIGCTL_SCRATCH0 HWIO_32_RW
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#define HWN_DIGCTL_SCRATCH0 DIGCTL_SCRATCH0
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#define HWI_DIGCTL_SCRATCH0
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#define BP_DIGCTL_SCRATCH0_PTR 0
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#define BM_DIGCTL_SCRATCH0_PTR 0xffffffff
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#define BF_DIGCTL_SCRATCH0_PTR(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_SCRATCH0_PTR(v) BM_DIGCTL_SCRATCH0_PTR
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#define BF_DIGCTL_SCRATCH0_PTR_V(e) BF_DIGCTL_SCRATCH0_PTR(BV_DIGCTL_SCRATCH0_PTR__##e)
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#define BFM_DIGCTL_SCRATCH0_PTR_V(v) BM_DIGCTL_SCRATCH0_PTR
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#define HW_DIGCTL_SCRATCH1 HW(DIGCTL_SCRATCH1)
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#define HWA_DIGCTL_SCRATCH1 (0x8001c000 + 0x2a0)
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#define HWT_DIGCTL_SCRATCH1 HWIO_32_RW
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#define HWN_DIGCTL_SCRATCH1 DIGCTL_SCRATCH1
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#define HWI_DIGCTL_SCRATCH1
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#define BP_DIGCTL_SCRATCH1_PTR 0
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#define BM_DIGCTL_SCRATCH1_PTR 0xffffffff
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#define BF_DIGCTL_SCRATCH1_PTR(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_SCRATCH1_PTR(v) BM_DIGCTL_SCRATCH1_PTR
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#define BF_DIGCTL_SCRATCH1_PTR_V(e) BF_DIGCTL_SCRATCH1_PTR(BV_DIGCTL_SCRATCH1_PTR__##e)
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#define BFM_DIGCTL_SCRATCH1_PTR_V(v) BM_DIGCTL_SCRATCH1_PTR
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#define HW_DIGCTL_ARMCACHE HW(DIGCTL_ARMCACHE)
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#define HWA_DIGCTL_ARMCACHE (0x8001c000 + 0x2b0)
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#define HWT_DIGCTL_ARMCACHE HWIO_32_RW
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#define HWN_DIGCTL_ARMCACHE DIGCTL_ARMCACHE
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#define HWI_DIGCTL_ARMCACHE
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#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
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#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300
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#define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) & 0x3) << 8)
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#define BFM_DIGCTL_ARMCACHE_CACHE_SS(v) BM_DIGCTL_ARMCACHE_CACHE_SS
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#define BF_DIGCTL_ARMCACHE_CACHE_SS_V(e) BF_DIGCTL_ARMCACHE_CACHE_SS(BV_DIGCTL_ARMCACHE_CACHE_SS__##e)
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#define BFM_DIGCTL_ARMCACHE_CACHE_SS_V(v) BM_DIGCTL_ARMCACHE_CACHE_SS
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#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
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#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30
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#define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) & 0x3) << 4)
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#define BFM_DIGCTL_ARMCACHE_DTAG_SS(v) BM_DIGCTL_ARMCACHE_DTAG_SS
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#define BF_DIGCTL_ARMCACHE_DTAG_SS_V(e) BF_DIGCTL_ARMCACHE_DTAG_SS(BV_DIGCTL_ARMCACHE_DTAG_SS__##e)
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#define BFM_DIGCTL_ARMCACHE_DTAG_SS_V(v) BM_DIGCTL_ARMCACHE_DTAG_SS
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#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
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#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3
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#define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) & 0x3) << 0)
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#define BFM_DIGCTL_ARMCACHE_ITAG_SS(v) BM_DIGCTL_ARMCACHE_ITAG_SS
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#define BF_DIGCTL_ARMCACHE_ITAG_SS_V(e) BF_DIGCTL_ARMCACHE_ITAG_SS(BV_DIGCTL_ARMCACHE_ITAG_SS__##e)
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#define BFM_DIGCTL_ARMCACHE_ITAG_SS_V(v) BM_DIGCTL_ARMCACHE_ITAG_SS
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#define HW_DIGCTL_SGTL HW(DIGCTL_SGTL)
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#define HWA_DIGCTL_SGTL (0x8001c000 + 0x300)
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#define HWT_DIGCTL_SGTL HWIO_32_RW
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#define HWN_DIGCTL_SGTL DIGCTL_SGTL
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#define HWI_DIGCTL_SGTL
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#define BP_DIGCTL_SGTL_COPYRIGHT 0
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#define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff
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#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) & 0xffffffff) << 0)
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#define BFM_DIGCTL_SGTL_COPYRIGHT(v) BM_DIGCTL_SGTL_COPYRIGHT
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#define BF_DIGCTL_SGTL_COPYRIGHT_V(e) BF_DIGCTL_SGTL_COPYRIGHT(BV_DIGCTL_SGTL_COPYRIGHT__##e)
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#define BFM_DIGCTL_SGTL_COPYRIGHT_V(v) BM_DIGCTL_SGTL_COPYRIGHT
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#define HW_DIGCTL_CHIPID HW(DIGCTL_CHIPID)
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#define HWA_DIGCTL_CHIPID (0x8001c000 + 0x310)
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#define HWT_DIGCTL_CHIPID HWIO_32_RW
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#define HWN_DIGCTL_CHIPID DIGCTL_CHIPID
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#define HWI_DIGCTL_CHIPID
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#define BP_DIGCTL_CHIPID_PRODUCT_CODE 16
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#define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000
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#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) & 0xffff) << 16)
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#define BFM_DIGCTL_CHIPID_PRODUCT_CODE(v) BM_DIGCTL_CHIPID_PRODUCT_CODE
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#define BF_DIGCTL_CHIPID_PRODUCT_CODE_V(e) BF_DIGCTL_CHIPID_PRODUCT_CODE(BV_DIGCTL_CHIPID_PRODUCT_CODE__##e)
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#define BFM_DIGCTL_CHIPID_PRODUCT_CODE_V(v) BM_DIGCTL_CHIPID_PRODUCT_CODE
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#define BP_DIGCTL_CHIPID_REVISION 0
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#define BM_DIGCTL_CHIPID_REVISION 0xff
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#define BF_DIGCTL_CHIPID_REVISION(v) (((v) & 0xff) << 0)
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#define BFM_DIGCTL_CHIPID_REVISION(v) BM_DIGCTL_CHIPID_REVISION
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#define BF_DIGCTL_CHIPID_REVISION_V(e) BF_DIGCTL_CHIPID_REVISION(BV_DIGCTL_CHIPID_REVISION__##e)
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#define BFM_DIGCTL_CHIPID_REVISION_V(v) BM_DIGCTL_CHIPID_REVISION
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#endif /* __HEADERGEN_STMP3600_DIGCTL_H__*/
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