617d1e9f6b
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30104 a1c6a512-1295-4272-9138-f99709370657
120 lines
3.7 KiB
C
120 lines
3.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "clkctrl-imx233.h"
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#define __CLK_CLKGATE (1 << 31)
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#define __CLK_BUSY (1 << 29)
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void imx233_enable_timrot_xtal_clk32k(bool enable)
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{
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if(enable)
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__REG_CLR(HW_CLKCTRL_XTAL) = HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE;
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else
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__REG_SET(HW_CLKCTRL_XTAL) = HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE;
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}
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void imx233_enable_clock(enum imx233_clock_t clk, bool enable)
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{
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volatile uint32_t *REG;
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switch(clk)
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{
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case CLK_PIX: REG = &HW_CLKCTRL_PIX; break;
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case CLK_SSP: REG = &HW_CLKCTRL_SSP; break;
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default: return;
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}
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/* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */
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if(enable)
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{
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*REG = (*REG) & ~__CLK_CLKGATE;
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while((*REG) & __CLK_CLKGATE);
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while((*REG) & __CLK_BUSY);
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}
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else
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{
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*REG |= __CLK_CLKGATE;
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while(!((*REG) & __CLK_CLKGATE));
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}
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}
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void imx233_set_clock_divisor(enum imx233_clock_t clk, int div)
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{
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switch(clk)
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{
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case CLK_PIX:
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__REG_CLR(HW_CLKCTRL_PIX) = HW_CLKCTRL_PIX__DIV_BM;
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__REG_SET(HW_CLKCTRL_PIX) = div;
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while(HW_CLKCTRL_PIX & __CLK_BUSY);
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break;
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case CLK_SSP:
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__REG_CLR(HW_CLKCTRL_SSP) = HW_CLKCTRL_SSP__DIV_BM;
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__REG_SET(HW_CLKCTRL_SSP) = div;
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while(HW_CLKCTRL_SSP & __CLK_BUSY);
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break;
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case CLK_CPU:
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__REG_CLR(HW_CLKCTRL_CPU) = HW_CLKCTRL_CPU__DIV_CPU_BM;
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__REG_SET(HW_CLKCTRL_CPU) = div;
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while(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__BUSY_REF_CPU);
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break;
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case CLK_AHB:
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__REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__DIV_BM;
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__REG_SET(HW_CLKCTRL_HBUS) = div;
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while(HW_CLKCTRL_HBUS & __CLK_BUSY);
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break;
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default: return;
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}
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}
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void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
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{
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/* NOTE: HW_CLKCTRL_FRAC only support byte access ! */
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volatile uint8_t *REG;
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switch(clk)
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{
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case CLK_PIX: REG = &HW_CLKCTRL_FRAC_PIX; break;
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case CLK_IO: REG = &HW_CLKCTRL_FRAC_IO; break;
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case CLK_CPU: REG = &HW_CLKCTRL_FRAC_CPU; break;
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default: return;
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}
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if(fracdiv != 0)
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*REG = fracdiv;
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else
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*REG = HW_CLKCTRL_FRAC_XX__CLKGATEXX;;
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}
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void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
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{
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uint32_t msk;
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switch(clk)
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{
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case CLK_PIX: msk = HW_CLKCTRL_CLKSEQ__BYPASS_PIX; break;
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case CLK_SSP: msk = HW_CLKCTRL_CLKSEQ__BYPASS_SSP; break;
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case CLK_CPU: msk = HW_CLKCTRL_CLKSEQ__BYPASS_CPU; break;
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default: return;
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}
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if(bypass)
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__REG_SET(HW_CLKCTRL_CLKSEQ) = msk;
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else
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__REG_CLR(HW_CLKCTRL_CLKSEQ) = msk;
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}
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