3a1127785b
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29053 a1c6a512-1295-4272-9138-f99709370657
137 lines
2.7 KiB
Text
137 lines
2.7 KiB
Text
#include "config.h"
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ENTRY(start)
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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STARTUP(target/arm/crt0-pp502x-bl-usb.o)
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#define DRAMORIG 0x01000000 /* Load at 16 MB */
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#define DRAMSIZE 0x00100000 /* 1MB for bootloader */
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#define MEMEND (MEMORYSIZE*0x100000) /* From virtual mapping at 0 */
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#define NOCACHE_BASE 0x10000000
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#ifndef IRAMORIG
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#define IRAMORIG 0x40000000
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#endif
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#define IRAMSIZE 0x20000
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#define FLASHORIG 0x001f0000
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#define FLASHSIZE 2M
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#define CACHEALIGN_SIZE 16
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MEMORY
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{
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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}
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SECTIONS
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{
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. = DRAMORIG;
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_loadaddress = . + NOCACHE_BASE;
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.text :
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{
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*(.init.text)
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*(.text*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(0x4);
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} > DRAM
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.rodata :
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{
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*(.rodata) /* problems without this, dunno why */
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*(.rodata*)
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*(.rodata.str1.1)
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*(.rodata.str1.4)
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. = ALIGN(0x4);
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} > DRAM
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.data :
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{
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*(.data*)
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. = ALIGN(0x4);
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} > DRAM
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/* .ncdata section is placed at uncached physical alias address and is
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* loaded at the proper cached virtual address - no copying is
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* performed in the init code */
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.ncdata . + NOCACHE_BASE :
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{
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. = ALIGN(CACHEALIGN_SIZE);
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*(.ncdata*)
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. = ALIGN(CACHEALIGN_SIZE);
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} AT> DRAM
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/DISCARD/ . - NOCACHE_BASE :
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{
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*(.eh_frame)
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} > DRAM
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_noloaddram = .;
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.ibss IRAMORIG (NOLOAD) :
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{
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_iedata = .;
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*(.qharray)
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*(.ibss)
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. = ALIGN(0x4);
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_iend = .;
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} > IRAM
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.iram _iend :
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{
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_iramstart = .;
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*(.icode)
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*(.irodata)
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*(.idata)
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_iramend = .;
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} > IRAM AT> DRAM
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_iramcopy = LOADADDR(.iram);
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.loadaddressend :
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{
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_loadaddressend = . + NOCACHE_BASE;
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} AT> DRAM
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.stack (NOLOAD) :
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{
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. = ALIGN(8);
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*(.stack)
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stackbegin = .;
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. += 0x2000;
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stackend = .;
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} > IRAM
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/* .bss and .ncbss are treated as a single section to use one init loop
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* to zero them - note "_edata" and "_end" */
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.bss _noloaddram (NOLOAD) :
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{
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_edata = .;
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*(.bss*)
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*(COMMON)
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} > DRAM
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.ncbss . + NOCACHE_BASE (NOLOAD) :
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{
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. = ALIGN(CACHEALIGN_SIZE);
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*(.ncbss*)
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. = ALIGN(CACHEALIGN_SIZE);
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} AT> DRAM
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/* This will be aligned by preceding alignments */
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.endaddr . - NOCACHE_BASE (NOLOAD) :
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{
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_end = .;
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} > DRAM
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/* Reference to all DRAM after loaded bootloader image */
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.freebuffer _end (NOLOAD) :
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{
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. = ALIGN(4);
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freebuffer = .;
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. = MEMEND-1;
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freebufferend = .;
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}
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}
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